DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0193565 A1 to Huang et al. (hereinafter “Huang” – previously cited reference).
Regarding claim 8, Huang discloses a semiconductor structure, comprising:
a first semiconductor unit which includes two first source/drain features spaced apart from each other in a first direction, and first channel features spaced apart from each other in a second direction different from the first direction, each of the first channel features extending between the two first source/drain features (first FET 102 having S/D regions 110 arranged apart in an X direction and having horizontal and vertical channel layer 122 portions arranged apart in an X-Z direction and between S/D regions 110 as shown in Fig. 1B; paragraphs [0025]-[0026]);
a second semiconductor unit stacked on the first semiconductor unit in the second direction (second FET 102 stacked upon first FET 102 in the X-Z direction; Fig. 1B; paragraphs [0025]-[0026]), the second semiconductor unit including two second source/drain features spaced apart from each other in the first direction, one of the two second source/drain features being stacked on one of the two first source/drain features and offset from the other of the two first source/drain features (second FET 102 having S/D regions 110 arranged apart in an X direction and stacked upon on S/D regions 110 of first FET 102 and offset therefrom Fig. 1B; paragraphs [0025]-[0026]), and second channel features spaced apart from each other in the second direction, each of the second channel features extending between the two second source/drain features (second FET 102 having horizontal and vertical channel layer 122 portions arranged apart in the X-Z direction and between S/D regions 110 as shown in Fig. 1B; paragraphs [0025]-[0026]);
a gate structure which includes a gate feature disposed around the first channel features and the second channel features, the gate feature being electrically conductive (gate structure including gate electrode 112B, padding layer 126, and conductive material layer 146 collectively form a gate feature which utilizes gate dielectric layers 112A respectively wrapped around channel regions 122 of each FET 102; Fig. 1B; paragraph [0028]), and having a first surface, a second surface which is opposite to the first surface in the second direction, and an interconnect surface which interconnects the first surface and the second surface (gate electrode 112B, padding layer 126, and conductive material layer 146 collectively form a gate feature which is disposed upon gate dielectric layer 112A and comprise first left surface, second right surface opposite left surface in the X-Z direction, and top/bottom surfaces connecting left and right outer surfaces as shown in Fig. 6; paragraphs [0028], [0033], [0035]), and a gate dielectric layer disposed to separate the gate feature from the first channel features and the second channel features (gate dielectric layers 112A isolate gate electrode 112B, padding layer 126, and conductive material layer 146 from channel regions 122; Fig. 1B; paragraph [0028]);
two gate spacers respectively located at two opposite sides of the gate structure in the first direction, the two gate spacers including a nitride-based material (gate spacers 114 disposed on opposing sides of the gate electrode 112B in the X direction and made from silicon nitride, for example; Fig. 1B; paragraphs [0028], [0031]); and
an electrically conductive capping feature which is in direct contact with one of the first surface and second surface of the gate feature, and which extends beyond the interconnect surface of the gate feature along a third direction different from the first direction and the second direction (conductive capping layer 142 contacting uppermost extent of left and right outer surfaces and vertically extending beyond the top surface in a Z direction as shown in Fig. 6; paragraph [0039]).
Huang fails to disclose a bottom surface of the second semiconductor unit is located entirely above a top surface of the first semiconductor unit.
However, if the FETs 102 of Huang are rotated 90 degrees, then this limitation would be disclosed by Huang. Therefore, it would have been obvious to have modified Huang to change the orientation of the FETs from horizontal to vertical stacking in order to potentially provide increased device density and reduced footprint, improved drive current, and increased electrostatic control. Further, such a modification would only involve reorientation of parts already disclosed by Huang as supported by MPEP 2144.04(VI)(C).
Regarding claim 9, Huang discloses the semiconductor structure of claim 8, wherein: the gate feature has a first length in the third direction; and the electrically conductive capping feature has a second length in the third direction which is greater than the first length (gate electrode 112B, padding layer 126, and conductive material layer 146 collectively have a top surface length in the Y direction, while conductive capping layer 142 is disposed over and fully encapsulates conductive material layer 146 in all directions; Fig. 6; paragraphs [0039], [0047]).
Regarding claim 10, Huang discloses the semiconductor structure of claim 9, wherein: the first semiconductor unit and second semiconductor unit are disposed distal from and proximate to the electrically conductive capping feature, respectively (FETs 102 are distal and adjacent conductive capping layer 142 as shown in Fig. 6); the semiconductor structure further comprises two contact features respectively disposed on the two second source/drain features (each FET 102 comprises trench conductor 130 respectively in contact with S/D regions 110 as shown in Fig. 6; paragraphs [0026], [0034], [0036], [0044), each of the two contact features having a contact surface in contact with a corresponding one of the two second source/drain features, and an opposite surface opposite to the contact surface (trench conductors 130 respectively in contact with S/D regions 110 and having opposite surface disposed away from S/D regions 110 as shown in Fig. 6; paragraphs [0026], [0034], [0036], [0044]); and an interface between the electrically conductive capping feature and the gate feature is located coincident with a reference surface which is located between the contact surface and the opposite surface of each of the first contact features (interfacial top surface between conductive capping layer 142 and conductive material layer 146 extends in an X direction between trench conductors 130 as shown in Fig. 6).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in further view of US 2022/0189870 A1 to Shin et al. (hereinafter “Shin” – previously cited reference).
Regarding claim 11, Huang discloses the semiconductor structure of claim 8, wherein: the interconnect surface of the gate feature has a first end region and a second end region opposite to each other in the third direction (S/D regions 110 are spaced apart in an X direction and top surface of gate feature has first and second ends along Y direction; Figs. 1A, 1B, 6; paragraphs [0025]-[0026]); the first surface and second surface of the gate feature are opposite to each other in the second direction (gate electrode 112B, padding layer 126, and conductive material layer 146 collectively have a top surface length in a Z direction; Fig. 6; paragraphs [0039], [0047]); and the electrically conductive capping feature includes a main portion which is adjacent the one of the first surface and the second surface of the gate feature, and a first extending portion which extends from the main portion beyond the first end region by a distance ranging from 2 nm to 20 nm (main body of conductive capping layer 142 contacting uppermost extent of left and right outer surfaces and having a horizontal extension EXT142 over layer of insulating material 144 ranging from about 0.1 nm to about 10 nm, where layer 144 is laterally adjacent to conductive material layer 146 as shown in Figs. 1B and 6; paragraph [0039]).
Huang fails to disclose a main portion which interfaces the one of the first surface and the second surface of the gate feature.
However, Shin discloses a main portion which interfaces the one of the first surface and the second surface of the gate feature (gate capping pattern GC having gate contact CB and interfacing left and right sides of gate electrode GE; Fig. 1B; paragraphs [0023]-[[0025], [0030]-[0031]).
Huang and Shin are both considered to be analogous to the claimed invention because they are in the same field of semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang to incorporate the teaching of Shin in order to potentially provide protection of the gate electrode, self-aligned via formation, prevention of electrical bridging, and reduced parasitic capacitance.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in further view of US 2022/0165857 A1 to Park et al. (hereinafter “Park” – previously cited reference).
Regarding claim 12, Huang discloses the semiconductor structure of claim 10, further comprising: two contact vias respectively disposed on the two first contact features (interconnect structures 140-1, 140-2 having vias 701, 703, 801 and disposed on trench conductors 130 as shown in Figs. 7C, 8 and 10; paragraphs [0053]-[0056]); and a gate via which is in direct contact with the first extending portion (vertical trench conductor 162 in direct contact with conductive capping layer 142 and portions extending beyond gate feature; Fig. 1B; paragraphs [0035]-[0036]).
Huang fails to disclose a gate via staggered from the two contact vias in both the first direction and the third direction.
However, Park discloses a gate via staggered from the two contact vias in both the first direction and the third direction (gate via contact 194 offset from source/drain via contact 192 to not be disposed on a straight line; paragraph [0072]).
Huang and Park are both considered to be analogous to the claimed invention because they are in the same field of semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang to incorporate the teaching of Park in order to potentially provide improved spacing, reduced parasitic capacitance, enhance manufacturability, and mitigation of electromigration and stress.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in further view of Shin and US 2016/0155839 A1 to Strachan et al. (hereinafter “Strachan” – previously cited reference).
Regarding claim 13, Huang in view of Shin discloses the semiconductor structure of claim 11. Huang further discloses wherein each of the first channel features and the second channel features has a first end and a second end which are opposite to each other in the third direction, and which are respectively proximate to the first end region and the second end region of the interconnect surface of the gate feature (channel regions 122 comprise first and second ends along Y direction and proximate to end regions of gate feature as shown in Fig 6).
Huang fails to disclose each of the first end and the second end being spaced apart from a corresponding one of the first end region and the second end region by a minimum distance ranging from 3 nm to 20 nm.
However, Strachan discloses each of the first end and the second end being spaced apart from a corresponding one of the first end region and the second end region by a minimum distance ranging from 3 nm to 20 nm (ends of the gate electrodes are separated from ends of the channel on the 10 nm scale; paragraph [0021]).
Huang and Strachan are both considered to be analogous to the claimed invention because they are in the same field of semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang to incorporate the teaching of Strachan in order to potentially provide reduced gate-to-channel capacitance, mitigation of short-channel effects, and reduced hot-carrier effects.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Huang in further view of US 2022/0199797 A1 to Naskar et al. (hereinafter “Naskar” – previously cited reference).
Regarding claim 14, Huang discloses the semiconductor structure of claim 8, wherein: a first proximate one of the first channel features is most proximate to the second channel features (channel regions 122 of FETs 102 are proximate to one another as shown in Fig. 6); a second proximate one of the second channel features is most proximate to the first channel features (channel regions 122 of FETs 102 are proximate to one another as shown in Fig. 6).
Huang fails to disclose the first proximate one of the first channel features is spaced apart from the second proximate one of the second channel features by a distance ranging from 10 nm to 50 nm.
However, Naskar discloses the first proximate one of the first channel features is spaced apart from the second proximate one of the second channel features by a distance ranging from 10 nm to 50 nm (separation between successive channel layers 104, 106 may be 10 nm; paragraph [0076]).
Huang and Naskar are both considered to be analogous to the claimed invention because they are in the same field of semiconductor structures. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Huang to incorporate the teaching of Naskar in order to potentially provide reduced parasitic capacitance between channels, mitigation of thermal crosstalk, and decreased channel-to-channel interference.
Allowable Subject Matter
Claims 1-7 and 15-20 are allowed. Specifically, regarding claim 1, Huang discloses some of the amended claim language related to the first and second dielectric fillers, i.e. dielectric materials 144, 148, that meet these particular limitations. However, Huang does not disclose the amended limitations of claim 1 in their totality. Claims 2-6 are allowable for depending upon an allowed claim. Further, regarding claim 15, Huang discloses some of the amended claim language related to the isolation portions on the protrusion, i.e. STI regions 138 on opposite sides of horizontal portion 108A. However, Huang does not disclose the amended limitations of claim 15 in their totality. Claims 16-20 are allowable for depending upon an allowed claim.
Response to Arguments
Applicant's arguments filed January 27, 2026 have been fully considered. Applicant submitted amendments to claims 1, 8 and 15 with corresponding arguments that these amended claims are allowable over the references cited. Examiner agrees in part that amended claims 1 and 15 are allowable. Moreover, Examiner agrees that amended claim 8 overcomes the previous 35 USC 102 rejection. However, claim 8 has been rejected on new grounds under 35 USC 103 that have not been preempted by Applicant in their Remarks.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818