Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The response of the applicant has been read and given careful consideration. The rejection of the previous action are withdrawn based upon the amendments to the claims. Responses to the arguments appear after the first rejection. This application has been assigned to a new examiner.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the claim should recite that the precursor includes “a metal and/or an element having an EUV cross section (sa) of greater than ….” and line 8 should replace “an element” with - - the element- -
Claim 1 should recite that the reactant is an - - oxygen reactant- - at line 6 as the oxide is formed. (see prepub at [0058])
Claim 1 at lines 9-10 should replace “a metal oxide underlayer” with –an oxide underlayer of the meal- -
Claims 1 should also recite that the metal oxide layer does not include the element.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 17 is rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Hu et al. CN 106025002
Hu et al. CN 106025002 (machine translation attached) in the abstract describes the invention claims an LED chip manufacturing method, comprising: a epitaxial wafer cleaning, a depositing a CBL electron blocking layer CBL electron blocking layer patterning, an evaporating an ITO transparent conductive layer, a depositing SiON film, ITO photoetching, the SiON etch patterning with phosphoric acid, etching patterning ITO, ITO patterned after removing glue (photoresist), ICP etching, ICP etching exposed N region, ICP etching, using phosphoric acid to remove the SiON, ITO alloy and depositing SiO2 protective layer. After depositing ITO, one layer of SiON is deposited on the ITO surface, so that the ITO etching, ITO etching patterning, ICP etching, ICP etching, ICP etching, removing photoresist after the five-step process of ITO film layer protected by the SiON, avoids the damage and pollution, improves the ITO film quality so as to improve the brightness of the LED chip, reducing the voltage.
The ITO is indium tin oxide film and one of the indium oxide or the tin oxide are considered the oxide of the EUV absorbing element as both have a cross section meeting the claims and trace elements, and the other of tin, tin oxide, indium or indium oxide is the dopant. The claims does not require the dopant to form an oxide. The SiON layer is a metal oxynitride (comprise an oxide which also contains nitrogen) Both of these comprise oxides.
The examiner notes that only claim 12 actually recites an EUV resist, which may limit the weight given to arguments relying upon unexpected result or the like.
The dopant level and material are not recited in the claims rejected under this heading, so the dopant can be any impurity present in the layer.
Claims 17 is rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Li. CN 105845580.
Li. CN 105845580 (machine translation attached) teaches a substrate with a gate structure, coating this with a silicon dioxide (SiO2) layer, sputtering on an ITO layer, coating the ITO layer with a resist (abstract)
The ITO is indium tin oxide film and one of the indium oxide or the tin oxide are considered the oxide of the EUV absorbing element as both have a cross section meeting the claims and trace elements, and the other of tin, tin oxide, indium or indium oxide is the dopant. The claims does not require the dopant to form an oxide. The silicon dioxide layer is a metal oxide.
Claims 17 is rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Fujimoto JP H1020511.
Fujimoto JP H1020511 in example 11 coats a silicon substrate with a 2000 angstrom ITO film, a 4000 angstrom silicon dioxide film and a 1 microns coating of a positive photoresist [0029].
The ITO is indium tin oxide film and one of the indium oxide or the tin oxide are considered the oxide of the EUV absorbing element as both have a cross section meeting the claims and trace elements, and the other of tin, tin oxide, indium or indium oxide is the dopant. The claims does not require the dopant to form an oxide. The silicon dioxide layer is a metal oxide.
Claims 17-19 are rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Ma et al. “High performance thin film transistors based on amorphous Al-N- co doped InZnO films prepared by RF magnetron sputtering”, J. Mat. Sci.:Mater Electronics Vol. 30 pp 9872-9876 (04/2019).
Ma et al. “High performance thin film transistors based on amorphous Al-N- co doped InZnO films prepared by RF magnetron sputtering”, J. Mat. Sci.:Mater Electronics Vol. 30 pp 9872-9876 (04/2019) describes sputtering from a ZnO-In2O3-Al2O3-Zn3N2) target to form a film on a p-type Si wafer with a thermally grown SiO2 layer (section 2)
Claims 17-19 are rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Hayashi et al. “42.1: Invited paper: improved amorphous In-Ga-Zn-O TFTs”, SID 08 digest pp 621-624 (2008).
Hayashi et al. “42.1: Invited paper: improved amorphous In-Ga-Zn-O TFTs”, SID 08 digest pp 621-624 (2008) illustrates a thin film transistor formed on a glass substrate with a gate electrode, including a silicon dioxide layer and an amorphous IGZO (indium-gallium-zinc oxide) layer.
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The intermediate product with the two layers is held to meet the claims, noting that the source and drain would have been photolithographically formed.
Claims 17-19 are rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Cho et al., “21.2: Al and Sn doped zinc indium oxide thin film transistors for AMOLED back plane”, SID 09 pp 280-283 (2009)
Cho et al., “21.2: Al and Sn doped zinc indium oxide thin film transistors for AMOLED back plane”, SID 09 pp 280-283 (2009) teaches a glass substrate with a gate electrode, an Al2O3 gate insulator, indium tin oxide (ITO) electrodes and an AT-ZINO (Al and Sn doped zinc indium oxide) layer, which is patterned.
The intermediate product with the two layers is held to meet the claims, noting that the patterning of the AT-ZIO layer would have been performed photolithographically.
Claim 16 is rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by JP 4230243.
JP 4230243 (machine translation attached) teaches with respect to the formation of a semiconductor device, coating an iridium layer, oxidizing the surface of the iridium layer (to form an iridium oxide layer) and then coating a Pb(ZrxTi1-x)O3 layer, this is then coated with an iridium oxide layer, a TiN film and a SiO hardmask which is patterned photolithographically (photoresist) [0048-0064+]
The Pb(ZrxTi1-x)O3 layer is considered a doped layer.
Claim 16 is rejected under 35 U.S.C. 10(a)(1) as being fully anticipated by Park et al. KR 20000038961
Park et al. KR 20000038961 (machine translation attached) teaches with respect to figure 5, a gate oxide film 20, a (doped) polysilicon layer 30, a lead oxide and a compound film 35 of lead and en-type oxides are deposited on the silicon substrate 10. The tungsten silicide layer 40 is formed by immediately depositing tungsten by conventional chemical vapor deposition without removing the compound film 35 on the top of the doped polysilicon film 30. Subsequently, anisotropic etching is performed to form a pattern of the gate electrode having the composite gate layer, and then a subsequent heat treatment is performed at about 600 ° C. so that the compound ions pass between the polysilicon grain boundaries of the doped polysilicon film 30. By suppressing the diffusion of W, F ions into the gate oxide film is suppressed or minimized. This method also has an effect of improving the operational reliability of the transistor device since the gate oxide film is less likely to be damaged.
Claims 1-5,8,11,13-14 and 17 are rejected under 35 U.S.C. 102(a)(2) as being fully anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Weidman et al. 20220342301.
Weidman et al. 20220342301 describes with respect to figure 1C to 1E, the formation of graded EUV resist films. These can be used in semiconductor processing as discussed at [0003,0029,0054,0110]. In figure 2A, the initial deposition of bismuth and tin precursors which react with water (oxygen source) to form an oxide where the process transitions during the deposition to a purely tin and water. Figure 2B is similar, but initially uses a combination of Te and Sn precursors which react with water which is graded to just the tin precursor and water at the top surface [0060-0066].
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The position of the examine is that one of ordinary skill in the art would immediately envision the formation of the graded metal oxide resists on a semiconductor wafer or other semiconductor substrate, thereby anticipating the claims as (sub)layers of differing compositions (SnO vs SnO + Te or Bi; SnO vs SnO + TerO or BiO) meet the . Oxide of tin, bismuth or tellurium can be considered to be the oxide of the high EUV absorbing element as these have an EUV cross section of more than 2 x 106 cm2/mole and the dopant can be trace elements in the layer, Bi, Sn, Te, TeO, SnO or BiO within the scope of the claims as the claims rejected under this heading do not describe the dopant level, dopant material or dopant properties.
The claims do not require the metal oxide to be different from the oxide of the element with the high EUV absorption. The claims also do not preclude the metal oxide layer from having the dopant. The (second) dopant can also be carbon, hydrogen or nitrogen entrapped in the layer.
If this position is not upheld, the examiner holds that it would have been obvious to one skilled in the art to form the graded resists using the processes disclosed at [00060-0066] on semiconductor wafers/substrate based upon the disclosures at [0003,0029,0054,0110] with a reasonable expectation of success.
While the specification describes these as underlayers for EUV resists, the claims rejected under this heading do not recite a photoresist and embrace the resists of Weidman et al. 20220342301 coated upon the semiconductor substrate.
Claims 1-5,8,11-14 and 17 are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Church et al. 20200152460.
Church et al. 20200152460 teaches with respect to figure 2, a substrate (20) having a graded hardmask (210) and a photoresist layer (24), where the hardmask matrix can include a gradient of high EUV absorbing materials, such as Sn, Te, Sb, Te, Cd, Cs and I. in one example the matrix includes silicon. In one embodiment, the graded hardmask matrix 110 includes tin (Sn). The Sn based graded hardmask matrix 110 includes the Sn gradient increasing from bottom to top. At the bottom the Sn is deposited as tin oxide (SnO) or tin nitride (SnN) for good adhesion to the bulk substrate 20 with the concentration of Sn increasing to have high Sn composition on the top surface directly under the photoresist layer 24. In one embodiment, the graded hardmask 22 can include a hardmask matrix 110, as shown in FIG. 3. The hardmask matrix 110 can include on a combination of vacuum co-deposited materials and will be vertically graded. Top materials 115 can include high EUV absorption cross sections, such as high-Z metals, metalloids and halogens, including but not limited to Sn, Sb, Te Cd, Cs, and I and derivatives thereof, with proven EUV absorptivity cross-section of at least 92 eV. Bottom materials 117 can act as seed layers to optimize the top layer closure and avoid a rough top surface or prevent intermixing or delamination with the bulk substrate 20. The selection of the top materials 115 and the bottom materials 117 permits tunable adhesion at both the bulk substrate 20 interface and the photoresist layer 24 interface. In one embodiment, the graded hardmask matrix 110 includes tin (Sn). The Sn based graded hardmask matrix 110 includes the Sn gradient increasing from bottom to top. At the bottom the Sn is deposited as tin oxide (SnO) or tin nitride (SnN) for good adhesion to the bulk substrate 20 with the concentration of Sn increasing to have high Sn composition on the top surface directly under the photoresist layer 24 [0043-0047,0062]. According to aspects of the present invention, a semiconductor device 10 can include a graded hardmask 22 formed thereon. The semiconductor device 10 can include a bulk substrate 20. The bulk substrate 20 can be a single substrate formed of a suitable semiconducting material, such as, e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), or any other suitable semiconducting group II, III, IV, V or VI material and combinations thereof. However, the bulk substrate 20 can also include multiple layers. For example, the bulk substrate 20 can include suitable semiconducting material, such as Si, SiGe, GaAs, InAs and other like semiconductors. Layered semiconductors such as Si/Ge and Semiconductor-On-Insulators (SOI) are also contemplated herein. Si-containing materials include, but are not limited to: Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulator substrates (SOI), SiGe-on-insulator (SGOI), annealed poly Si, and poly Si line structures. The Si-containing material can be the substrate of the device, or a Si-containing layer formed atop the substrate, e.g., a polySi gate or a raised source/drain region. The bulk substrate 20 can include any structures formed therein [0041-0042].
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With respect to claims 1-5,11-14 and 17, The position of the examiner is that one of ordinary skill in the art would immediately envision, the embodiments illustrated in figures 2 or 3 where the {sub)layers are SnO with different amounts of a dopant (silicon) to reduce the percentage of SnO at different distances in the thickness, thereby anticipating claimed invention. The claims do not require the metal oxide to be different from the oxide of the element with the high EUV absorption. The claims also do not preclude the metal oxide layer from having the dopant.
The claims do not require the metal oxide to be different from the oxide of the element with the high EUV absorption. The claims also do not preclude the metal oxide layer from having the dopant or require that the dopant be an oxide. The (second) dopant can also be carbon, hydrogen or nitrogen entrapped in the layer.
With respect to claims 1-5,8,11-14 and 17, if this position is not upheld the examiner holds that it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of SnO in combination with another element, such as silicon disclosed at [0043-0047,0062] which is a dopant which forms a matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
Claim 16 is rejected under 35 U.S.C. 103 as obvious over JP 4946214
JP 4946214 teaches in the process of forming a semiconductor device, coating a conductive film (23) of a Pt, PtO, IrOx, SrRuO3 of the like, followed by the formation of a perovskite PbZrTiO3 film (24) [0065-0066].
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It would have been obvious to one skilled in the art to form the conductive layer of PtO or IrOx with a reasonable expectation of forming a useful device.
Claims 1-8,11-14,17 and 19 are rejected under 35 U.S.C. 103 as obvious over Church et al. 20200152460.
Alternatively with respect to claims 1-5,8,11-14 and 17, it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of TeO, SbO or CdO in combination with another element, such as silicon disclosed at [0043-0047,0062] which is a dopant which forms a matrix with a reasonable expectation of forming a useful structure ready for EUV exposure. The (second) dopant can also be carbon, hydrogen or nitrogen entrapped in the layer.
Alternatively with respect to claims 1-6,8,11-14 and 16-17, it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of CsO in combination with another element, such as silicon disclosed at [0043-0047,0062] which is a dopant which forms a matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
Alternatively with respect to claims 1-5,8,11-14 and 17 it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of IO in combination with another element, such as Sn, SnO or silicon disclosed at [0043-0047,0062] which is a dopant which forms a matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
Claims 1-6,8 and 11-17 are rejected under 35 U.S.C. 103 as obvious over Church et al. 20200152460, in view of Tan et al. 20220035247.
Tan et al. 20220035247 teaches that hardmask materials can include any of a variety of materials, including amorphous carbon (a-C), tin oxide (e.g., SnO.sub.x), silicon oxide (e.g., SiO.sub.x, including SiO.sub.2), silicon oxynitride (e.g., SiO.sub.xN.sub.y), silicon oxycarbide (e.g., SiO.sub.xC.sub.y), silicon nitride (e.g., Si.sub.3N.sub.4), titanium oxide (e.g., TiO.sub.2), titanium nitride (e.g., TiN), tungsten (e.g., W), doped carbon (e.g., W-doped C), tungsten oxide (e.g., WO.sub.x), hafnium oxide (e.g., HfO.sub.2), zirconium oxide (e.g., ZrO.sub.2), and aluminum oxide (e.g., Al.sub.2O.sub.3). Suitable substrate materials can include various carbon-based films (e.g., ashable hardmask (AHM), silicon-based films (e.g., SiO.sub.x, SiC.sub.x, SiO.sub.xC.sub.y, SiO.sub.xN.sub.y, SiO.sub.xC.sub.yN.sub.z), a-Si:H, poly-Si, or SiN), or any other (generally sacrificial) film applied to facilitate the patterning process) [0198] In other implementations, the underlayer may be vapor deposited on the substrate by PECVD or ALD using a Si-containing precursor that co-reacts with an oxidizer (e.g., an oxocarbon, an O-containing precursor, CO, or CO.sub.2). In variations on this implementation, the Si-containing precursor further co-reacts with a C source dopant (e.g., a hydrocarbon precursor, as described herein). Non-limiting Si-containing precursors are described herein, such as silanes, halosilanes, aminosilanes, alkoxysilanes, organosilanes, etc [0075].
Church et al. 20200152460 does not exemplify the embodiments where the graded hard mask includes a metal oxide other than SnO and arguably SiO
With respect to claims 1-6,8,11-14 and 16-17, it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of SnO of Church et al. 20200152460 in combination with silicon dioxide based upon the disclosure of Si in Church et al. 20200152460 at [0043-0047,0062] and SiOx as a hardmask material in Tan et al. 20220035247 at [0075] where the SiOx forms the matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
Alternatively it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of TeO, SbO, CdO or CsO in combination with silicon dioxide based upon the disclosure of Si in Church et al. 20200152460 at [0043-0047,0062] and SiOx as a hardmask material in Tan et al. 20220035247 at [0075] where the SiOx forms the matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
Alternatively it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of IO in combination with another element, such as Sn, SnO or silicon dioxide based upon the disclosure at [0043-0047,0062] of Church et al. 20200152460 at [0043-0047,0062] and SiOx as a hardmask material in Tan et al. 20220035247 at [0075] where the SiOx forms the matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
With respect to claims 1-6,8 and 11-17 , it would have been obvious to produce the embodiments taught with respect to figures 2 or 3 by forming the graded or multilayer of TeO, SbO, CdO or CsO in combination with silicon dioxide based upon the disclosure of Si in Church et al. 20200152460 at [0043-0047,0062] and SiO.sub.xC.sub.y as a hardmask material in Tan et al. 20220035247 at [0075] where the SiOx forms the matrix with a reasonable expectation of forming a useful structure ready for EUV exposure.
Claims 1-14 and 16-20 are rejected under 35 U.S.C. 103 as obvious over Weidman et al. 20220342301, in view of Kanakasbapahty et al. WO 2021202198
Kanakasbapahty et al. WO 2021202198 teaches with respect to figure 2B, the deposition of the resist (222) on the substrate and treatment of the resist during a post application bake (PAB) with the EUV sensitizer which will (hyper) sensitize the top surface of the photoresist [0095-0103]. Useful EUV sensitizers include Xe and iodide [0107]. EUV resist materials includes tin oxide, tellurium oxide, bismuth oxide, antimony oxide, indium oxide or oxides of these alloys [0111]. These can be formed using atomic layer deposition in the disclosed precursors, which may include Sn, Bi, Te, Cs, Sb, In, Mo, Hf, I, Zr, Fe, Co, Ni, Cu, Zn, Ag, Pt, Pb [0117-0144 , particularly 0121]. These are reacted with counter reactants to form the compounds and the counter reactants include oxygen, ozone, water, peroxides, alcohols, acids hydroxy sources [0145].
In addition to the basis above, it would have been obvious to one skilled in the art to modify the embodiments anticipated or rendered obvious by Weidman et al. 20220342301 by adding any Cs, Sb, In, Hf, I, Fe, Co, Ni, Cu, Zn, Ag, Pt, Pb to the EUV resist compositions based upon the disclosure of Kanakasbapahty et al. WO 2021202198 at [0117-0144 , particularly 0121] with a reasonable expectation of forming a useful graded resist.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
NAGABHIRAVAet al. WO 2021173557 in figure 3A illustrates a substrate 200 having ultra-low k dielectric lay er 315, silicon nitride layer 314, titanium nitride layer 313, oxide layer 312, organic planarization layer 311, and multi-layer hardmask 202 having upper layer 202a and lower layer 202b. Example ultra-low k dielectric materials include, e.g., various versions of SiCOH. In some cases, the titanium nitride layer 313 may further include oxygen such that it is a titanium oxynitride layer. The oxide layer 312 may be a TEOS-based oxide layer in certain embodiments (e.g., a silicon oxide layer). The substrate 200 of FIG. 3A may be formed through the process flow described in FIG. 1 (e.g., operations 101-111, or a subset thereol) and FIGS. 2A-2G. For the sake of brevity, the description will not be repeated. The substrate 200 of FIG. 3 A is analogous to the substrate 200 of FIG. 2G, with the underlying material 201 of FIG. 2G corresponding to layers 311, 312, 313, 314, and 315 of FIG. 3 A. [0055] After the recessed features 204 are transferred into both the upper layer 202a and the lower layer 202b of the multi-layer hardmask 202, as shown in FIG. 3A [0054]. The hardmask includes at least an upper layer and a lower layer. The upper layer of the hardmask includes a metal-containing material. Example metal-containing materials include metal oxides, metal nitrides, and metal oxynitrides. The metal in the metal-containing material may include titanium, tantalum, hafnium, tin, zinc, molybdenum, ruthenium, etc., as well as combinations thereof. As such, the upper layer of the hardmask may include, for example, titanium oxide, titanium nitride, titanium oxynitride, tantalum oxide, tantalum nitride, tantalum oxynitride, hafnium oxide, hafnium nitride, hafnium oxynitride, tin oxide, tin nitride, tin oxynitride, ruthenium oxide, ruthenium nitride, ruthenium oxynitride, etc. The metal -containing material of the upper layer of the hardmask provides secondary electron generation during an EUV lithography exposure. This secondary electron generation is beneficial because it reduces the amount of resist scum that forms during exposure, thus improving the degree to which the features are adequately opened. Further, the secondary electron generation during EUV exposure provides a dose-to-size benefit, meaning that the same degree of EUV resist removal can be accomplished at a lower exposure dose due to increased electron generation from the metal-containing material of the upper layer of the hardmask. Another benefit associated with the disclosed hardmask is that the metal-containing material in the upper layer of the hardmask enables adhesion of the EUV resist directly on the upper layer of the hardmask, without the use of an additional organic adhesion layer [0030]. The lower layer of the hardmask includes an inorganic dielectric silicon- containing material. Example silicon-containing materials include, but are not limited to, amorphous silicon (e.g., a-Si), silicon oxide, silicon carbide, silicon oxycarbide, silicon nitride, and silicon oxynitride. The lower layer of the hardmask provides excellent selectivity with respect to the underlying layers during pattern transfer. This high degree of selectivity ensures high quality pattern transfer, substantially reducing the amount of shorts that form and increasing yield, as compared to what is achieved with conventional hardmasks [0032]. FIGS. 2A-2H depict a partially fabricated semiconductor substrate as it undergoes the method shown in FIG. 1 [0034]
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See also [0188].
Singh et al. 20210033974 teaches EUV resist with underlayers, including metal oxide underlayer (206) and a metal oxide resist [0036-0037].
Weidman et al. WO 2020264557 teaches a resist where the initially Te and Sn precursors are reacted with water, but as the deposition continues, the relative amounts of Te:Sn decreases [0062]
Liang et al. WO 2020232329 teaches resist underlayer 2, which is Si or SiON , underlayer 2, which is Sn or SnO2 and a photoresist [0056]
Shamma et al. 20180337046 teaches with respect to figure 1A multiple resist underlayers including hardmasks (115 and 117) [0068]. In various embodiments, the second hard mask material is a tin-containing material such as tin oxide or tin(II) oxide (SnO), stannic oxide or tin(IV) oxide (SnO.sub.2) [0024]. The third hard mask is any one or more of silicon oxynitride, silicon-containing anti-reflective coating material, spin-on glass, bottom anti-reflective coating material, tin oxide, tin nitride, tin sulfide, lead oxide, lead nitride, and lead sulfide. [0025]. In various embodiments, the first hard mask material is selected from the group consisting of photoresist and spin-on carbon [0030] The first hard mask may be a carbon-containing, silicon-containing, or tin-containing material. In some embodiments, the first hard mask is a carbon-containing material, such as amorphous carbon or spin-on carbon, or may be a photoresist. In some embodiments, the first hard mask is a silicon-containing material, such as amorphous silicon. In some embodiments, the first hard mask is a tin-containing material, such as tin oxide or tin nitride. While the first hard mask material is referred to as a “hard mask material” it will be understood that in many embodiments, the first hard mask material is photoresist [0095]. For example, the layer immediately adjacent to and underlying the first hard mask layer may have the same composition as the first hard mask. This layer is referred to herein as the “adjacent underlayer.” The adjacent underlayer may have different composition from the first hard mask. In some embodiments, the layer immediately adjacent to and underlying the first hard mask may both contain carbon but may be deposited by different techniques. In some embodiments, the adjacent underlayer is silicon oxynitride, or silicon-containing anti-reflective coating (SiARC), or spin-on glass, or bottom anti-reflective coating (BARC). In various embodiments, the adjacent underlayer is a tin-containing film, such as tin oxide, or tin nitride, or tin sulfide. In some embodiments the adjacent underlayer includes lead oxide, or lead nitride or lead sulfide, or combinations thereof. Where the adjacent underlayer is tin oxide, less second hard mask material as described below with respect to operation 312 may be deposited in each cycle (which may be performed in the same chamber, or the same tool, or without breaking vacuum) because directional etching can be performed without damaging the tin oxide adjacent underlayer in features that already have a desired depth and/or aspect ratio, thereby achieving etch selectivity while continuing to etch features that are partially defined until such features have the same depth and/or aspect ratio of other features on the substrate, or until variability of depth and/or aspect ratio of features across a wafer is reduced [0099].
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Smith et al. 20180308687 teaches SiO.sub.2 can be selectively deposited on a silicon substrate in the feature by thermal ALD using a monoamine silane precursor with O.sub.3 as an oxidizing agent. Or HfO.sub.2 can be selectively deposited on a silicon oxide substrate, e.g., a hardmask in the feature by thermal ALD using a hafnium amide with water as an oxidant [0047].
Belyansky et al. 9929012 teaches with respect to figure 1, a substrate (16), an underlayers (14), an interface hardmask layer (12) and an EUV photoresist. In accordance with a non-limiting embodiment of this invention there is provided a method to prepare a substrate for photolithography. The method comprises forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. In the performance of the method the interface hardmask layer is comprised of at least one of Me; MeO; MeC; MeCO; MeN; MeON; and MeCON, where Me stands for a transition metal, and where N is nitrogen, O is oxygen and C is carbon. In the performance of the method the interface hardmask layer is comprised of at least one of Ti, Al, Ta, Cu, W, Ga, Mn, Co, Hf, La and other metals with higher Z number, oxides of these metals, carbides of these metals, nitrides of these metals and silicides of these metals (col 2/lines 7-27). The EUV resist 10 is deposited on top of the tuned surface of the interface hardmask layer 12. As employed herein ‘tuning’ the surface of the interface layer refers to controlling material properties and/or the composition of the interface hardmask layer 12 to establish a certain desired secondary electron yield at the interface layer. In accordance with some non-limiting embodiments of this invention the interface hardmask layer 12 can be comprised of at least one of Me; MeO; MeC; MeCO; MeN; MeON; and MeCON, where Me stands for a transition metal (i.e., the 38 elements in groups 3 through 12 of the periodic table), and where N is nitrogen, O is oxygen and C is carbon. Non-limiting examples of suitable transition metals include, but are not limited to: Ti, Al, Ta, Cu, W, Ga, Mn, Co, Hf; La and other metals with higher Z number. In accordance with some further non-limiting embodiments of this invention the interface hardmask layer 12 can be comprised of; where applicable, oxides of these metals, carbides of these metals, nitrides of these metals and silicides of these metals. The thickness of the interface hardmask layer 12 can be in an exemplary range of about 1 nm to about 10 nm; although thinner or thicker interface hardmask layer layers can be employed. The interface hardmask layer 12 can be deposited by any deposition process suitable for forming a thin material layer, for example, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD). Preferably the interface hardmask layer 12 is deposited at a (relatively) low temperature (typically <300° C.) to avoid melting, deformation and/or outgassing of the underlying layer 14 of; for example, OP (4/412-5/4). In another non-limiting example surface modification of the interface hardmask layer 12 can be achieved by ion implantation (or a combination of implantation and other treatments, such as a low temperature anneal) of materials with higher secondary electron yields. For example, a film composed of a pure transition metal can be implanted by a variety of species (e.g., oxygen, carbon, nitrogen, or silicon) to modify the composition of just the top surface layer or completely through the metal layer thickness depending on implant dose and energy. Implantation can typically be performed at room temperature. After implantation the film can be annealed at a temperature of up to about 500° C. to ensure both the reaction of the metal with the implanted species and the stability of the underlayer 14. The end result is the formation of the interface hardmask layer 12 having the desired properties. The anneal duration can range from seconds to hours depending on the metal and a desired thickness of the oxidized surface layer (Me.sub.xO.sub.y) (5/45-62)
Liang et al. 20200004155 teaches with respect to figure 1B, a substrate (140), an underlayer (151), an interface layer (152) and a resist (153) . The underlayer 151 can have a relatively high radiation extinction coefficient, given the type of photolithography at issue. For example, for EUV photolithography, the underlayer 151 can have a radiation extinction coefficient of at least 0.02 at EUV wavelengths. The underlayer 151 can also have a relatively high radiation absorption percentage (e.g., a 25% or more radiation absorption percentage at EUV wavelengths for a 10 nm thick film). Those skilled in the art will recognize that the radiation absorption percentage will depend, not only on the type of material used for the underlayer but also the thickness. Additionally, the material of the underlayer 151 can be selected, given the material of the photoresist layer 153, in order to achieve particular positive valence and conduction band offsets between the different materials that create (i.e., internally generate) an effective electric field 160 between the underlayer 151 and the photoresist layer 153 (i.e., cause the multi-layer stack to be “self-biased”). As mentioned above, the “self-biased” state refers to a state where, due to the materials of the different layers 151 and 153, an effective electric field is internally generated within the multi-layer stack 150 and, more particularly, a specific electromotive force (EMF) is internally generated within the multi-layer stack 150. These exemplary materials are relatively wide band gap semiconductors and include indium(III) oxide (In.sub.2O.sub.3), nickel(II) oxide (i.e., NiO), zinc oxide (ZnO), copper(I) oxide (Cu.sub.2O), cobalt (III) oxide (Co.sub.2O.sub.3), hafnium(IV) oxide (HfO.sub.2), and chromium (III) oxide (Cr.sub.2O.sub.3). It should be noted that in the graph of FIG. 2A, silicon dioxide and silicon are shown as references. Optionally, the underlayer 151 can also be doped with oxygen vacancies, interstitial cation or anion elements, or other implantation materials for higher p-type conductivity within the underlayer 151. For example, optionally, the underlayer 151 can be doped with dopants including, but not limited to, any one or more of the following: zinc (Zn), antimony (Sb), arsenic (As), and/or phosphorus (P) with an implantation energy ranging from 0.5 keV to 3 keV and a dose from 1E12/cm2 to 1E16 ions/cm2 . More specifically, in embodiments disclosed herein, the desired positive valence and conduction band offsets in the “self-biased” multi-layer stack 150 and, thereby the effective electric field 160, can be achieved by creating a p-n junction at the interface between the underlayer 151 and the photoresist layer 153. That is, the underlayer 151 can be a p-type underlayer and the photoresist layer 153 can be an n-type photoresist layer. The p-type underlayer can be a wide band gap p-type semiconductor layer. For example, the p-type underlayer could be a nickel(II) oxide (i.e., NiO) layer or a copper(I) oxide (Cu.sub.2O) layer that is doped with interstitial oxygen and/or has cation vacancies so that the underlayer has the desired p-type conductivity. Alternatively, the p-type underlayer could be a zinc oxide (ZnO) layer doped with zinc (Zn), antimony (Sb), arsenic (As), and/or phosphorus (P) vacancies as acceptors so that the underlayer has the desired p-type conductivity. The n-type photoresist layer could be a chemically amplified positive organic photoresist layer, which is either doped to achieve the desired n-type conductivity or which naturally has the desired n-type conductivity. Alternatively, the n-type photoresist layer can be a chemically amplified negative organic photoresist layer or a non-chemically amplified photoresist layer that naturally has the desired n-type conductivity [0029-0041]. As mentioned above, optionally the underlayer 151 can also be doped with oxygen vacancies, interstitial cation or anion elements or other implantation materials for higher conductivity. For example, optionally, the underlayer 151 can be doped with dopants including, but not limited to, any one or more of the following: zinc (Zn), antimony (Sb), arsenic (As), and/or phosphorus (P) with an implantation energy ranging from 0.5 keV to 3 keV and a dose from 1E12/cm2 to 1E16 ions/cm2. These oxygen vacancies, interstitials or dopants, if present, can increase p-type conductivity of the underlayer, ideally creates a p-n junction at the interface between the underlayer and the photoresist layer that helps the movement of radiation-excited electrons (e.sup.−) from the underlayer 151 to the radiation-exposed areas 154 of the photoresist layer 153. Such an increase in electrons (e.sup.−) within the exposed areas 154 of the photoresist layer 153 will improve the efficiency of the photoreaction between the radiation 590 and the photoresist material within the radiation-exposed areas 154 of the photoresist layer 153. It should be understood that if a n-p junction were to be created at this interface (i.e., if the underlayer were to have an n-type conductivity and the photoresist layer were to have p-type conductivity) undesirable electrons movement would occur from the photoresist layer into the underlayer [0055]. There can be a hardmask layer (142)and can be silicon nitride [0043,0059]
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MARTIN J. ANGEBRANNDT
Primary Examiner
Art Unit 1737
/MARTIN J ANGEBRANNDT/Primary Examiner, Art Unit 1737 February 18, 2026