DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to the rejections in the previous Office action have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-10, 12-16, and 18-23 are rejected under 35 U.S.C. 103 as being unpatentable over I-Wen Wu et al. (US 20230377943 A1; hereinafter Wu) in view of Wei Hong et al. (US 20200105584 A1; hereinafter Hong) and Jun Kanamori (US 20040087103 A1; hereinafter Kanamori).
Regarding Claim 1, Wu teaches a method, comprising:
providing a plurality of gates (Fig. 3; gates 212 comprising spacers 214; ¶0018-¶0019) in a stack of layers (in stack of layers of Fig. 3), wherein each gate of the plurality of gates comprises a sidewall spacer (214; as shown in Fig. 3);
forming a mask (Fig. 5; 226; ¶0023) over the stack of layers, wherein an opening (228; ¶0023) through the mask (226) exposes a dummy gate (212b; ¶0018) of the plurality of gates, wherein a width of the dummy gate (212b comprising sidewall spacers 214) aligns with a width of the opening (228) (as shown in Fig. 3);
removing a gate material (of 212b) of the dummy gate to form a recess (232) (as shown in Fig. 7), wherein the recess (232) exposes a silicon-on-insulator (SOI) layer of the stack of layers (wherein 202 in area 205C is the SOI layer {active layer} as it is the channel for the transistors; ¶0015-¶0016), and wherein the gate material is etched selective to the sidewall spacer (214) to expose the sidewall spacer (214) of the dummy gate (212b) (as shown in Fig. 7 and ¶0024);
forming an isolation structure (235; ¶0026) in the recess (232) (Fig. 9),
wherein a bottom surface of the recess is a top surface of the SOI layer exposed by the recess (bottom of recess 232 in Fig. 7 is the top surface of the SOI layer which is the active layer in the channel region 205C of the SOI substrate 202).
Wu does not expressly disclose forming the isolation structure comprises using an oxidation process in the SOI layer within the recess to form an isolation area and forming a fill material atop the isolation area.
In the same field of endeavor Hong teaches a similar method comprising providing a plurality of gates (Fig. 1; gate structures 16; ¶0022) in a stack of layers (Fig. 1; 16 are in a stack of layers 12, 14, 15, 19), wherein each gate (16) of the plurality of gates comprises a sidewall spacer (Fig. 1; sidewall spacer 16e; ¶0023);
forming a mask (Fig. 1; mask layer includes 20, 22, and 24; as described in ¶0025 and ¶0027; which combined make a mask to define the width of the opening recess to be formed) over the stack of layers (as shown in Fig. 1), wherein an opening through the mask exposes a dummy gate (Fig. 1 to Fig. 3; dummy gate 16a; ¶0022) of the plurality of gates (16) (as shown in Fig. 2 and Fig. 3 and described in ¶0028; wherein an opening recess 26 is formed by a timed etching process that implicitly exposes the dummy gate 16a);
removing a gate material (Fig. 2; gate material 16c; ¶0023) of the dummy gate (16a) to form a recess (Fig. 3; recess 26 and as described in ¶0028), wherein the recess (26) exposes a silicon-on-insulator (SOI) layer (Fig. 3; 15; ¶0021) of the stack of layers (as shown in Fig. 3; wherein the SOI layer 15 is exposed by the opening recess 26 by removing the gate material 16c); wherein a bottom surface of the recess (bottom of 26) is a top surface of the SOI layer exposed by the recess (bottom of recess 26 in Fig. 3 is the top surface of the SOI layer 15); and
forming an isolation area by an oxidation process (Fig. 4 and as described in ¶0029; the channel region 28 in the SOI layer 15 undergoes an oxidation process to provide an isolation area between components) and forming a fill material (Fig. 6; 30; ¶0032) atop the isolation area.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps above of Hong in the method of Wu in order to provide device isolation to reduce overall leakage and design area while allowing different voltages on the drains and preventing stress loss in the SOI layer (Hong; ¶0018).
Modified Wu does not expressly disclose the oxidation process comprises implanting oxygen ions into the recess and annealing the SOI layer within the recess to form the isolation area.
In the same field of endeavor, Kanamori teaches a method of forming fine patterned isolation regions (Kanamori; ¶0009-¶0010) particularly advantageous to FD-SOI substrates/devices (Kanamori; ¶0025).
Kanamori’s method comprises forming a mask layer (Kanamori; Fig. 1A; 110+112) over a FD-SOI substrate (Kanamori; Fig. 1A; 100; ¶0022) with an opening exposing the area to be isolated (as shown in Kanamori Fig. 1A); followed by implanting oxygen ions into the opening (as shown in Fig. 1A and described in ¶0022) and annealing the SOI layer (Kanamori; Fig. 1A; 106; ¶0022-¶0023; wherein the field oxidation process is an annealing process) to form an isolation area (Kanamori; Fig. 1B; 116; ¶0023).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the oxygen implant method of Kanamori for the oxidation method of modified Wu. One of ordinary skill in the art would have motivation to make this modification because Kanamori teaches the oxidation process is good for avoiding the degradation of FD-SOI devices caused by shallow trench isolation/etching methods (Kanamori; ¶0006) while providing finely patterned and adequate isolation areas between active regions (Kanamori; ¶0014) which is particularly advantageous to FD-SOI devices (Kanamori; ¶0025).
Regarding Claim 2, modified Wu teaches the method of claim 1, further comprising forming a fill material (Hong; 30) within the recess (Hong; 26).
Regarding Claim 3, modified Wu teaches the method of claim 2, wherein the fill material (30) is formed atop the isolation area (oxidized channel region 28) (as modified by Hong Fig. 6).
Regarding Claim 4, modified Wu teaches the method of claim 1, wherein the isolation area (as modified by Hong, oxidized channel region 28) is formed within the SOI layer (15).
Regarding Claim 8, modified Wu teaches the method of claim 1, further comprising forming the stack of layers by (as modified by Hong): forming a buried oxide layer (Hong; Fig. 1; 14; ¶0021) over a silicon substrate (Hong; Fig. 1; 12; ¶0021), wherein the SOI layer (Hong; Fig. 1; 15; ¶0021) is formed over the buried oxide layer (14) (as shown in Hong Fig. 1); and forming an oxide layer (Hong; Fig. 1; 19; ¶0024 which can be deposited by CVD) over the SOI layer (15) (as shown in Hong Fig. 1).
Hong as modified does not expressly disclose that the oxide layer 19 is a silicon oxide layer. In the same field of endeavor, Kanamori teaches forming a silicon oxide film (Kanamori; Fig. 1A; 108; ¶0022) over the SOI layer (Kanamori; 106) that can be deposited by CVD (Kanamori; ¶0036).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the silicon oxide of Kanamori for the oxide layer in Hong to form the SOI of Wu because the substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 9, Wu teaches a method of forming an isolation area in a silicon-on- insulator (SOI) device (¶0015), the method comprising:
forming a plurality of gates (Fig. 3; gates 212 comprising spacers 214; ¶0018-¶0019) in a stack of layers (in stack of layers of Fig. 3), wherein each gate of the plurality of gates comprises a sidewall spacer (214; as shown in Fig. 3) along a gate material (material of gate 212; ¶0018);
forming a mask (Fig. 5; 226; ¶0023) over the stack of layers, wherein an opening (228; ¶0023) through the mask (226) exposes a dummy gate (212b; ¶0018) of the plurality of gates, wherein a width of the dummy gate (212b comprising sidewall spacers 214) aligns with a width of the opening (228) (as shown in Fig. 3);
etching the gate material (of 212b) of the dummy gate to form a recess (232) (as shown in Fig. 7; etching ¶0024), wherein the recess (232) exposes a SOI layer of the stack of layers (wherein 202 in area 205C is the SOI layer {active layer} as it is the channel for the transistors; ¶0015-¶0016), and wherein the gate material is removed selective to the sidewall spacer (214) to expose the sidewall spacer (214) of the dummy gate (212b) (as shown in Fig. 7 and ¶0024);
forming an isolation structure (235; ¶0026) in the recess (232) (Fig. 9),
wherein a bottom surface of the recess is a top surface of the SOI layer exposed by the recess (bottom of recess 232 in Fig. 7 is the top surface of the SOI layer which is the active layer in the channel region 205C of the SOI substrate 202).
Wu does not expressly disclose forming the isolation structure comprises using an oxidation process of the SOI layer within the recess to form an isolation area and forming a fill material atop the isolation area.
In the same field of endeavor Hong teaches a similar method comprising providing a plurality of gates (Fig. 1; gate structures 16; ¶0022) in a stack of layers (Fig. 1; 16 are in a stack of layers 12, 14, 15, 19), wherein each gate (16) of the plurality of gates comprises a sidewall spacer (Fig. 1; sidewall spacer 16e; ¶0023);
forming a mask (Fig. 1; mask layer includes 20, 22, and 24; as described in ¶0025 and ¶0027; which combined make a mask to define the width of the opening recess to be formed) over the stack of layers (as shown in Fig. 1), wherein an opening through the mask exposes a dummy gate (Fig. 1 to Fig. 3; dummy gate 16a; ¶0022) of the plurality of gates (16) (as shown in Fig. 2 and Fig. 3 and described in ¶0028; wherein an opening recess 26 is formed by a timed etching process that implicitly exposes the dummy gate 16a);
removing a gate material (Fig. 2; gate material 16c; ¶0023) of the dummy gate (16a) to form a recess (Fig. 3; recess 26 and as described in ¶0028), wherein the recess (26) exposes a silicon-on-insulator (SOI) layer (Fig. 3; 15; ¶0021) of the stack of layers (as shown in Fig. 3; wherein the SOI layer 15 is exposed by the opening recess 26 by removing the gate material 16c); wherein a bottom surface of the recess (bottom of 26) is a top surface of the SOI layer exposed by the recess (bottom of recess 26 in Fig. 3 is the top surface of the SOI layer 15); and
forming an isolation area by an oxidation process (Fig. 4 and as described in ¶0029; the channel region 28 in the SOI layer 15 undergoes an oxidation process to provide an isolation area between components) into a bottom surface of the recess and forming a fill material (Fig. 6; 30; ¶0032) atop the isolation area.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps above of Hong in the method of Wu in order to provide device isolation to reduce overall leakage and design area while allowing different voltages on the drains and preventing stress loss in the SOI layer (Hong; ¶0018).
Modified Wu does not expressly disclose the oxidation process comprises implanting oxygen ions into a bottom surface of the recess and annealing the bottom surface of the recess to form the isolation area in the SOI layer.
In the same field of endeavor, Kanamori teaches a method of forming fine patterned isolation regions (Kanamori; ¶0009-¶0010) particularly advantageous to FD-SOI substrates/devices (Kanamori; ¶0025).
Kanamori’s method comprises forming a mask layer (Kanamori; Fig. 1A; 110+112) over a FD-SOI substrate (Kanamori; Fig. 1A; 100; ¶0022) with an opening exposing the area to be isolated (as shown in Kanamori Fig. 1A); followed by implanting oxygen ions into the bottom surface of the opening (as shown in Fig. 1A and described in ¶0022) and annealing the bottom surface of the opening in the SOI layer (Kanamori; Fig. 1A; 106; ¶0022-¶0023; wherein the field oxidation process is an annealing process) to form an isolation area (Kanamori; Fig. 1B; 116; ¶0023) in the SOI layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the oxygen implant method of Kanamori for the oxidation method of modified Wu. One of ordinary skill in the art would have motivation to make this modification because Kanamori teaches the oxidation process is good for avoiding the degradation of FD-SOI devices caused by shallow trench isolation/etching methods (Kanamori; ¶0006) while providing finely patterned and adequate isolation areas between active regions (Kanamori; ¶0014) which is particularly advantageous to FD-SOI devices (Kanamori; ¶0025).
Regarding Claim 10, modified Wu teaches the method of claim 9, further comprising forming a fill material (Hong; 30) within the recess (Hong; 26), wherein the fill material (30) is formed atop the isolation area (oxidized channel region 28) (as modified by Hong Fig. 6).
Regarding Claim 13, modified Wu teaches the method of claim 9, further comprising forming the stack of layers by (as modified by Hong): forming a buried oxide layer (Hong; Fig. 1; 14; ¶0021) over a silicon substrate (Hong; Fig. 1; 12; ¶0021), wherein the SOI layer (Hong; Fig. 1; 15; ¶0021) is formed over the buried oxide layer (14) (as shown in Hong Fig. 1); and forming an oxide layer (Hong; Fig. 1; 19; ¶0024 which can be deposited by CVD) over the SOI layer (15) (as shown in Hong Fig. 1).
Hong as modified does not expressly disclose that the oxide layer 19 is a silicon oxide layer. In the same field of endeavor, Kanamori teaches forming a silicon oxide film (Kanamori; Fig. 1A; 108; ¶0022) over the SOI layer (Kanamori; 106) that can be deposited by CVD (Kanamori; ¶0036).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the silicon oxide of Kanamori for the oxide layer in Hong to form the SOI of Wu because the substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 14, modified Wu teaches the method of claim 9, wherein the gate material of the dummy gate (Wu; gate material of 212b) is etched through the opening (228) of the mask (226), and wherein no sacrificial spacer is present along a sidewall of the opening of the mask during the etching (as shown in Wu Fig. 6/Fig. 7).
Regarding Claim 15, Wu teaches a method of forming a fully depleted silicon-on-insulator (FDSOI) device having a diffusion break (implicitly satisfied by meeting the following limitations), the method comprising:
forming a plurality of gates (Fig. 3; gates 212 comprising spacers 214; ¶0018-¶0019) in a stack of layers (in stack of layers of Fig. 3), wherein each gate of the plurality of gates comprises a sidewall spacer (214; as shown in Fig. 3) along a gate material (material of gate 212; ¶0018); and
forming a mask (Fig. 5; 226; ¶0023) over the stack of layers, wherein an opening (228; ¶0023) through the mask (226) exposes a dummy gate (212b; ¶0018) of the plurality of gates, wherein a width of the dummy gate (212b comprising sidewall spacers 214) aligns with a width of the opening (228) (as shown in Fig. 3);
forming the diffusion break by:
etching the gate material (of 212b) of the dummy gate to form a recess (232) (as shown in Fig. 7; etching ¶0024), wherein the recess (232) exposes a SOI layer of the stack of layers (wherein 202 in area 205C is the SOI layer {active layer} as it is the channel for the transistors; ¶0015-¶0016), and wherein the gate material of the dummy gate is removed selective to the sidewall spacer (214) to expose the sidewall spacer (214) of the dummy gate (212b) (as shown in Fig. 7 and ¶0024);
forming an isolation structure (235; ¶0026) in the recess (232) (Fig. 9),
wherein a bottom surface of the recess is a top surface of the SOI layer exposed by the recess (bottom of recess 232 in Fig. 7 is the top surface of the SOI layer which is the active layer in the channel region 205C of the SOI substrate 202).
Wu does not expressly disclose forming the diffusion-break/isolation structure comprises using an oxidation process in a bottom surface of the recess to form an isolation area in the SOI layer, and forming a fill material within the recess, wherein the fill material is formed atop the isolation area.
In the same field of endeavor Hong teaches a similar method comprising providing a plurality of gates (Fig. 1; gate structures 16; ¶0022) in a stack of layers (Fig. 1; 16 are in a stack of layers 12, 14, 15, 19), wherein each gate (16) of the plurality of gates comprises a sidewall spacer (Fig. 1; sidewall spacer 16e; ¶0023);
forming a mask (Fig. 1; mask layer includes 20, 22, and 24; as described in ¶0025 and ¶0027; which combined make a mask to define the width of the opening recess to be formed) over the stack of layers (as shown in Fig. 1), wherein an opening through the mask exposes a dummy gate (Fig. 1 to Fig. 3; dummy gate 16a; ¶0022) of the plurality of gates (16) (as shown in Fig. 2 and Fig. 3 and described in ¶0028; wherein an opening recess 26 is formed by a timed etching process that implicitly exposes the dummy gate 16a);
removing a gate material (Fig. 2; gate material 16c; ¶0023) of the dummy gate (16a) to form a recess (Fig. 3; recess 26 and as described in ¶0028), wherein the recess (26) exposes a silicon-on-insulator (SOI) layer (Fig. 3; 15; ¶0021) of the stack of layers (as shown in Fig. 3; wherein the SOI layer 15 is exposed by the opening recess 26 by removing the gate material 16c); wherein a bottom surface of the recess (bottom of 26) is a top surface of the SOI layer exposed by the recess (bottom of recess 26 in Fig. 3 is the top surface of the SOI layer 15); and
forming an isolation area by an oxidation process (Fig. 4 and as described in ¶0029; the channel region 28 in the SOI layer 15 undergoes an oxidation process to provide an isolation area between components) and forming a fill material (Fig. 6; 30; ¶0032) atop the isolation area.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the steps above of Hong in the method of Wu in order to provide device isolation to reduce overall leakage and design area while allowing different voltages on the drains and preventing stress loss in the SOI layer (Hong; ¶0018).
Modified Wu does not expressly disclose the oxidation process to form the diffusion break/isolation structure comprises implanting oxygen ions into a bottom surface of the recess and annealing the bottom surface of the recess to form the isolation area in the SOI layer.
In the same field of endeavor, Kanamori teaches a method of forming fine patterned isolation regions (Kanamori; ¶0009-¶0010) particularly advantageous to FD-SOI substrates/devices (Kanamori; ¶0025).
Kanamori’s method comprises forming a mask layer (Kanamori; Fig. 1A; 110+112) over a FD-SOI substrate (Kanamori; Fig. 1A; 100; ¶0022) with an opening exposing the area to be isolated (as shown in Kanamori Fig. 1A); followed by implanting oxygen ions into the bottom surface of the opening (as shown in Fig. 1A and described in ¶0022) and annealing the bottom surface of the opening in the SOI layer (Kanamori; Fig. 1A; 106; ¶0022-¶0023; wherein the field oxidation process is an annealing process) to form an isolation area (Kanamori; Fig. 1B; 116; ¶0023) in the SOI layer.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the oxygen implant method of Kanamori for the oxidation method of modified Wu. One of ordinary skill in the art would have motivation to make this modification because Kanamori teaches the oxidation process is good for avoiding the degradation of FD-SOI devices caused by shallow trench isolation/etching methods (Kanamori; ¶0006) while providing finely patterned and adequate isolation areas between active regions (Kanamori; ¶0014) which is particularly advantageous to FD-SOI devices (Kanamori; ¶0025).
Regarding Claim 16, modified Wu teaches the method of claim 15, wherein the isolation area is further formed by annealing the bottom surface of the recess (as modified by Kanamori; Fig. 1A; 106; ¶0022-¶0023; wherein the field oxidation process is an annealing process).
Regarding Claim 19, modified Wu teaches the method of claim 15, further comprising (as modified by Hong) forming the stack of layers by: forming a buried oxide layer (Hong; Fig. 1; 14; ¶0021) over a silicon substrate (Hong; Fig. 1; 12; ¶0021), wherein the SOI layer (Hong; Fig. 1; 15; ¶0021) is formed over the buried oxide layer (14) (as shown in Hong Fig. 1); and forming an oxide layer (Hong; Fig. 1; 19; ¶0024 which can be deposited by CVD) over the SOI layer (15) (as shown in Hong Fig. 1).
Hong as modified does not expressly disclose that the oxide layer 19 is a silicon oxide layer. In the same field of endeavor, Kanamori teaches forming a silicon oxide film (Kanamori; Fig. 1A; 108; ¶0022) over the SOI layer (Kanamori; 106) that can be deposited by CVD (Kanamori; ¶0036).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use the silicon oxide of Kanamori for the oxide layer in Hong to form the SOI of Wu because the substitution of a known equivalent for another known equivalent is prima facie case of obviousness. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 20, modified Wu teaches the method of claim 15, wherein the gate material of the dummy gate (212b) is etched through exposed sidewalls of the opening of the mask (226) (as shown in Wu Fig. 7).
Regarding Claim 21, modified Wu teaches the method of claim 1, but Wu is silent regarding wherein a capping material and stopping layer of the dummy gate are also removed to expose the SOI layer.
However, Hong teaches the similar method, wherein the dummy gate (middle gate Fig. 2) comprises a capping material (16d; ¶0023) and a stopping layer (16b; ¶0023) which are subsequently removed to expose the SOI layer (15).
Absent any evidence of criticality or unexpected results, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the dummy gate configuration of Hong (including the capping material and stopping layer) for the dummy gate structure of Wu because of their art recognized equivalence/suitability for the intended purpose of being a dummy gate to be removed to form an isolation structure. MPEP 2144.06
Regarding Claim 22, modified Wu teaches the method of claim 9, but Wu is silent regarding wherein a capping material and stopping layer of the dummy gate are also removed to expose the SOI layer.
However, Hong teaches the similar method, wherein the dummy gate (middle gate Fig. 2) comprises a capping material (16d; ¶0023) and a stopping layer (16b; ¶0023) which are subsequently removed to expose the SOI layer (15).
Absent any evidence of criticality or unexpected results, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the dummy gate configuration of Hong (including the capping material and stopping layer) for the dummy gate structure of Wu because of their art recognized equivalence/suitability for the intended purpose of being a dummy gate to be removed to form an isolation structure. MPEP 2144.06
Regarding Claim 23, modified Wu teaches the method of claim 15, but Wu is silent regarding wherein a capping material and stopping layer of the dummy gate are also removed to expose the SOI layer.
However, Hong teaches the similar method, wherein the dummy gate (middle gate Fig. 2) comprises a capping material (16d; ¶0023) and a stopping layer (16b; ¶0023) which are subsequently removed to expose the SOI layer (15).
Absent any evidence of criticality or unexpected results, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have the dummy gate configuration of Hong (including the capping material and stopping layer) for the dummy gate structure of Wu because of their art recognized equivalence/suitability for the intended purpose of being a dummy gate to be removed to form an isolation structure. MPEP 2144.06
Claims 6-7, 12, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Hong, Kanamori, and Joel P. DeSouza et al. (US 20040266129 A1; hereinafter DeSouza).
Regarding Claim 6, modified Wu teaches the method of claim 1, but is silent regarding the oxygen ion implant parameters, including wherein the oxygen ions are implanted at a temperature below 400°C.
In the same field of endeavor, DeSouza teaches implanting oxygen ions into silicon at room temperature (which is below 20-25°C) to form an isolation region (DeSouza; ¶0022). DeSouza teaches in ¶0022 that performing room temperature oxygen ion implants acts to amorphize the silicon at a depth determined by the energy level, while the amorphized area caused by the room temperature oxygen ion implant enhances internal thermal oxidation during a following high temperature anneal, which beneficially leads to an isolation area with excellent properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a room temperature oxygen ion implant (as in DeSouza) in the method of modified Wu in order to obtain the benefits made evident above (DeSouza; ¶0022).
Regarding Claim 7, modified Wu teaches the method of claim 1, but is silent regarding the oxygen ion implant parameters, including wherein the oxygen ions are implanted at a temperature below 40°C.
In the same field of endeavor, DeSouza teaches implanting oxygen ions into silicon at room temperature (which is below 20-25°C) to form an isolation region (DeSouza; ¶0022). DeSouza teaches in ¶0022 that performing room temperature oxygen ion implants acts to amorphize the silicon at a depth determined by the energy level, while the amorphized area caused by the room temperature oxygen ion implant enhances internal thermal oxidation during a following high temperature anneal, which beneficially leads to an isolation area with excellent properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a room temperature oxygen ion implant (as in DeSouza) in the method of modified Wu in order to obtain the benefits made evident above (DeSouza; ¶0022).
Regarding Claim 12, modified Wu teaches the method of claim 9, but is silent regarding the oxygen ion implant parameters, including wherein the oxygen ions are implanted at a temperature below 400°C.
In the same field of endeavor, DeSouza teaches implanting oxygen ions into silicon at room temperature (which is below 20-25°C) to form an isolation region (DeSouza; ¶0022). DeSouza teaches in ¶0022 that performing room temperature oxygen ion implants acts to amorphize the silicon at a depth determined by the energy level, while the amorphized area caused by the room temperature oxygen ion implant enhances internal thermal oxidation during a following high temperature anneal, which beneficially leads to an isolation area with excellent properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a room temperature oxygen ion implant (as in DeSouza) in the method of modified Wu in order to obtain the benefits made evident above (DeSouza; ¶0022).
Regarding Claim 18, modified Wu teaches the method of claim 15, but is silent regarding the oxygen ion implant parameters, including wherein the oxygen ions are implanted at a temperature below 400°C.
In the same field of endeavor, DeSouza teaches implanting oxygen ions into silicon at room temperature (which is below 20-25°C) to form an isolation region (DeSouza; ¶0022). DeSouza teaches in ¶0022 that performing room temperature oxygen ion implants acts to amorphize the silicon at a depth determined by the energy level, while the amorphized area caused by the room temperature oxygen ion implant enhances internal thermal oxidation during a following high temperature anneal, which beneficially leads to an isolation area with excellent properties.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to use a room temperature oxygen ion implant (as in DeSouza) in the method of modified Wu in order to obtain the benefits made evident above (DeSouza; ¶0022).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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NATHAN PRIDEMORE
Examiner
Art Unit 2898
/NATHAN PRIDEMORE/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898