DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0148374 A1 to Lee et al. (hereinafter “Lee” – previously cited reference) in further view of US 2018/0047938 A1 to Kishimoto et al. (hereinafter “Kishimoto” – previously cited reference).
Regarding claim 1, Lee discloses a display device comprising:
a substrate comprising a display area for displaying an image, and a non-display area around the display area (display apparatus having a display panel 102 having substrate S within substrate layer 110 paired with substrate layer 150 with an active area AA and a peripheral area PA around the active area AA; Fig. 4; paragraph [0101]);
fan-out lines above the substrate (display panel 102 comprises fanout lines FO1, FO2 disposed on a top side of the substrate 110; Figs. 4-5; paragraph [0111]-[0113]);
a first insulating layer above the fan-out lines such that the fan-out lines are between the substrate and the first insulating layer (via insulation layer 1600 disposed above fanout lines FO1, FO2, where fanout lines FO1, FO2 are shown in Fig. 2 to be disposed between substrate layers 110 and 150, where Fig. 4 illustrates layer 1600 is included in layer 150 and substrate S is included in layer 110; Figs. 2, 4 and 17; paragraph [0171]);
top layers located above the first insulating layer, and electrically connected through a first contact hole of the first insulating layer (electrode layer 1700 disposed on top of via insulation layer 1600 having via hole through which electrode 1700 is disposed to contact active pattern 1200 through drain electrode 1550; Fig. 17; paragraph [0171]);
lead lines below the substrate (display panel 102 comprises connection wires 500, 600 disposed on a bottom surface of the substrate 110 and wrapping around ; Fig. 6; paragraph [0112]); a second insulating layer below the lead lines (insulating interlayer 1400 disposed below connection wires 600; Figs. 2, 4 and 17; paragraph [0174]);
side connecting lines on sides of the substrate, and electrically connecting the fan-out lines and the lead lines (display panel 102 comprises connection wires 500 on side surfaces of the substrate 110 which connect connection wires 600 and fanout lines FO1, FO2; Figs. 4-6; paragraph [0112]); and
bottom layers located below the second insulating layer, and electrically connected through a second contact hole of the second insulating layer (active layer 1200 located below insulating interlayer 1400 having via hole through which drain electrode 1550 is disposed to active pattern 1200; Fig. 17; paragraph [0171]).
Lee fails to disclose top antistatic layers along edges of a top surface above the substrate, located above the first insulating layer, and electrically connected to the fan-out lines; wherein the lead lines are between the substrate and the second insulating layer; and bottom antistatic layers along edges of a bottom surface below the substrate, located below the second insulating layer, and electrically connected to the lead lines.
However, Kishimoto discloses top antistatic layers along edges of a top surface above the substrate, located above the first insulating layer, and electrically connected to the fan-out lines (antistatic adhesive layer 304 regions disposed along all portions of top of peripheral region 40 of substrate 110 of bent display panel 200 and above first portion of insulating interlayer 190, such that antistatic adhesive layer 304 regions protect plurality of wirings including conductive pattern 174 disposed in peripheral region 40 of display panel 200; Fig. 3B; paragraphs [0080], [0082], [0090], [0100], [0119]); wherein the lead lines are between the substrate and the second insulating layer (conductive pattern 172 disposed between substrate 110 and second portion of insulating interlayer 190; Fig. 4B); and bottom antistatic layers along edges of a bottom surface below the substrate, located below the second insulating layer, and electrically connected to the lead lines (antistatic adhesive layer 302 regions disposed along portions of bottom of peripheral region 40 of substrate 110 of bent display panel 200 and below second portion of insulating interlayer 190, such that antistatic adhesive layer 302 regions protect plurality of wirings including conductive pattern 172 disposed in peripheral region 40 of display panel 200; Fig. 3B; paragraphs [0080], [0082], [0090], [0100], [0119]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide ESD protection, improved uniformity of charge distribution, simplified grounding design, mitigation of crosstalk and signal interference, enhanced structural integrity, and lower defect rates in protective layers.
Regarding claim 2, Lee in view of Kishimoto discloses the display device of claim 1, further comprising pixel electrodes in the display area, and configured to receive driving currents (first and second pixel electrodes PE in active area AA and receiving driving signals from display panel driver; Fig. 5; paragraphs [0101], [0104]).
Lee fails to disclose wherein the top antistatic layers and the pixel electrodes comprise a same material in a same layer.
However, Kishimoto discloses wherein the top antistatic layers and the pixel electrodes comprise a same material in a same layer (antistatic adhesive layer 304 regions and gate electrode 170 of display panel 200 are each made from indium tin oxide ITO and disposed co-planar in the same layer; Fig. 3B; paragraphs [0096], [0123]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide simplified manufacturing processes, cost reductions, improved layer compatibility, and seamless electrical integration.
Regarding claim 3, Lee in view of Kishimoto discloses the display device of claim 2, further comprising a passivation layer covering edges of the pixel electrodes (thin film encapsulation layer covering area containing pixel electrodes PE; Fig. 5; paragraph [0074]).
Lee fails to disclose covering edges of the top antistatic layers such that top surfaces of top antistatic layers are exposed by the passivation layer.
However, Kishimoto discloses covering edges of the top antistatic layers such that top surfaces of top antistatic layers are exposed by the passivation layer (protection layer 303 covers portions of antistatic adhesive layer 304 regions such that top side surfaces are left exposed as shown in Fig. 3B; paragraph [0080]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide robust edge protection, maintained electrical functionality, reduced risk of shorts, and enhanced mechanical stability.
Regarding claim 4, Lee in view of Kishimoto discloses the display device of claim 2. Lee fails to disclose wherein the top antistatic layers comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO).
However, Kishimoto discloses wherein the top antistatic layers comprise at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO) (antistatic adhesive layer 304 regions are made from indium tin oxide ITO; Fig. 3B; paragraph [0123]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide high transparency, good electrical conductivity, compatibility with existing fabrication processes, and integration with pixel electrodes.
Regarding claim 5, Lee in view of Kishimoto discloses the display device of claim 1. Lee fails to disclose pad units in the non-display area, and separated from the top antistatic layers in plan view.
However, Kishimoto discloses pad units in the non-display area, and separated from the top antistatic layers in plan view (pad electrodes 470 disposed in pad electrode region 60 and separated from antistatic adhesive layer 304 regions in a plan view as shown in Fig. 1B; paragraph [0083]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide reduced risk of electrical interference, enhanced ESD protection isolation, and simplified bonding and assembly.
Regarding claim 6, Lee in view of Kishimoto discloses the display device of claim 1, wherein some of the lead lines extend from the display area to edges of the non-display area (connection wires 600 extending from active area AA to edges of peripheral area PA via wires 500 and fanout lines FO1, FO2; Figs. 4-6).
Lee fails to disclose wherein some of the lead lines are separated from the bottom antistatic layers in plan view.
However, Kishimoto discloses some of the lead lines are separated from the bottom antistatic layers in plan view (antistatic adhesive layer 302 regions are separated from wirings of display panel 200 in any view; Fig. 3B; paragraphs [0080], [0082], [0090], [0119]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide reduced risk of electrical interference and enhanced ESD protection.
Regarding claim 7, Lee in view of Kishimoto discloses the display device of claim 1. Lee further discloses wherein the fan-out lines are electrically connected to a low-potential electrode or a common voltage line (fanout lines FO1, FO2 receive data voltages output from data driver 400; paragraphs [0087], [0091]).
Regarding claim 8, Lee in view of Kishimoto discloses the display device of claim 1, further comprising: contact electrodes below the substrate, and electrically connected to the lead lines (pixel and common electrodes disposed below substrate 150 of substrate pair and coupled to connection wires 600 via wires 500 and fanout lines FO1, FO2; Figs 4-6; paragraphs [0073], [0076]); and flexible films electrically connected to the contact electrodes (data flexible substrates 410 electrically connected to display panel 100 comprising pixel and common electrodes; paragraphs [0089], [0110]).
Lee fails to disclose wherein the bottom antistatic layers and the contact electrodes comprise a same material.
However, Kishimoto discloses wherein the bottom antistatic layers and the contact electrodes comprise a same material (antistatic adhesive layer 302 regions and electrode layer 410 of display panel 200 are each made from indium tin oxide ITO and disposed co-planar in the same layer; Fig. 3B; paragraphs [0113], [0123]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide simplified manufacturing processes, cost reductions, improved layer compatibility, and seamless electrical integration.
Regarding claim 9, Lee in view of Kishimoto discloses the display device of claim 1. Lee further discloses wherein the side connecting lines are not in direct contact with the top antistatic layers or the bottom antistatic layers (connection wires 500 not in contact with any antistatic layers as shown in Figs. 4-6).
Regarding claim 10, Lee in view of Kishimoto discloses the display device of claim 1, further comprising: pixels comprising at least one light-emitting element (pixels in display layer 170 comprising organic light emitting layer; paragraph [0103]).
Lee fails to disclose antistatic circuits between the top antistatic layers and the pixels.
However, Kishimoto discloses antistatic circuits between the top antistatic layers and the pixels (a circuit is formed due to the electrical interaction between antistatic adhesive layer 304 regions and plurality of pixels P that the regions are designed to protect; paragraphs [0006]-[0007], [0082], [0120]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to at least potentially provide enhanced ESD protection for pixels, improved charge management, and reduced risk of pixel interference.
Regarding claim 11, Lee in view of Kishimoto discloses the display device of claim 1. Lee further discloses further comprising: transistors above the substrate (transistors disposed in pixel area on top surface of substrate 110; paragraphs [0068], [0168]); connecting electrodes above, and electrically connected to, the transistors (each transistor disposed on barrier layer 1100 and connected to electrodes 1350, 1500, 1550 stacked above barrier layer 1100; Fig. 17; paragraph [0171]); anode connecting lines above, and electrically connected to, the connecting electrodes (each transistor having vertical conductor line connecting anode electrode 1700 to electrodes 1350, 1500, 1550 as shown in Fig. 17; paragraph [0192]); anode connecting electrodes above, and electrically connected to, the anode connecting lines (anode electrode 1700 disposed above vertical conductor line as shown in Fig. 17); and pixel electrodes above, and electrically connected to, the anode connecting electrodes (each transistor comprises pixel electrode 2100 disposed above and electrically coupled to anode electrode 1700 as shown in Fig. 17; paragraphs [0207]-[0208]).
Regarding claim 12, Lee in view of Kishimoto discloses the display device of claim 11. Lee fails to disclose wherein the top antistatic layers and the anode connecting electrodes comprise a same material in a same layer.
However, Kishimoto discloses wherein the top antistatic layers and the anode connecting electrodes comprise a same material in a same layer (antistatic adhesive layer 304 regions and gate electrode 170 of display panel 200 are each made from indium tin oxide ITO and disposed co-planar in the same layer; Fig. 3B; paragraphs [0096], [0123]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide simplified manufacturing processes, cost reductions, improved layer compatibility, and seamless electrical integration.
Regarding claim 13, Lee in view of Kishimoto discloses the display device of claim 11. Lee fails to disclose wherein the top antistatic layers and the anode connecting lines comprise a same material in a same layer.
However, Kishimoto discloses wherein the top antistatic layers and the anode connecting lines comprise a same material in a same layer (antistatic adhesive layer 304 regions and components of gate electrode 170 of display panel 200 are each made from indium tin oxide ITO and disposed co-planar in the same layer; Fig. 3B; paragraphs [0096], [0123]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide simplified manufacturing processes, cost reductions, improved layer compatibility, and seamless electrical integration.
Regarding claim 14, Lee in view of Kishimoto discloses the display device of claim 11. Lee fails to disclose wherein the top antistatic layers and the connecting electrodes comprise a same material in a same layer.
However, Kishimoto discloses wherein the top antistatic layers and the connecting electrodes comprise a same material in a same layer (antistatic adhesive layer 304 regions and electrode layer 410 of display panel 200 are each made from indium tin oxide ITO and disposed co-planar in the same layer; Fig. 3B; paragraphs [0096], [0123]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide simplified manufacturing processes, cost reductions, improved layer compatibility, and seamless electrical integration.
Regarding claim 15, Lee discloses a display device comprising:
a substrate comprising a display area for displaying an image, and a non-display area around the display area (display apparatus having a substrate pairing 110, 150 with an active area AA and a peripheral area PA around the active area AA; Fig. 4; paragraph [0101]);
fan-out lines above the substrate (fanout lines FO1, FO2 disposed on a top side of the substrate 110; Figs. 4-5; paragraph [0111]-[0113]);
a first insulating layer above the fan-out lines such that the fan-out lines are between the substrate and the first insulating layer (via insulation layer 1600 disposed above fanout lines FO1, FO2, where fanout lines FO1, FO2 are shown in Fig. 2 to be disposed between substrate layers 110 and 150, where Fig. 4 illustrates layer 1600 is included in layer 150 and substrate S is included in layer 110; Figs. 2, 4 and 17; paragraph [0171]);
top layers located above the first insulating layer, and electrically connected through a first contact hole of the first insulating layer (electrode layer 1700 disposed on top of via insulation layer 1600 having via hole through which electrode 1700 is disposed to contact active pattern 1200 through drain electrode 1550; Fig. 17; paragraph [0171]);
lead lines (connection wires 600; Figs. 4-6; paragraph [0112]);
side connecting lines on sides of the substrate, and electrically connecting the fan-out lines and the lead lines (connection wires 500 on side surfaces of the substrate 110 which connect connection wires 600 and fanout lines FO1, FO2; Figs. 4-6; paragraph [0112]);
wherein the side connecting lines are not in direct contact with the top antistatic layers or the bottom antistatic layers (connection wires 500 not in contact with any antistatic layers as shown in Figs. 4-6).
Lee fails to disclose top antistatic layers along edges of a top surface above the substrate, located above the first insulating layer, and electrically connected to the fan-out lines; and bottom antistatic layers along edges of a bottom surface below the substrate, and electrically connected to the fan-out lines.
However, Kishimoto discloses top antistatic layers along edges of a top surface above the substrate, located above the first insulating layer, and electrically connected to the fan-out lines (antistatic adhesive layer 304 regions disposed along all portions of top of peripheral region 40 of substrate 110 of bent display panel 200 and above first portion of insulating protection layer 301, such that antistatic adhesive layer 304 regions protect plurality of wirings disposed in peripheral region 40 of display panel 200; Fig. 3B; paragraphs [0080], [0082], [0090], [0119]); and bottom antistatic layers along edges of a bottom surface below the substrate, and electrically connected to the fan-out lines (antistatic adhesive layer 302 regions disposed along portions of bottom of peripheral region 40 of substrate 110 of bent display panel 200, such that antistatic adhesive layer 302 regions protect plurality of wirings disposed in peripheral region 40 of display panel 200; Fig. 3B; paragraphs [0080], [0082], [0090], [0119]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide ESD protection, improved uniformity of charge distribution, simplified grounding design, and mitigation of crosstalk and signal interference.
Regarding claim 16, Lee in view of Kishimoto discloses the display device of claim 1. Lee further discloses further comprising flexible films below the substrate wherein the lead lines are electrically connected between the flexible films and the side connecting lines (data flexible substrates 410 disposed on bottom side of substrate 110 and connection wires 600 disposed between substrate 410 and connection lines 500 as shown in Fig. 6; paragraphs [0089], [0110]).
Regarding claim 17, Lee in view of Kishimoto discloses the display device of claim 11. Lee fails to disclose wherein the bottom antistatic layers are electrically connected to the fan-out lines through the lead lines and the side connecting lines.
However, Kishimoto discloses wherein the bottom antistatic layers are electrically connected to the fan-out lines through the lead lines and the side connecting lines (antistatic adhesive layer 302 regions electrically interact with all wirings to protect them from electrostatic discharge; paragraphs [0006]-[0007], [0071], [0082], [0120]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide ESD protection, improved uniformity of charge distribution, simplified grounding design, and mitigation of crosstalk and signal interference.
Regarding claim 18, Lee in view of Kishimoto discloses the display device of claim 15. Lee fails to disclose further comprising pad units in the non- display area, and separated from the top antistatic layers in plan view.
However, Kishimoto discloses further comprising pad units in the non- display area, and separated from the top antistatic layers in plan view (pad electrodes 470 disposed in pad electrode region 60 and separated from antistatic adhesive layer 304 regions in a plan view as shown in Fig. 1B; paragraph [0083]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide reduced risk of electrical interference, enhanced ESD protection isolation, and simplified bonding and assembly.
Regarding claim 19, Lee in view of Kishimoto discloses the display device of claim 15, wherein some of the lead lines extend from the display area to edges of the non-display area (connection wires 600 extending from active area AA to edges of peripheral area PA via wires 500 and fanout lines FO1, FO2; Figs. 4-6).
Lee fails to disclose wherein some of the lead lines are separated from the bottom antistatic layers in plan view.
However, Kishimoto discloses some of the lead lines are separated from the bottom antistatic layers in plan view (antistatic adhesive layer 302 regions are separated from wirings of display panel 200 in any view; Fig. 3B; paragraphs [0080], [0082], [0090], [0119]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to at least potentially provide reduced risk of electrical interference and enhanced ESD protection.
Regarding claim 20, Lee discloses tiled display device comprising:
display devices comprising:
a substrate comprising a display area for displaying an image, and a non- display area around the display area (tiled display apparatus having plurality of display panels each having a substrate pairing 110, 150 with an active area AA and a peripheral area PA around the active area AA; Fig. 4; paragraph [0101]);
fan-out lines above the substrate (fanout lines FO1, FO2 disposed on a top side of the substrate 110; Figs. 4-5; paragraph [0111]-[0113]);
a first insulating layer above the fan-out lines such that the fan-out lines are between the substrate and the first insulating layer (via insulation layer 1600 disposed above fanout lines FO1, FO2, where fanout lines FO1, FO2 are shown in Fig. 2 to be disposed between substrate layers 110 and 150, where Fig. 4 illustrates layer 1600 is included in layer 150 and substrate S is included in layer 110; Figs. 2, 4 and 17; paragraph [0171]);
top layers located above the first insulating layer, and electrically connected through a first contact hole of the first insulating layer (electrode layer 1700 disposed on top of via insulation layer 1600 having via hole through which electrode 1700 is disposed to contact active pattern 1200 through drain electrode 1550; Fig. 17; paragraph [0171]);
lead lines below the substrate (connection wires 600 disposed on a bottom surface of the substrate 110; Fig. 6; paragraph [0112]);
a second insulating layer below the lead lines (insulating interlayer 1400 disposed below connection wires 600; Figs. 2, 4 and 17; paragraph [0174]);
side connecting lines on sides of the substrate, and electrically connecting the fan-out lines and the lead lines (connection wires 500 on side surfaces of the substrate 110 which connect connection wires 600 and fanout lines FO1, FO2; Figs. 4-6; paragraph [0112]);
bottom layers located below the second insulating layer, and electrically connected through a second contact hole of the second insulating layer (active layer 1200 located below insulating interlayer 1400 having via hole through which drain electrode 1550 is disposed to active pattern 1200; Fig. 17; paragraph [0171]); and
a bonding area between the display devices (plurality of display panels connected together along boundary areas as shown in Fig. 7; paragraphs [0049], [0124], [0139]).
Lee fails to disclose top antistatic layers along edges of a top surface above the substrate, located above the first insulating layer, and electrically connected to the fan-out lines; wherein the lead lines are between the substrate and the second insulating layer; and bottom antistatic layers along edges of a bottom surface below the substrate, located below the second insulating layer, and electrically connected to the lead lines.
However, Kishimoto discloses top antistatic layers along edges of a top surface above the substrate, located above the first insulating layer, and electrically connected to the fan-out lines (antistatic adhesive layer 304 regions disposed along all portions of top of peripheral region 40 of substrate 110 of bent display panel 200 and above first portion of insulating protection layer 301, such that antistatic adhesive layer 304 regions protect plurality of wirings disposed in peripheral region 40 of display panel 200; Fig. 3B; paragraphs [0080], [0082], [0090], [0119]); wherein the lead lines are between the substrate and the second insulating layer (conductive pattern 172 disposed between substrate 110 and second portion of insulating interlayer 190; Fig. 4B); and bottom antistatic layers along edges of a bottom surface below the substrate, located below the second insulating layer, and electrically connected to the lead lines (antistatic adhesive layer 302 regions disposed along portions of bottom of peripheral region 40 of substrate 110 of bent display panel 200 and above second portion of insulating protection layer 301, such that antistatic adhesive layer 302 regions protect plurality of wirings disposed in peripheral region 40 of display panel 200; Fig. 3B; paragraphs [0080], [0082], [0090], [0119]).
Lee and Kishimoto are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lee to incorporate the teaching of Kishimoto in order to potentially provide ESD protection, improved uniformity of charge distribution, simplified grounding design, mitigation of crosstalk and signal interference, enhanced structural integrity, and lower defect rates in protective layers.
Response to Arguments
Applicant's arguments filed February 5, 2026 have been fully considered. Applicant submitted arguments that Kishimoto does not appear to disclose that the top and bottom antistatic layers 302, 304 are electrically connected to the conductive patterns 172, 174. However, in order for layers 302, 304 to function as antistatic layers for the patterns 172, 174 as disclosed by Kishimoto, the layers must be inductively/capacitively coupled to the patterns which meets the broadest reasonable interpretation of the claim term ‘electrically connected’. Specifically, if the layers 302, 304 weren’t there, then charge would build up on the substrate and induce an electric field within the patterns 172, 174. Therefore, by preventing the electric field from being induced within the patterns, the layers are electrically coupled to the patterns via the inductive/capacitive coupling.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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