DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Claim 1 as amended recites “first conductive material”. The term is most likely referring to a plurality of different materials 20 which does not comprise “conductive material”.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8, 10, 14, 15, 17 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 as amended recites “at least one depletion mode gate on a first conductive material and over a semiconductor material; and at least one enhancement mode gate comprising a combination of a second conductive material and p-doped semiconductor material, the p-doped semiconductor material of the at least one enhancement mode gate being electrically connected to the at least one depletion mode gate. and the first conductive material being over the p-doped semiconductor material and under the second conductive material and being under the at least one depletion mode gate.”
According to originally filed specification a conductive layer is defined as Al.sub.2O.sub.3 and the conductive material is defined as SiN. See [0021, 0022] of Originally filed specifications.
The Examiner notes that Aluminum Oxide and SiN are non-conductive or dielectric layers and the use of the term "conductive layer" creates, assuming the standard definition applied in the semiconductor art, the expectation of electrically conductive layer.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “first conductive material” and “second conductive material” in claim 1 is used by the claim to mean “electrically conductive,” while the accepted meaning is “non-conductive or dielectric” The term is indefinite because the specification does not clearly redefine the term.
For the purposes of examination, the Examiner will treat “first conductive material” and “second conductive material” as electrically isolation layer.
Claims 2-8 and 10 are rejected as being dependent of Claim 1.
Claim 14 as amended recites “a plurality of different materials comprising a conductive layer, an etch stop layer and an insulator material”
According to originally filed specification a conductive layer is defined as Al.sub.2O.sub.3. See [0022] of originally filed specifications.
The Examiner notes that Aluminum Oxide is non-conductive or dielectric layer the use of the term "conductive layer" creates, assuming the standard definition applied in the semiconductor art, the expectation of electrically conductive layer.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “conductive layer” in claim 1 is used by the claim to mean “electrically conductive,” while the accepted meaning is “non-conductive or dielectric” The term is indefinite because the specification does not clearly redefine the term.
For the purposes of examination, the Examiner will treat "conductive layer" as electrically isolation layer.
Claims 15, 17 and 19 are rejected as being dependent of Claim 14.
Claim 6 recites “the at least one depletion mode gate comprises a metal insulator semiconductor (MIS) capacitor.”
It is not clear how can depletion mode gate can comprise MIS capacitor if according to Claim 1 it is formed on a first conductive material and over a semiconductor material which are parts of MIS capacitor (at least according to Claim 7).
For the purposes of examination, the Examiner will treat Claim 6 as meta as long as a metal insulator semiconductor (MIS) capacitor comprises the at least one depletion mode gate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 14, 15, 17 and 19 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Ota et al. (US 2014/0209922 A1).
Regarding Claim 1, Ota (Fig. 23) discloses a structure comprising:
at least one depletion mode gate (GE2) on a first conductive material (IF) and over a semiconductor material (CH); and
at least one enhancement mode gate (GE2, P1, M1, CAP) comprising a combination of a second conductive material (GE2, P1, M1) and p-doped semiconductor material (CAP, p type GaN), [0086] the p-doped semiconductor material (CAP) of the at least one enhancement mode gate (GE1) being electrically connected to the at least one depletion mode gate (GE1). and the first conductive material (ES) being and-over the p-doped semiconductor material (CAP) and under the second conductive material (GE2, P1, M1) and being under the at least one depletion mode gate. (GE2)
Regarding Claim 2, Ota (Fig. 23) discloses the structure of claim 1, wherein
the p-doped semiconductor material of the at least one enhancement mode gate comprises a GaN island (CAP, p type GaN), [0086] and the second conductive material comprises with a gate metal (GE2) connecting to the GaN island. (CAP, p type GaN).
Regarding Claim 3, Ota (Fig. 23) discloses the structure of claim 2, wherein the second conductive material is an intervening conductive material (at least GE2) between to the GaN island (CAP) and the first conductive material (IF).
Regarding Claim 4, Ota (Fig. 23) discloses the structure of claim 2, wherein
the GaN island is a p-doped GaN island (CAP, p type GaN), [0086].
Regarding Claim 5, Ota (Fig. 23) discloses the structure of claim 1, wherein the at least one depletion mode gate (GE2) comprises a field plate. (extension of G2 over ES).
Regarding Claim 6, Ota (Fig. 23) discloses the structure of claim 5, wherein the at least one depletion mode gate (GE2) comprises a metal insulator semiconductor (MIS) capacitor. (GE2, CAP, IF)
Regarding Claim 7, Huang (Fig. 4, 8, 11, 16) discloses the structure of claim 6, wherein
the semiconductor material comprises a common conducting channel (CH) of the at least one depletion mode gate (G2) and the least one enhancement mode gate (GE2, P1, M1, CAP), and the field plate of the at least one depletion mode gate (Extention of G2) forms part of the MIS capacitor. (GE2, CAP, IF)
The Examiner notes that the gate of the D-mode HEMT forms MIS capacitor by including insulating gate dielectric layer 72 between gate field-plate metal 62/metal layer 36 and semiconductor channel layer 15) (Fig. 16)
Regarding Claim 8, Ota (Fig. 23) discloses the structure of claim 7, wherein the common conducting channel comprises GaN. (gallium nitride (GaN) constituting the channel layer CH) [0063].
Regarding Claim 14, Ota (Fig. 23) discloses a structure comprising:
a metal-insulator-semiconductor (MIS) capacitor (CH, ES, IF, GE2), the MIS capacitor comprising a metal plate (GE2) over a common conducting channel (CH) and a plurality of different materials comprising a conductive layer (SiO2), an etch stop layer (SiON) and an insulator material (AlN, diamond film, polyimide film) (IF, “As the insulating film IF, for example, a silicon nitride (SiN) film can be used. A silicon oxide film (SiO.sub.2), a SiON film, an AlN film, a diamond film, a polyimide film, or the like may also be used. A film stack obtained by stacking these materials may also be use”) [0073] and
an island of semiconductor material (CAP) over a semiconductor substrate (SUB) and electrically connected to the MIS capacitor (CH, ES, IF, GE2), the island of semiconductor material also being under the plurality of different materials (IF).
Regarding Claim 15, Ota (Fig. 23) discloses the structure of claim 14, wherein
the common conducting channel comprises GaN. (gallium nitride (GaN) constituting the channel layer CH) [0063].
Regarding Claim 17, Ota (Fig. 23) discloses the structure of claim 16, wherein
the island of semiconductor material comprises pGaN. (CAP, p type GaN), [0086].
Regarding Claim 19, Ota (Fig. 23) discloses the structure of claim 14, wherein
the island of semiconductor material (CAP) comprises an enhancement mode gate. (GE1, CAP).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota et al. (US 2014/0209922 A1).
Regarding Claim 10, Ota (Fig. 23) discloses the structure of claim 1,
Ota in the current embodiment does not explicitly disclose that wherein the at least one depletion mode gate surrounds the at least one enhancement mode gate.
Ota (Fig. 24) discloses at least one depletion mode gate (See GE2 over IF and 2DEG) surrounds the at least one enhancement mode gate. (GE1 over CAP (“a cap layer composed of a p type semiconductor layer”) [0012]).
The Examiner notes that GE2 at least partially surrounds GE1. (Fig. 24)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Ota such that the at least one depletion mode gate surrounds the at least one enhancement mode gate in order to avoid misalignment between the cap layer CAP and the gate electrode GE. [0255]
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 01/27/2026 have been fully considered but they are not persuasive.
Regarding Applicants Arguments concerning Claim 14 and prior art of Ota on page 9.
The Examiner notes Claim 14 as amended recites “the MIS capacitor comprising a metal plate over a common conducting channel and a plurality of different materials comprising a conductive layer, an etch stop layer and an insulator material”. Further, Claim 1 does not recite nor originally filed specifications supports “teach different materials under a MIS capacitor and over an enhancement mode capacitor” or “different materials can be under any device, much less a MIS capacitor comprising a metal plate over a common conducting channel.”
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “teach different materials under a MIS capacitor and over an enhancement mode capacitor” or “different materials can be under any device, much less a MIS capacitor comprising a metal plate over a common conducting channel.”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891