DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the
“a metal-insulator-semiconductor (MIS) capacitor” of Claim 1.
“an intervening conductive material between to the GaN island and the gate metal” of Claim 3.
“a metal-insulator-semiconductor (MIS) capacitor” of Claim 14.
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claims 4, 5, 6, 7, 17 and 19 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 4 recites “the GaN island is a p-doped GaN island” fails to further limit Claim 2 as amended “the p-doped semiconductor material comprises a GaN island”.
Claim 5 recites “the at least one depletion mode gate comprises a field plate.” fails to further limit Claim 1 as amended “at least one depletion mode gate comprising a field plate”.
Claim 6 recites “the field plate of at least one depletion mode gate comprises forms part of the metal insulator semiconductor capacitor.” fails to further limit Claim 1 as amended “the field plate of the at least one depletion mode gate is part of the MIS capacitor.”
Claim 7 recites “the semiconductor material comprises a common conducting channel shared by the at least one depletion mode gate and the at least one enhancement mode gate, and the field plate of the at least one depletion mode gate is part of the MIS capacitor.” fails to further limit Claim 1 as amended “the semiconductor material comprises a common conducting channel shared by the at least one depletion mode gate and the at least one enhancement mode gate, and the field plate of the at least one depletion mode gate is part of the MIS capacitor.”
Claim 17 recites “the island of semiconductor material comprises pGaN” fails to further limit Claim 14 as amended “the island of semiconductor material comprises a p-doped GaN island”.
Claim 19 recites “the island of semiconductor material comprises an enhancement mode gate connected to the MIS capacitor.” fails to further limit Claim 14 as amended “an island of semiconductor material over a semiconductor substrate and electrically connected to the MIS capacitor, wherein the island of semiconductor material comprises a p-doped GaN island configured as an enhancement mode gate”.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim 8 is rejected as being dependent on Claim 5.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites “the at least one depletion mode gate comprises a field plate.”
It is not clear if the Applicant is trying to introduce an additional filed plate in the at least one depletion mode gate or refer back to “a filed plate” introduces in Claim 1.
For the purposes of examination and in order to avoid written description rejection under 35 U.S.C. 112(b) first paragraph the limitation “the at least one depletion mode gate comprises a field plate.” will be interpreted as --the at least one depletion mode gate comprises the field plate.--
Claim 19 recites “the island of semiconductor material comprises an enhancement mode gate connected to the MIS capacitor.”
It is not clear if the Applicant is trying to introduce an additional enhancement mode gate or refer back to “an enhancement mode gate” introduces in Claim 14.
For the purposes of examination and in order to avoid written description rejection under 35 U.S.C. 112(b) first paragraph the limitation “the island of semiconductor material comprises an enhancement mode gate” will be interpreted as --the island of semiconductor material comprises the enhancement mode gate.--
Claims 6-8 are rejected as being dependent on Claim 5.
Claim Objections
Claims 6 and 7 are objected to because of the following informalities:
Claim 6 recites “the field plate of at least one depletion mode gate” is missing “the” before “at least one depletion mode gate”.
Claim 7 recites “the least one enhancement mode gate” which is grammatical defect. This limitation is missing “at” and should read “the at least one enhancement mode gate”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-8 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Ota et al. (US 2014/0209922 A1).
Regarding Claim 1, Ota (Fig. 23) discloses a structure comprising:
at least one depletion mode gate (GE2, IF) comprising a field plate (extension of GE2 over ES) and being part of a metal-insulator-semiconductor (MIS) capacitor (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) on the channel layer CH ([0195] over a semiconductor material (“a channel layer CH made of a nitride semiconductor”); and
at least one enhancement mode gate (GE1, P1, CAP) comprising
a p-doped semiconductor material (CAP, p type GaN), [0086], and a gate metal (“metal film is then patterned to form the first gate electrode portion GE1”) [0190] over the p-doped semiconductor material (CAP, p type GaN), [0086], the p-doped semiconductor material (CAP, p type GaN) of the at least one enhancement mode gate being electrically connected (connected at least through M1 and P2) to the at least one depletion mode gate, wherein
the semiconductor material (CH) comprises a common conducting channel (a (channel layer CH made of a nitride semiconductor“) shared by the at least one depletion mode gate and the at least one enhancement mode gate, and
the field plate (extension of GE2 over ES) of the at least one depletion mode gate is part of the MIS capacitor. (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) thereby forming MIS capacitor.
Regarding Claim 2, Ota (Fig. 23) discloses the structure of claim 1, wherein
the p-doped semiconductor material comprises a GaN island (CAP, p type GaN), [0086] and the gate metal (“metal film is then patterned to form the first gate electrode portion GE1”) [0190] is electrically connected to the GaN island. (CAP, p type GaN).
Regarding Claim 4, Ota (Fig. 23) discloses the structure of claim 2, wherein
the GaN island is a p-doped GaN island (CAP, p type GaN), [0086].
Regarding Claim 5, Ota (Fig. 23) discloses the structure of claim 1, wherein the at least one depletion mode gate (GE2, IF) comprises a field plate. (extension of GE2 over ES).
Regarding Claim 6, Ota (Fig. 23) discloses the structure of claim 5, wherein
the field plate of at least one depletion mode gate (GE2, IF) forms part of the metal insulator semiconductor (MIS) capacitor. (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) thereby forming MIS capacitor.
Regarding Claim 7, Ota (Fig. 23) discloses the structure of claim 6, wherein
the semiconductor material comprises a common conducting channel (CH) of the at least one depletion mode gate (GE2, IF) and the least one enhancement mode gate (GE1, P1, CAP), and the field plate of the at least one depletion mode gate (extension of GE2 over ES) forms part of the MIS capacitor. (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) thereby forming MIS capacitor.
Regarding Claim 8, Ota (Fig. 23) discloses the structure of claim 7, wherein the common conducting channel comprises GaN. (gallium nitride (GaN) constituting the channel layer CH) [0063].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota et al. (US 2014/0209922 A1).
Regarding Claim 3, Ota (Fig. 23) discloses the structure of claim 2.
Ota does not explicitly disclose an intervening conductive material between to the GaN island and the gate metal.
However, Ota discloses the gate metal (GE1) comprises a metal silicide (“the first gate electrode portion GE1 may be comprised of a silicide or nitride film of a metal such as aluminum, titanium, tungsten, molybdenum, or nickel.” [01190] and gate metal can comprise multilayer stack of conductive material/metal (“As the metal film, a single layer film of a metal selected from aluminum, titanium, tungsten, molybdenum, nickel, or the like or a film stack thereof may be used.”) [0190]
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Ota such that an intervening conductive material between to the GaN island and the gate metal in order to create good ohmic contact between GaN island and the gate metal and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Regarding Claim 10, Ota (Fig. 23) discloses the structure of claim 1,
Ota in the current embodiment does not explicitly disclose that wherein the at least one depletion mode gate surrounds the at least one enhancement mode gate.
Ota (Fig. 24) discloses at least one depletion mode gate (See GE2 over IF and 2DEG) surrounds the at least one enhancement mode gate. (GE1 over CAP (“a cap layer composed of a p type semiconductor layer”) [0012]).
The Examiner notes that GE2 at least partially surrounds GE1. (Fig. 24)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Ota such that the at least one depletion mode gate surrounds the at least one enhancement mode gate in order to avoid misalignment between the cap layer CAP and the gate electrode GE. [0255]
Claim(s) 14, 15, 17 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ota et al. (US 2014/0209922 A1) in view of Chiu et al. (US 2016/0240646 A1).
Regarding Claim 14, Ota (Fig. 23) discloses a structure comprising:
a metal-insulator-semiconductor (MIS) capacitor (ES, IF, GE2), the MIS capacitor comprising
a metal plate (GE2) over a common conducting channel (CH), a silicon nitride layer (“SiON film”), and an insulator layer (AlN film, a diamond film, a polyimide film) [0073]
an island of semiconductor material (CAP, p type GaN), [0086] over a semiconductor substrate (SUB) and electrically connected (through C1,M1,C2) to the MIS capacitor (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) thereby forming MIS capacitor), wherein
the island of semiconductor material comprises a p-doped GaN island (CAP, p type GaN), configured as an enhancement mode gate [0188-0191]
The Examiner notes originally filed specification discloses
“[0035] FIG. 8A shows a pGaN island (e.g., e-mode gate 19) formed on the semiconductor material 14 (e.g., conducting channel). In embodiments, the semiconductor material 14 may be deposited on the semiconductor substrate 12 using any conventional deposition method, e.g., CVD. To form the e-mode gate 19, semiconductor material 16 may be epitaxially grown on the semiconductor material 14. In embodiments, an in-situ doping (e.g., p-type dopant) may be used during the epitaxial growth process. Conductive material 18, e.g., TiN, may be deposited on the semiconductor material 16. The semiconductor material 16 and conductive material 18 undergo conventional lithography and etching processes to form the e-mode gate 19, e.g., GaN island. In embodiments, the conductive material 18 may undergo an additional selective pull-back etching process to form the e-mode gate 19.”
Therefore, as long as p-doped GaN island (CAP) is on semiconductor material (ES) and/or p-doped GaN island (CAP) and conductive material (GE1) are formed (See Fig. 15, 16) the limitation “the island of semiconductor material comprises a p-doped GaN island, configured as an enhancement mode gate” is considered to be met.
Ota does not explicitly disclose an aluminum oxide layer.
Chiu (Fig. 3) discloses a metal-insulator-semiconductor (MIS) (“the III-N HEMT device 300 corresponds to a D-mode MIS FET (metal-insulator-semiconductor field-effect transistor)” comprising an aluminum oxide layer (“the insulator 126 may comprise a silicon nitride (SiN) layer, an aluminum oxide (AlO.sub.3 or Al.sub.2O.sub.3) layer, a hafnium oxide layer (HfO.sub.2), or a silicon dioxide (SiO.sub.2) layer.”. [0028]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure in Ota in view of Chiu such that MIS capacitor comprising the at least one depletion mode gate surrounds the at least one enhancement mode gate in order to provide adequate insulation to separate the gate electrode rom the rest of the device [0027] and since the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) (See MPEP 2144.07).
Regarding Claim 15, Ota (Fig. 23) in view of Chiu discloses the structure of claim 14, wherein
the common conducting channel comprises GaN. (gallium nitride (GaN) constituting the channel layer CH) [0063].
Regarding Claim 17, Ota (Fig. 23) in view of Chiu discloses the structure of claim 14, wherein
the island of semiconductor material comprises pGaN. (CAP, p type GaN), [0086].
Regarding Claim 19, Ota (Fig. 23) in view of Chiu discloses the structure of claim 14, wherein
the island of semiconductor material (CAP) comprises an enhancement mode gate. (GE1, CAP) connected (through C1,M1,C2) to the MIS capacitor. (Fig. 23)
Response to Arguments
Applicant's arguments filed 06/10/2026 have been fully considered but they are not persuasive.
Regarding Applicants Arguments concerning Claim 1 and prior art of Ota on page 10.
The Examiner unclear as to what the claimed differences between
“(a) a depletion mode gate comprising a field plate; (b) the depletion mode gate forming part of an MIS capacitor; (c) an enhancement mode gate electrically connected to the depletion mode gate; (d) a common conducting channel shared by both gate structures; and (e) the field plate forming part of the MIS capacitor.”
and
least one depletion mode gate (GE2, IF) comprising a field plate (extension of GE2 over ES) and
being part of a metal-insulator-semiconductor (MIS) capacitor (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) on the channel layer CH ([0195] over a semiconductor material (“a channel layer CH made of a nitride semiconductor”); and
at least one enhancement mode gate (GE1, P1, CAP) comprisinga p-doped semiconductor material (CAP, p type GaN), [0086], and a gate metal (“metal film is then patterned to form the first gate electrode portion GE1”) [0190] over the p-doped semiconductor material (CAP, p type GaN), [0086], the p-doped semiconductor material (CAP, p type GaN) of the at least one enhancement mode gate being electrically connected (connected at least through M1 and P2) to the at least one depletion mode gate, wherein
the semiconductor material (CH) comprises a common conducting channel (a (channel layer CH made of a nitride semiconductor“) shared by the at least one depletion mode gate and the at least one enhancement mode gate, and
the field plate (extension of GE2 over ES) of the at least one depletion mode gate is part of the MIS capacitor. (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) thereby forming MIS capacitor.
as disclosed by prior art of Ota.
Regarding Applicants Arguments concerning Claim 14 and prior art of Ota on pages 10-11.
The Examiner notes that prior art of Ota discloses
an island of semiconductor material (CAP, p type GaN), [0086] over a semiconductor substrate (SUB) and electrically connected (through C1,M1,C2) to the MIS capacitor (“an electron supply layer ES made of a nitride semiconductor” (as semiconductor), “an insulating film IF” (as insulator), “gate electrode GE is made of, for example, a metal film (a single metal film or a stack of metal films)”, “a metal film constituting the second gate electrode portion GE2” (as metal) thereby forming MIS capacitor),
Further, prior art of Ota discloses the island of semiconductor material comprises a p-doped GaN island (CAP, p type GaN), configured as an enhancement mode gate [0188-0191]
The Examiner notes originally filed specification discloses
“[0035] FIG. 8A shows a pGaN island (e.g., e-mode gate 19) formed on the semiconductor material 14 (e.g., conducting channel). In embodiments, the semiconductor material 14 may be deposited on the semiconductor substrate 12 using any conventional deposition method, e.g., CVD. To form the e-mode gate 19, semiconductor material 16 may be epitaxially grown on the semiconductor material 14. In embodiments, an in-situ doping (e.g., p-type dopant) may be used during the epitaxial growth process. Conductive material 18, e.g., TiN, may be deposited on the semiconductor material 16. The semiconductor material 16 and conductive material 18 undergo conventional lithography and etching processes to form the e-mode gate 19, e.g., GaN island. In embodiments, the conductive material 18 may undergo an additional selective pull-back etching process to form the e-mode gate 19.”
Therefore, as long as p-doped GaN island (CAP) is on semiconductor material (ES) and/or p-doped GaN island (CAP) and conductive material (GE1) are formed (See Fig. 15, 16, 23) the limitation “the island of semiconductor material comprises a p-doped GaN island, configured as an enhancement mode gate” is considered to be met.
Further, arguments concerning dependent claim 2-8, 10, 15, 17, 19 have been addressed with the response to Claims 1 and 14 above.
Regarding Applicants Arguments concerning Claim 3 rejected under 35 U.S.C. 103 as being unpatentable over Ota et al. (US 2014/0209922 A1).
The Examiner notes that Claim 3 rejected under 35 U.S.C. 102(A1) as being anticipated by Ota et al. (US 2014/0209922 A1) in Office Action dated 03/40/2026.
Therefore, arguments concerning obviousness over prior art of Ota as applied to Claim 3 filed 01//27/2026 are considered to be moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DMITRIY YEMELYANOV/ Examiner, Art Unit 2891
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