DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/06/2025 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/17/2025 was filed after the mailing date of the Final Office Action on 08/12/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Acknowledgment is made of the amendment filed 11/06/2025, in which: claims 1 and 10 are amended; claims 3 and 16-19 stand withdrawn; and the rejection of the claims are traversed. Claims 1-2, 4-15, and 21 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4-7, 9-12, 15, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak et al. (US Publication 20210036087) in view of Xie et al. (US Publication 20210091120).
Regarding independent claim 1, Kwak teaches a display panel (fig. 1, DA) comprising:
a light emitting element (fig. 3, OLED); and
a pixel circuit (PC) electrically connected to the light emitting element, the pixel circuit comprising a first transistor (fig. 4, TFT2), the first transistor comprising:
a first gate (GEa);
an oxide semiconductor member (AO, paragraph 0111) overlapping the first gate;
a second gate (GEb) overlapping the oxide semiconductor member;
a first insulating layer (113) disposed between the first gate and the oxide semiconductor member, wherein the oxide semiconductor member is disposed directly on the first insulating layer (fig. 4, AO is directly disposed above 113); and
a second insulating layer (114) disposed between the oxide semiconductor member and the second gate, wherein the oxide semiconductor member is disposed between the first gate and the second gate (fig. 4) and comprises:
wherein the pixel circuit further comprises a second transistor (TFT1) comprising a silicon semiconductor member (AS, paragraph 0103), and an overlapping electrode (CE2), and
wherein the overlapping electrode overlaps the silicon semiconductor member (fig. 4), is disposed directly on the first insulating layer (can be rearranged to be disposed directly on top of 113 per MPEP 2144.04), and comprises a same transparent conductive oxide as the oxide semiconductor member (paragraph 0115, “fourth electrode CE4 of the second capacitor Cbt may include an oxide semiconductor”, material used in CE4 can be used in CE2 per MPEP 2144.07).
Kwak does not teach a first semiconductor layer; and a second semiconductor layer disposed between the first semiconductor layer and the second gate in a thickness direction of the oxide semiconductor member, wherein an atomic percent of oxygen of the first semiconductor layer is lower than an atomic percent of oxygen of the second semiconductor layer.
Xie teaches a first semiconductor layer (fig. 10, 41); and
a second semiconductor layer (42) disposed between the first semiconductor layer and the second gate in a thickness direction of the oxide semiconductor member (fig. 10, 42 disposed between first gate 20 and 70 which occupies space for second gate of Kwak), wherein an atomic percent of oxygen of the first semiconductor layer is lower than an atomic percent of oxygen of the second semiconductor layer (paragraph 0059 and paragraph 0062, first semiconductor layer does not use material containing oxygen and therefore has a lower atomic percent of oxygen than the second semiconductor layer).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Kwak and the first and second semiconductor layers of Xie in order to facilitate “the active layer of the TFT device to possess combined excellent properties of two semiconductor materials and lowering the production cost” (Xie paragraph 008).
Regarding dependent claim 4, Kwak in view of Xie teaches the display panel of claim 1.
Kwak in view of Xie does not explicitly teach wherein the atomic percent of oxygen of the first semiconductor layer is lower than the atomic percent of oxygen of the second semiconductor layer by at least 2 atomic percent, however, Xie discloses the material of the first semiconductor layer to not contain oxygen (paragraph 0059) and the material of the second semiconductor layer to contain oxygen (paragraph 0062).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to obtain the specified oxygen atomic percent difference between the first and second semiconductor layers with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding dependent claim 5, Kwak further teaches the display panel of claim 1, wherein the oxide semiconductor member comprises an indium gallium zinc oxide (paragraph 0111, “the second semiconductor layer AO may include, for example, an In—Ga—Zn—O (IGZO) semiconductor, an In—tin (Sn)—Zn—O (ITZO) semiconductor, and/or an In—Ga—Sn—Zn—O (IGTZO) semiconductor”).
Kwak in view of Xie does not explicitly teach and wherein the atomic percent of oxygen of the first semiconductor layer is in a range from 40 atomic percent to 60 atomic percent, however, Xie discloses the material of the first semiconductor layer to not contain oxygen (paragraph 0059) and the material of the second semiconductor layer to contain oxygen (paragraph 0062).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to obtain the specified oxygen atomic percent range of the first semiconductor layer with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding dependent claim 6, Kwak further teaches the display panel of claim 1, wherein the pixel circuit further comprises a capacitor (fig. 4, Cbt), wherein the capacitor comprises:
a first electrode (CE4) disposed on the first insulating layer (fig. 4, CE4 disposed on top of 113) and comprising a same transparent conductive oxide as the oxide semiconductor member (paragraph 0115); and
a second electrode (CE3), wherein the first electrode and the second electrode overlap each other (fig. 4).
Regarding dependent claim 7, Kwak further teaches the display panel of claim 6, wherein the first insulating layer is partially disposed between the first electrode and the second electrode (fig. 4, first insulating layer 113 is disposed between CE4 and CE3).
Regarding dependent claim 9, Xie further teaches the display panel of claim 1, wherein a maximum thickness of the first insulating layer (fig. 10, 30) is less than a maximum thickness of the second insulating layer (60) in the thickness direction of the oxide semiconductor member (maximum thickness of 30 is less than a maximum thickness of 60).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Kwak and the first/second insulating layer thicknesses per the reason(s) stated above in claim 1.
Regarding dependent claim 10, Kwak further teaches the display panel of claim 1, further comprises:
disposed between the overlapping electrode and the silicon semiconductor member (fig. 4), and
wherein the overlapping electrode overlaps the gate electrode (fig. 4)
Regarding dependent claim 11, Kwak further teaches the display panel of claim 10, wherein the first insulating layer is partially disposed between the gate electrode and the overlapping electrode (fig. 4, CE2 can be rearranged such that 113 is disposed between GE1 and CE2 per MPEP 2144.04).
Regarding dependent claim 12, Kwak further teaches the display panel of claim 10, wherein the first gate of the first transistor and the gate electrode of the second transistor comprise a same material (paragraphs 0105, 0108, and 112, GEa and GE1 comprise a same material).
Regarding dependent claim 15, Kwak teaches the display panel of claim 1, wherein the second semiconductor layer (fig. 4, second semiconductor layer of Xie inside AO) comprises a channel (C2), a drain (D2), and a source (S2), and wherein the channel is overlapped by the second gate (fig. 4, Geb overlaps C2) and is positioned between the drain and the source (fig. 4).
Regarding dependent claim 21, Xie further teaches display panel of claim 1, wherein the first semiconductor layer has a side surface in direct contact with the second insulation layer (fig. 10, side surfaces of 41 in direct contact with 60).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Kwak and the first semiconductor layer side surface of Xie per the reason(s) stated above in claim 1.
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kwak in view of Xie as applied to claim 1 above, and further in view of Koezuka et al. (US Publication 20180219102).
Regarding dependent claim 2, Kwak in view of Xie teaches the display panel of claim 1.
Kwak in view of Xie does not teach wherein a thickness of the first semiconductor layer is in a range of 100 angstroms to 150 angstroms, and wherein a thickness of the second semiconductor layer is in a range of 100 angstroms to 150 angstroms.
Koezuka teaches wherein a thickness of the first semiconductor layer is in a range of 100 angstroms to 150 angstroms, and wherein a thickness of the second semiconductor layer is in a range of 100 angstroms to 150 angstroms (paragraph 0094).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Kwak in view of Xie and the first/second semiconductor layer thicknesses of Koezuka in order to reduce variations in threshold voltage and lower channel resistance (paragraph 0095).
Regarding dependent claim 8, Kwak further teaches the display panel of claim 7, wherein the first insulating layer comprises a silicon oxide layer and a silicon nitride layer disposed on the silicon oxide layer (paragraph 0109).
Kwak in view of Xie does not teach wherein a thickness of the first insulating layer is in a range from 1000 angstroms to 1500 angstroms.
Koezuka teaches wherein a thickness of the first insulating layer is in a range from 1000 angstroms to 1500 angstroms (paragraph 0128, thickness of first insulating layer 104 can be 100-3000 nm which encompasses specified range but also discloses “equal to 100 nm” which is 1000 angstroms).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Kwak in view of Xie and the first insulating layer thickness of Koezuka in order to increase the amount of oxygen released (Koezuka paragraph 0128).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Koezuka in view of Kim, as applied to claim 1, and further in view of Park et al. (US Publication 20210036029).
Regarding dependent claim 13, Kwak further teaches the display panel of claim 1, further comprising:
a third insulating layer (fig. 4, 115) covering the second gate.
Kwak in view of Xie does not teach a connection electrode disposed on the third insulating layer and electrically connecting the second gate and the first gate.
Park teaches a connection electrode (fig. 7, 330) disposed on the third insulating layer (160) and electrically connecting the second gate and the first gate (fig. 7, 330 connects 360 and 350).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Kwak in view of Xie and the connection electrode of Park in order to connect the conductive region and light blocking layer to each other (Park paragraph 0161).
Regarding dependent claim 14, Park further teaches the display panel of claim 13, wherein the connection electrode is connected to the second gate via a first contact hole (fig. 7, CT1) through the third insulating layer and is connected to the first gate via a second contact hole (CT3) through the first insulating layer, the second insulating layer, and the third insulating layer (fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Kwak in view of Xie and the contact hole of Park per the reason(s) stated above in claim 13.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-15, and 21 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 11/06/2025 have been fully considered but are not persuasive.
Applicant argues on pages 9-13 of the instant Remarks: “In Kim, the active layers with different oxygen atom percentages correspond to configurations within different transistors. The reason the first active layer ACT1 has a different oxygen atom percentage than the second active layer ACT2 is due to the oxide layer OXL… assuming for purposes of argument only that the first active layer ACT1 and the second active layer ACT2 did overlap, the first active layer ACT1 and the second active layer ACT2 would have the same oxygen atom percentages as the oxide layer OXY would not be present to inject oxygen into the first active layer ACT1. Further… FIG. 4 of Kim 084 does not teach or suggest that an oxide semiconductor member is disposed directly on the first insulating layer 116 on which the auxiliary gate electrode 227 is placed. Kim does not cure this deficiency in Koezuka and Kim 084.”
However, as stated above, Xie teaches wherein an atomic percent of oxygen of the first semiconductor layer is lower than an atomic percent of oxygen of the second semiconductor layer (paragraph 0059 and paragraph 0062, first semiconductor layer 41 does not use material containing oxygen and therefore has a lower atomic percent of oxygen than the second semiconductor layer 42), and Kwak teaches wherein the overlapping electrode overlaps the silicon semiconductor member (fig. 4), [and] is disposed directly on the first insulating layer (can be rearranged to be disposed directly on top of 113 per MPEP 2144.04). Therefore, Kwak in view of Xie teaches the limitations as recited in amended claim 1, as well as its dependent claims in combination with the other cited sources above.
Conclusion
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897