7DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/01/2026 was filed after the mailing date of the Non-Final Office Action on 01/14/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Acknowledgment is made of the amendment filed 04/10/2026, in which: claims 1, 5, and 8 are amended; claims 3 and 16-19 stand rejected; and the rejection of the claims are traversed. Claims 1-2, 4-15 and 21 are currently pending an Office action on the merits as follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10-12 recites the limitations "the second transistor", “the silicon semiconductor member”, and “the overlapping electrode”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 4-7, 9-12, 15, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Ono et al. (US Publication 20180277614) in view of Kim et al. (US Publication 20130280859).
Regarding independent claim 1, Ono teaches a display panel (fig. 1, 14) comprising:
a light emitting element (fig. 2, 26); and
a pixel circuit (22) electrically connected to the light emitting element, the pixel circuit comprising a first transistor (28), the first transistor comprising:
a first gate (fig. 4, 416);
an oxide semiconductor member (424) overlapping the first gate;
a second gate (Gate2) overlapping the oxide semiconductor member;
a first insulating layer (422) disposed between the first gate and the oxide semiconductor member, wherein the oxide semiconductor member is disposed directly on the first insulating layer (fig. 4, 424 is directly disposed above 416); and
a second insulating layer (428) disposed between the oxide semiconductor member and the second gate, and entirely covering the oxide semiconductor member (fig. 4) wherein the oxide semiconductor member is disposed between the first gate and the second gate (fig. 4).
Ono does not teach [wherein the oxide semiconductor member] comprises: a first semiconductor layer comprising an indium gallium zinc oxide; and a second semiconductor layer comprising an indium gallium zinc oxide, and disposed between the first semiconductor layer and the second gate in a thickness direction of the oxide semiconductor member, wherein an atomic percent of oxygen of the first semiconductor layer is lower than an atomic percent of oxygen of the second semiconductor layer.
Kim teaches [wherein the oxide semiconductor member] (fig. 1, 130) comprises:
a first semiconductor layer (132) comprising an indium gallium zinc oxide (paragraph 0057, “a first IGZO thin layer 132”); and
a second semiconductor layer (134) comprising an indium gallium zinc oxide (paragraph 0057, “a second IGZO thin layer 134”), and disposed between the first semiconductor layer and the second gate in a thickness direction of the oxide semiconductor member (134 disposed between 132 and area above which holds space for second gate of Ono).
Ono in view of Kim does not explicitly teach wherein an atomic percent of oxygen of the first semiconductor layer is lower than an atomic percent of oxygen of the second semiconductor layer, however, Kim discloses the “introduced amount of the oxidation source may be also controlled” (paragraph 0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the atomic percent of oxygen in the first semiconductor layer lower than atomic percent of oxygen in second semiconductor layer in order to control characteristics of the semiconductor layers such as mobility and electrical conductivity (Kim paragraph 0057) with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding dependent claim 4, Ono in view of Kim teaches the display panel of claim 1.
Ono in view of Kim does not explicitly teach wherein the atomic percent of oxygen of the first semiconductor layer is lower than the atomic percent of oxygen of the second semiconductor layer by at least 2 atomic percent, however, Kim discloses the “introduced amount of the oxidation source may be also controlled” (paragraph 0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to obtain the specified oxygen atomic percent difference between the first and second semiconductor layers with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding dependent claim 5, Ono in view of Kim teaches the display panel of claim 1.
Ono in view of Kim does not explicitly teach and wherein the atomic percent of oxygen of the first semiconductor layer is in a range from 40 atomic percent to 60 atomic percent, however, Kim discloses the “introduced amount of the oxidation source may be also controlled” (paragraph 0057).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to obtain the specified oxygen atomic percent range of the first semiconductor layer with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990).
Regarding dependent claim 6, Ono further teaches the display panel of claim 1, wherein the pixel circuit further comprises a capacitor (fig. 2, Cst), wherein the capacitor comprises:
a first electrode (fig. 4, 426) disposed on the first insulating layer (paragraph 0053) and comprising a same transparent conductive oxide as the oxide semiconductor member (paragraph 0052); and
a second electrode (420), wherein the first electrode and the second electrode overlap each other (fig. 4).
Regarding dependent claim 7, Ono further teaches the display panel of claim 6, wherein the first insulating layer is partially disposed between the first electrode and the second electrode (fig. 4, paragraph 0053).
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Regarding dependent claim 9, Ono further teaches the display panel of claim 1, wherein a maximum thickness of the first insulating layer (see figure below) is less than a maximum thickness of the second insulating layer (see figure below) in the thickness direction of the oxide semiconductor member.
Regarding dependent claim 15, Ono further teaches the display panel of claim 1, wherein the second semiconductor layer (fig. 4, second semiconductor layer of Kim inside 424) comprises a channel (Oxide), a drain (area of 424 right of Oxide), and a source (area of 424 left of Oxide), and wherein the channel is overlapped by the second gate (fig. 4, Gate2 overlaps Oxide) and is positioned between the drain and the source (fig. 4).
Regarding dependent claim 21, Ono further teaches display panel of claim 1, wherein the first semiconductor layer has a side surface in direct contact with the second insulation layer (fig. 4, side surfaces of 424 in direct contact with 428).
Claims 2 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ono in view of Kim as applied to claim 1 above, and further in view of Koezuka et al. (US Publication 20180219102).
Regarding dependent claim 2, Ono in view of Kim teaches the display panel of claim 1.
Ono in view of Kim does not teach wherein a thickness of the first semiconductor layer is in a range of 100 angstroms to 150 angstroms, and wherein a thickness of the second semiconductor layer is in a range of 100 angstroms to 150 angstroms.
Koezuka teaches wherein a thickness of the first semiconductor layer is in a range of 100 angstroms to 150 angstroms, and wherein a thickness of the second semiconductor layer is in a range of 100 angstroms to 150 angstroms (paragraph 0094).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ono in view of Kim and the first/second semiconductor layer thicknesses of Koezuka in order to reduce variations in threshold voltage and lower channel resistance (paragraph 0095).
Regarding dependent claim 8, Ono in view of Kim teaches the display panel of claim 7.
Ono in view of Kim does not teach wherein the first insulating layer comprises a silicon nitride oxide
Koezuka teaches wherein the first insulating layer comprises a silicon nitride oxide oxide layer (paragraphs 0129-0130), and wherein a thickness of the first insulating layer is in a range from 1000 angstroms to 1500 angstroms (paragraph 0128, thickness of first insulating layer 104 can be 100-3000 nm which encompasses specified range but also discloses “equal to 100 nm” which is 1000 angstroms).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ono in view of Kim and the first insulating layer thickness of Koezuka in order to increase the amount of oxygen released (Koezuka paragraph 0128).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ono in view of Kim, as applied to claim 1, and further in view of Kwak et al. (US Publication 20210036087).
Regarding dependent claim 10, Ono further teaches the display panel of claim 1, wherein the second transistor (fig. 2, 30) further comprises:
a gate electrode (fig. 4, Gate1) overlapping the silicon semiconductor member (406, paragraph 0049).
Ono in view of Kim does not teach and disposed between the overlapping electrode and the silicon semiconductor member, and wherein the overlapping electrode overlaps the gate electrode.
Kwak teaches and disposed between the overlapping electrode (fig. 4, CE2) and the silicon semiconductor member (AS), and wherein the overlapping electrode overlaps the gate electrode (GE1).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ono in view of Kim and the overlapping electrode of Kwak in order to maintain the voltage applied to the gate electrode (Kwak paragraph 0090).
Regarding dependent claim 11, Kwak further teaches the display panel of claim 10, wherein the first insulating layer (fig. 4, 112) is partially disposed between the gate electrode and the overlapping electrode.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ono in view of Kim and the location of the first insulating layer relative to the gate and overlapping electrodes of Kwak per the reason(s) stated above in claim 10.
Regarding dependent claim 12, Kwak further teaches the display panel of claim 10, wherein the first gate of the first transistor and the gate electrode of the second transistor comprise a same material (paragraphs 0105, 0108, and 112, GEa and GE1 comprise a same material).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ono in view of Kim and the material of the gate electrodes of Kwak per the reason(s) stated above in claim 10.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ono in view of Kim, as applied to claim 1, and further in view of Park et al. (US Publication 20210036029).
Regarding dependent claim 13, Ono further teaches the display panel of claim 1, further comprising:
a third insulating layer (fig. 4, 430) covering the second gate.
Ono in view of Kim does not teach a connection electrode disposed on the third insulating layer and electrically connecting the second gate and the first gate.
Park teaches a connection electrode (fig. 7, 330) disposed on the third insulating layer (160) and electrically connecting the second gate and the first gate (fig. 7, 330 connects 360 and 350).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display device of Ono in view of Kim and the connection electrode of Park in order to connect the conductive region and light blocking layer to each other (Park paragraph 0161).
Regarding dependent claim 14, Park further teaches the display panel of claim 13, wherein the connection electrode is connected to the second gate via a first contact hole (fig. 7, CT1) through the third insulating layer and is connected to the first gate via a second contact hole (CT3) through the first insulating layer, the second insulating layer, and the third insulating layer (fig. 7).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Ono in view of Kim and the contact hole of Park per the reason(s) stated above in claim 13.
Response to Arguments
Applicant’s arguments with respect to claims 1-2, 4-15, and 21 have been fully considered but are moot in view of the new grounds of rejection (Amendments).
Applicant’s arguments filed 04/10/2026 have been fully considered but are not persuasive.
Applicant argues on pages 8-9 of the instant Remarks: “Kwak does not teach or suggest anything regarding a first semiconductor layer and a second conductor layer as currently amended. While Xie discloses a semiconductor pattern 41 and an oxide semiconductor pattern 42 there is no disclosure that the first semiconductor pattern comprises an indium gallium zinc oxide and the second semiconductor pattern comprises an indium gallium zinc oxide as currently claimed. Instead in Xie para. [0075] states that "first active layer 41 adopts a new semiconductor material of carbon nanotubes, graphene, silicon carbide, molybdenum disulfide or organic semiconductor materials." With no disclosure of an indium gallium zinc oxide material. Additionally, neither Kwak nor Xie in combination disclose a second insulating layer disposed between the oxide semiconductor member and the second gate, and entirely covering the oxide semiconductor member. As can be seen in Kwak fig. 1 the alleged second insulating layer element 114 is only disposed on top of region C2 of the semiconductor layer and does not entirely cover the semiconductor member as claimed. Similarly, Xie does not even disclose a second insulating layer let alone that it is entirely covering the oxide semiconductor member.”
However, as stated above, Kim teaches a first semiconductor layer (fig. 4, 132) comprising an indium gallium zinc oxide (paragraph 0057, “a first IGZO thin layer 132”) and a second semiconductor layer (134) comprising an indium gallium zinc oxide (paragraph 0057, “a second IGZO thin layer 134”), and Ono teaches a second insulating layer (428) disposed between the oxide semiconductor member and the second gate, and entirely covering the oxide semiconductor member (fig. 4). Therefore, the rejection to claim 1 stands.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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