Prosecution Insights
Last updated: October 01, 2026
Application No. 17/902,551

SiC MOSFET Including Trench with Rounded Corners

Non-Final OA §103
Filed
Sep 02, 2022
Examiner
DEGRASSE, IAN ISAAC
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Inc.
OA Round
5 (Non-Final)
81%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
83%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
21 granted / 26 resolved
+12.8% vs TC avg
Minimal +2% lift
Without
With
+1.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
49 currently pending
Career history
78
Total Applications
across all art units

Statute-Specific Performance

§103
58.0%
+18.0% vs TC avg
§102
29.0%
-11.0% vs TC avg
§112
13.0%
-27.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 26 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 28, 2025 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2, 4-5, 7-10, 12, 14-15, 17 and 19 are rejected under 35 U.S.C. 103 as being obvious over US 2021/0408279 A1 to Siemieniec et al. (hereinafter “Siemieniec” – previously cited reference). Regarding claim 1, Siemieniec discloses a method, comprising: providing a masking layer over a silicon carbide (SiC) layer, wherein an opening is formed in the masking layer (hard mask 421 disposed over silicon carbide body 100 and having a hard mask opening 429 formed therein; Fig. 1B; paragraph [0079]); providing a sidewall spacer along only a sidewall of the opening of the masking layer (mask spacers 423 formed along only sidewalls of hard mask opening 429 and not along any other surface of the hard mask 421; Figs. 1B, 1D; paragraphs [0080], [0086]); forming an implant region within the SiC layer by directing ions through the opening defined by the sidewall spacer (ion implant regions 762 formed via ion implantation through hard mask opening 429; Fig. 1D; paragraph [0086]); performing a first etch to the SiC layer after another implant region is formed within the SiC layer, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess (silicon carbide body 100 is etched to form trench 450 after implant regions 761 are formed, where trench 450 has left and right shoulder structures therearound in form of spacer mask 420 as shown in Figs. 1A-1D; paragraphs [0077], [0080], [0086]); and performing a second etch to remove the set of shoulder regions (spacer etch is performed to remove left and right shoulder structures in form of spacer mask 420 as shown in Figs. 1C-1E; paragraphs [0085], [0087]). Siemieniec fails to explicitly disclose performing a first etch to the SiC layer after the implant region is formed within the SiC layer. However, Siemieniec already discloses etching out the trench 450 after first implant regions 761 are formed into body 100 (see Fig. 1A; paragraphs [0077]-[0078]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to perform trench 450 formation prior to implant region 762 formation (akin to the trench 450 being formed after implant region 761 formation) in order to potentially provide no need for the conformal spacer-mask deposition and anisotropic spacer etch, use of a conventional uniform high-energy implant into a flat wafer surface as opposed to constraints imposed by trench sidewalls and unintended implantation, and use of a functional residual doped region under the finished trench bottom serving as shielding region 762 all the same. Further, forming trench 450 after forming implant region 762 is a routine, predictable variation of the identical technique already disclosed for trench 450 formation after forming implant region 761. No new process module or unexpected result is required given that one would simply perform the deep implant on the planar surface and let the subsequent trench etch define the final location of the residual doped pocket under the trench bottom. Regarding claim 2, Siemieniec discloses the method of claim 1, further comprising removing the masking layer following the second etch (spacer mask 420 including hard mask 421 removed by spacer etch; Figs. 1C-1E; paragraphs [0085], [0087]). Regarding claim 3, Siemieniec discloses the method of claim 2, wherein the second etch removes the sidewall spacer (spacer etch removes spacer mask 420 including mask spacers 423; Figs. 1C-1E; paragraphs [0085]-[0087]), and wherein the second etch forms an apex in the central recess of the trench (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]). Siemieniec fails to disclose wherein the first etch removes the sidewall spacer. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Siemieniec to use the first etch, instead of the second etch, to remove the sidewall spacer, because simply substituting the second etch of Siemieniec to be a first etch of the process would yield the same resulting structure which is a predictable result. Regarding claim 4, Siemieniec discloses the method of claim 1, wherein the second etch forms an apex in the central recess (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]). Regarding claim 5, Siemieniec discloses the method of claim 1, wherein the implant region is located in a central area of an etch region of the SiC layer (implant regions 761, 762 located in part in central area of trench 450 within silicon carbide body 100 as shown in Fig. 1D), wherein directing ions through the opening defined by the sidewall spacer causes increased damage to the implant region relative to a remainder of the etch region, and wherein the increased damage increases an etch rate of the implant region of the SiC layer during the first etch (ion implantation directed through mask opening 429 inherently increases damage to lattice structure of implant region 761 which inherently increases etch rate during formation of trench 450 through implant region 761 as shown in Figs. 1A-1B). Regarding claim 7, Siemieniec discloses the method of claim 1, wherein directing ions through the sidewall spacer comprises delivering at least one of the following ion species into the opening: oxygen, argon, helium, and hydrogen, phosphorus, nitrogen, and aluminum (silicon carbide body 100 may be implanted with ions including oxygen, hydrogen, phosphorous, nitrogen and aluminum; paragraph [0033]). Regarding claim 8, Siemieniec discloses the method of claim 1, wherein the first etch forms the central recess to a first depth relative to an uppermost surface of the SiC layer, wherein the second etch forms the central recess to a second depth relative to the uppermost surface of the SiC layer, and wherein the second depth is greater than the first depth (first etch forms trench 450 with mask layer 422 at bottom surface 453, and spacer etch forms a new inverted apex shape at bottom surface 453 of trench 450 lower than before as shown in Figs. 1C-1D; paragraph [0085]). Regarding claim 9, Siemieniec discloses a method of forming a silicon carbide (SiC) metal-oxide-semiconductor field- effect transistor (MOSFET), the method comprising: providing a masking layer over a SiC layer, wherein an opening is formed in the masking layer, and wherein the opening defines an etch region in the SiC layer (method of producing SiC MOSFET where hard mask 421 disposed over silicon carbide body 100 and having a hard mask opening 429 formed therein for subsequent etching therethrough; Fig. 1B; paragraphs [0079], [0108]); providing a sidewall spacer along only a sidewall of the opening of the masking layer (mask spacers 423 formed along only sidewalls of hard mask opening 429 and not along any other surface of the hard mask 421; Figs. 1B, 1D; paragraphs [0080], [0086]); forming an implant region in a central area of the etch region by directing ions into the SiC layer, through the opening defined by the sidewall spacer (ion implant regions 761, 762 disposed in middle of etched area and formed via ion implantation through hard mask opening 429; Fig. 1D; paragraph [0086]); performing a first etch to the SiC layer after another implant region is formed in the central area of the etch region, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess (silicon carbide body 100 is etched to form trench 450 after implant regions 761 are formed, where trench 450 has left and right shoulder structures therearound in form of spacer mask 420 as shown in Figs. 1A-1D; paragraphs [0077], [0080], [0086]); and performing a second etch to remove the set of shoulder regions (spacer etch is performed to remove left and right shoulder structures in form of spacer mask 420 as shown in Figs. 1C-1E; paragraphs [0085], [0087]). Siemieniec fails to explicitly disclose performing a first etch to the SiC layer after the implant region is formed in the central area of the etch region. However, Siemieniec already discloses etching out the trench 450 after first implant regions 761 are formed into body 100 (see Fig. 1A; paragraphs [0077]-[0078]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to perform trench 450 formation prior to implant region 762 formation (akin to the trench 450 being formed after implant region 761 formation) in order to potentially provide no need for the conformal spacer-mask deposition and anisotropic spacer etch, use of a conventional uniform high-energy implant into a flat wafer surface as opposed to constraints imposed by trench sidewalls and unintended implantation, and use of a functional residual doped region under the finished trench bottom serving as shielding region 762 all the same. Further, forming trench 450 after forming implant region 762 is a routine, predictable variation of the identical technique already disclosed for trench 450 formation after forming implant region 761. No new process module or unexpected result is required given that one would simply perform the deep implant on the planar surface and let the subsequent trench etch define the final location of the residual doped pocket under the trench bottom. Regarding claim 10, Siemieniec discloses the method of claim 9, further comprising removing the masking layer following the second etch (spacer mask 420 including hard mask 421 removed by spacer etch; Figs. 1C-1E; paragraphs [0085], [0087]). Regarding claim 11, Siemieniec discloses the method of claim 9, wherein the second etch removes the sidewall spacer (spacer etch removes spacer mask 420 including mask spacers 423; Figs. 1C-1E; paragraphs [0085]-[0087]), and wherein the second etch forms an apex in the central recess of the trench (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]). Siemieniec fails to disclose wherein the first etch removes the sidewall spacer. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Siemieniec to use the first etch, instead of the second etch, to remove the sidewall spacer, because simply substituting the second etch of Siemieniec to be a first etch of the process would yield the same resulting structure which is a predictable result. Regarding claim 12, Siemieniec discloses the method of claim 9, wherein directing ions through the opening defined by the sidewall spacer causes increased damage to the implant region relative to a remainder of the etch region, and wherein the increased damage increases an etch rate of the implant region of the SiC layer during the first etch (ion implantation directed through mask opening 429 inherently increases damage to lattice structure of implant region 761 which inherently increases etch rate during formation of trench 450 through implant region 761 as shown in Figs. 1A-1B). Regarding claim 14, Siemieniec discloses the method of claim 9, wherein the first etch forms the central recess to a first depth relative to an uppermost surface of the SiC layer, wherein the second etch forms the central recess to a second depth relative to the uppermost surface of the SiC layer, and wherein the second depth is greater than the first depth (first etch forms trench 450 with mask layer 422 at bottom surface 453, and spacer etch forms a new inverted apex shape at bottom surface 453 of trench 450 lower than before as shown in Figs. 1C-1D; paragraph [0085]). Regarding claim 15, Siemieniec discloses a method of forming a silicon carbide (SiC) metal-oxide-semiconductor field- effect transistor (MOSFET), the method comprising: providing a masking layer over a SiC layer, wherein an opening is formed in the masking layer, and wherein the opening defines an etch region in the SiC layer (method of producing SiC MOSFET where hard mask 421 disposed over silicon carbide body 100 and having a hard mask opening 429 formed therein for subsequent etching therethrough; Fig. 1B; paragraphs [0079], [0108]); providing a sidewall spacer along only a sidewall of the opening of the masking layer (mask spacers 423 formed along only sidewalls of hard mask opening 429 and not along any other surface of the hard mask 421; Figs. 1B, 1D; paragraphs [0080], [0086]); forming an implant region in a central area of the etch region by directing ions into the SiC layer, through the opening defined by the sidewall spacer (ion implant regions 761, 762 disposed in middle of etched area and formed via ion implantation through hard mask opening 429; Fig. 1D; paragraph [0086]); performing a first etch to the SiC layer after another implant region is formed in the central area of the etch region, wherein the first etch forms a trench having a central recess and a set of shoulder regions adjacent the central recess (silicon carbide body 100 is etched to form trench 450 after implant regions 761 are formed, where trench 450 has left and right shoulder structures therearound in form of spacer mask 420 as shown in Figs. 1A-1D; paragraphs [0077], [0080], [0086]); and performing a second etch to the trench to remove the set of shoulder regions (spacer etch is performed to remove left and right shoulder structures in form of spacer mask 420 as shown in Figs. 1C-1E; paragraphs [0085], [0087]). Siemieniec fails to explicitly disclose performing a first etch to the SiC layer after the implant region is formed in the central area of the etch region. However, Siemieniec already discloses etching out the trench 450 after first implant regions 761 are formed into body 100 (see Fig. 1A; paragraphs [0077]-[0078]). Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to perform trench 450 formation prior to implant region 762 formation (akin to the trench 450 being formed after implant region 761 formation) in order to potentially provide no need for the conformal spacer-mask deposition and anisotropic spacer etch, use of a conventional uniform high-energy implant into a flat wafer surface as opposed to constraints imposed by trench sidewalls and unintended implantation, and use of a functional residual doped region under the finished trench bottom serving as shielding region 762 all the same. Further, forming trench 450 after forming implant region 762 is a routine, predictable variation of the identical technique already disclosed for trench 450 formation after forming implant region 761. No new process module or unexpected result is required given that one would simply perform the deep implant on the planar surface and let the subsequent trench etch define the final location of the residual doped pocket under the trench bottom. Regarding claim 16, Siemieniec discloses the method of claim 15, wherein the second etch removes the sidewall spacer (spacer etch removes spacer mask 420 including mask spacers 423; Figs. 1C-1E; paragraphs [0085]-[0087]), and wherein the second etch forms an apex in the central recess of the trench (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]). Siemieniec fails to disclose wherein the first etch removes the sidewall spacer. However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Siemieniec to use the first etch, instead of the second etch, to remove the sidewall spacer, because simply substituting the second etch of Siemieniec to be a first etch of the process would yield the same resulting structure which is a predictable result. Regarding claim 17, Siemieniec discloses the method of claim 15, wherein directing ions through the opening defined by the sidewall spacer causes increased damage to the implant region relative to a remainder of the etch region, and wherein the increased damage increases an etch rate of the implant region of the SiC layer during the first etch (ion implantation directed through mask opening 429 inherently increases damage to lattice structure of implant region 761 which inherently increases etch rate during formation of trench 450 through implant region 761 as shown in Figs. 1A-1B). Regarding claim 19, Siemieniec discloses the method of claim 15, wherein the first etch forms the central recess to a first depth relative to an uppermost surface of the SiC layer, wherein the second etch forms the central recess to a second depth relative to the uppermost surface of the SiC layer, and wherein the second depth is greater than the first depth (first etch forms trench 450 with mask layer 422 at bottom surface 453, and spacer etch forms a new inverted apex shape at bottom surface 453 of trench 450 lower than before as shown in Figs. 1C-1D; paragraph [0085]). Claims 6, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in further view of US 11,302,776 B1 to Sundaresan et al. (hereinafter “Sundaresan” – previously cited reference). Regarding claims 6, 13 and 18, Siemieniec discloses the method of claims 1, 9 and 15, wherein providing the masking layer comprises depositing a hardmask atop the SiC layer (hard mask 421 disposed over silicon carbide body 100; Fig. 1B; paragraph [0079]), and wherein directing ions into the SiC layer comprises delivering at least one of the following ion species through the opening: oxygen, argon, helium, hydrogen, phosphorus, nitrogen, and aluminum (silicon carbide body 100 may be implanted with ions including oxygen, hydrogen, phosphorous, nitrogen and aluminum; paragraph [0033]). Siemieniec fails to disclose a silicon dioxide or silicon nitride hardmask. However, Sundaresan discloses a silicon dioxide or silicon nitride hardmask (hard mask 206 having two silicon oxide layers with a silicon nitride layer therebetween; column 16, lines 55-59). Siemieniec and Sundaresan are both considered to be analogous to the claimed invention because they are in the same field of semiconductor structure fabrication methods. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Sundaresan in order to at least potentially provide high etch selectivity, compatibility with wet etching, and thermal stability. Response to Arguments Applicant's arguments filed July 22, 2026 have been fully considered. Applicant presents amendment to claims 1, 9 and 15 with corresponding arguments. Examiner agrees that Siemieniec does not explicitly disclose the amended limitation. However, Siemieniec already discloses trench 450 formation after implant region 761 is formed. Further, while Applicant asserts the reverse order of operation in Siemieniec would not be obvious to implement, Examiner asserts that the reverse order would provide no need for the conformal spacer-mask deposition and anisotropic spacer etch, use of a conventional uniform high-energy implant into a flat wafer surface as opposed to constraints imposed by trench sidewalls and unintended implantation, and use of a functional residual doped region under the finished trench bottom serving as shielding region 762 all the same. Accordingly, a new ground of rejection that was necessitated by the amendments has been made under 35 USC 103 using Siemieniec as outlined above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /IAN DEGRASSE/Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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Prosecution Timeline

Show 12 earlier events
Feb 03, 2026
Response Filed
May 01, 2026
Final Rejection mailed — §103
Jun 25, 2026
Examiner Interview Summary
Jun 25, 2026
Applicant Interview (Telephonic)
Jul 22, 2026
Response after Non-Final Action
Aug 03, 2026
Request for Continued Examination
Aug 04, 2026
Response after Non-Final Action
Aug 10, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

5-6
Expected OA Rounds
81%
Grant Probability
83%
With Interview (+1.8%)
3y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 26 resolved cases by this examiner. Grant probability derived from career allowance rate.

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