DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-5, 7-10, 12, 14-15, 17 and 19 are rejected under 35 U.S.C. 103 as being obvious over US 2021/0408279 A1 to Siemieniec et al. (hereinafter “Siemieniec” – previously cited reference).
Regarding claim 1, Siemieniec discloses a method, comprising:
providing a masking layer over a silicon carbide (SiC) layer, wherein an opening is formed in the masking layer (hard mask 421 disposed over silicon carbide body 100 and having a hard mask opening 429 formed therein; Fig. 1B; paragraph [0079]);
providing a sidewall spacer along only a sidewall of the opening of the masking layer, a portion of the sidewall spacer not formed in the SiC layer (mask spacers 423 formed along only sidewalls of hard mask opening 429 and not along any other surface of the hard mask 421, where portion of mask spacers 423 are formed outside of SiC body 100; Figs. 1B, 1D; paragraphs [0080], [0086]);
forming an implant region within the SiC layer by directing ions through the opening defined by the sidewall spacer (ion implant regions 761, 762 formed via ion implantation through hard mask opening 429; Fig. 1D; paragraph [0086]);
performing a first etch to the SiC layer, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess (silicon carbide body 100 is etched to form trench 450 having left and right shoulder structures therearound in form of spacer mask 420 as shown in Figs. 1B-1D; paragraphs [0080], [0086]); and
performing a second etch to remove the set of shoulder regions (spacer etch is performed to remove left and right shoulder structures in form of spacer mask 420 as shown in Figs. 1C-1E; paragraphs [0085], [0087]).
Siemieniec fails to disclose an entirety of the sidewall spacer not formed in the SiC layer.
However, Siemieniec already discloses a portion of the mask spacers 423 not being formed in the SiC body 100 and the portion that does not extend outside of the top surface of the SiC body 100 is disposed within a trench formed by removal of a portion of the SiC body 100 which can thereby imply that the space within the trench is not a part of the SiC body 100.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to not have any portion of the mask spacers 423 below the top surface of the SiC body 100 in order to potentially provide preservation of SiC trench sidewalls by reducing interface traps and improving channel mobility/reliability in the inversion layer, minimization of defects due to spacer removal from the sidewall for subsequent gate-oxide formation, and uniform trench geometry for uniform gate-oxide growth and void-free gate electrode fill.
Regarding claim 2, Siemieniec discloses the method of claim 1, further comprising removing the masking layer following the second etch (spacer mask 420 including hard mask 421 removed by spacer etch; Figs. 1C-1E; paragraphs [0085], [0087]).
Regarding claim 3, Siemieniec discloses the method of claim 2, wherein the second etch removes the sidewall spacer (spacer etch removes spacer mask 420 including mask spacers 423; Figs. 1C-1E; paragraphs [0085]-[0087]), and wherein the second etch forms an apex in the central recess of the trench (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]).
Siemieniec fails to disclose wherein the first etch removes the sidewall spacer.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Siemieniec to use the first etch, instead of the second etch, to remove the sidewall spacer, because simply substituting the second etch of Siemieniec to be a first etch of the process would yield the same resulting structure which is a predictable result.
Regarding claim 4, Siemieniec discloses the method of claim 1, wherein the second etch forms an apex in the central recess (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]).
Regarding claim 5, Siemieniec discloses the method of claim 1, wherein the implant region is located in a central area of an etch region of the SiC layer (implant regions 761, 762 located in part in central area of trench 450 within silicon carbide body 100 as shown in Fig. 1D), wherein directing ions through the opening defined by the sidewall spacer causes increased damage to the implant region relative to a remainder of the etch region, and wherein the increased damage increases an etch rate of the implant region of the SiC layer during the first etch (ion implantation directed through mask opening 429 inherently increases damage to lattice structure of implant region 761 which inherently increases etch rate during formation of trench 450 through implant region 761 as shown in Figs. 1A-1B).
Regarding claim 7, Siemieniec discloses the method of claim 1, wherein directing ions through the sidewall spacer comprises delivering at least one of the following ion species into the opening: oxygen, argon, helium, and hydrogen, phosphorus, nitrogen, and aluminum (silicon carbide body 100 may be implanted with ions including oxygen, hydrogen, phosphorous, nitrogen and aluminum; paragraph [0033]).
Regarding claim 8, Siemieniec discloses the method of claim 1, wherein the first etch forms the central recess to a first depth relative to an uppermost surface of the SiC layer, wherein the second etch forms the central recess to a second depth relative to the uppermost surface of the SiC layer, and wherein the second depth is greater than the first depth (first etch forms trench 450 with mask layer 422 at bottom surface 453, and spacer etch forms a new inverted apex shape at bottom surface 453 of trench 450 lower than before as shown in Figs. 1C-1D; paragraph [0085]).
Regarding claim 9, Siemieniec discloses a method of forming a silicon carbide (SiC) metal-oxide-semiconductor field- effect transistor (MOSFET), the method comprising:
providing a masking layer over a SiC layer, wherein an opening is formed in the masking layer, and wherein the opening defines an etch region in the SiC layer (method of producing SiC MOSFET where hard mask 421 disposed over silicon carbide body 100 and having a hard mask opening 429 formed therein for subsequent etching therethrough; Fig. 1B; paragraphs [0079], [0108]);
providing a sidewall spacer along only a sidewall of the opening of the masking layer, a portion of the sidewall spacer not formed in the SiC layer (mask spacers 423 formed along only sidewalls of hard mask opening 429 and not along any other surface of the hard mask 421, where portion of mask spacers 423 are formed outside of SiC body 100; Figs. 1B, 1D; paragraphs [0080], [0086]);
forming an implant region in a central area of the etch region by directing ions into the SiC layer, through the opening defined by the sidewall spacer (ion implant regions 761, 762 disposed in middle of etched area and formed via ion implantation through hard mask opening 429; Fig. 1D; paragraph [0086]);
performing a first etch to the SiC layer, wherein the first etch forms a central recess and a set of shoulder regions adjacent the central recess (silicon carbide body 100 is etched to form trench 450 having left and right shoulder structures therearound in form of spacer mask 420 as shown in Figs. 1B-1D; paragraphs [0080], [0086]); and
performing a second etch to remove the set of shoulder regions (spacer etch is performed to remove left and right shoulder structures in form of spacer mask 420 as shown in Figs. 1C-1E; paragraphs [0085], [0087]).
Siemieniec fails to disclose an entirety of the sidewall spacer not formed in the SiC layer.
However, Siemieniec already discloses a portion of the mask spacers 423 not being formed in the SiC body 100 and the portion that does not extend outside of the top surface of the SiC body 100 is disposed within a trench formed by removal of a portion of the SiC body 100 which can thereby imply that the space within the trench is not a part of the SiC body 100.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to not have any portion of the mask spacers 423 below the top surface of the SiC body 100 in order to potentially provide preservation of SiC trench sidewalls by reducing interface traps and improving channel mobility/reliability in the inversion layer, minimization of defects due to spacer removal from the sidewall for subsequent gate-oxide formation, and uniform trench geometry for uniform gate-oxide growth and void-free gate electrode fill.
Regarding claim 10, Siemieniec discloses the method of claim 9, further comprising removing the masking layer following the second etch (spacer mask 420 including hard mask 421 removed by spacer etch; Figs. 1C-1E; paragraphs [0085], [0087]).
Regarding claim 11, Siemieniec discloses the method of claim 9, wherein the second etch removes the sidewall spacer (spacer etch removes spacer mask 420 including mask spacers 423; Figs. 1C-1E; paragraphs [0085]-[0087]), and wherein the second etch forms an apex in the central recess of the trench (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]).
Siemieniec fails to disclose wherein the first etch removes the sidewall spacer.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Siemieniec to use the first etch, instead of the second etch, to remove the sidewall spacer, because simply substituting the second etch of Siemieniec to be a first etch of the process would yield the same resulting structure which is a predictable result.
Regarding claim 12, Siemieniec discloses the method of claim 9, wherein directing ions through the opening defined by the sidewall spacer causes increased damage to the implant region relative to a remainder of the etch region, and wherein the increased damage increases an etch rate of the implant region of the SiC layer during the first etch (ion implantation directed through mask opening 429 inherently increases damage to lattice structure of implant region 761 which inherently increases etch rate during formation of trench 450 through implant region 761 as shown in Figs. 1A-1B).
Regarding claim 14, Siemieniec discloses the method of claim 9, wherein the first etch forms the central recess to a first depth relative to an uppermost surface of the SiC layer, wherein the second etch forms the central recess to a second depth relative to the uppermost surface of the SiC layer, and wherein the second depth is greater than the first depth (first etch forms trench 450 with mask layer 422 at bottom surface 453, and spacer etch forms a new inverted apex shape at bottom surface 453 of trench 450 lower than before as shown in Figs. 1C-1D; paragraph [0085]).
Regarding claim 15, Siemieniec discloses a method of forming a silicon carbide (SiC) metal-oxide-semiconductor field- effect transistor (MOSFET), the method comprising:
providing a masking layer over a SiC layer, wherein an opening is formed in the masking layer, and wherein the opening defines an etch region in the SiC layer (method of producing SiC MOSFET where hard mask 421 disposed over silicon carbide body 100 and having a hard mask opening 429 formed therein for subsequent etching therethrough; Fig. 1B; paragraphs [0079], [0108]);
providing a sidewall spacer along only a sidewall of the opening of the masking layer, a portion of the sidewall spacer not formed in the SiC layer (mask spacers 423 formed along only sidewalls of hard mask opening 429 and not along any other surface of the hard mask 421, where portion of mask spacers 423 are formed outside of SiC body 100; Figs. 1B, 1D; paragraphs [0080], [0086]);
forming an implant region in a central area of the etch region by directing ions into the SiC layer, through the opening defined by the sidewall spacer (ion implant regions 761, 762 disposed in middle of etched area and formed via ion implantation through hard mask opening 429; Fig. 1D; paragraph [0086]);
performing a first etch to the SiC layer, wherein the first etch forms a trench having a central recess and a set of shoulder regions adjacent the central recess (silicon carbide body 100 is etched to form recessed trench 450 having left and right shoulder structures therearound in form of spacer mask 420 as shown in Figs. 1B-1D; paragraphs [0080], [0086]); and
performing a second etch to the trench to remove the set of shoulder regions (spacer etch is performed to remove left and right shoulder structures in form of spacer mask 420 as shown in Figs. 1C-1E; paragraphs [0085], [0087]).
Siemieniec fails to disclose an entirety of the sidewall spacer not formed in the SiC layer.
However, Siemieniec already discloses a portion of the mask spacers 423 not being formed in the SiC body 100 and the portion that does not extend outside of the top surface of the SiC body 100 is disposed within a trench formed by removal of a portion of the SiC body 100 which can thereby imply that the space within the trench is not a part of the SiC body 100.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to not have any portion of the mask spacers 423 below the top surface of the SiC body 100 in order to potentially provide preservation of SiC trench sidewalls by reducing interface traps and improving channel mobility/reliability in the inversion layer, minimization of defects due to spacer removal from the sidewall for subsequent gate-oxide formation, and uniform trench geometry for uniform gate-oxide growth and void-free gate electrode fill.
Regarding claim 16, Siemieniec discloses the method of claim 15, wherein the second etch removes the sidewall spacer (spacer etch removes spacer mask 420 including mask spacers 423; Figs. 1C-1E; paragraphs [0085]-[0087]), and wherein the second etch forms an apex in the central recess of the trench (spacer etch forms a new inverted apex shape at bottom surface 453 of trench as shown in Figs. 1C-1D; paragraph [0085]).
Siemieniec fails to disclose wherein the first etch removes the sidewall spacer.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Siemieniec to use the first etch, instead of the second etch, to remove the sidewall spacer, because simply substituting the second etch of Siemieniec to be a first etch of the process would yield the same resulting structure which is a predictable result.
Regarding claim 17, Siemieniec discloses the method of claim 15, wherein directing ions through the opening defined by the sidewall spacer causes increased damage to the implant region relative to a remainder of the etch region, and wherein the increased damage increases an etch rate of the implant region of the SiC layer during the first etch (ion implantation directed through mask opening 429 inherently increases damage to lattice structure of implant region 761 which inherently increases etch rate during formation of trench 450 through implant region 761 as shown in Figs. 1A-1B).
Regarding claim 19, Siemieniec discloses the method of claim 15, wherein the first etch forms the central recess to a first depth relative to an uppermost surface of the SiC layer, wherein the second etch forms the central recess to a second depth relative to the uppermost surface of the SiC layer, and wherein the second depth is greater than the first depth (first etch forms trench 450 with mask layer 422 at bottom surface 453, and spacer etch forms a new inverted apex shape at bottom surface 453 of trench 450 lower than before as shown in Figs. 1C-1D; paragraph [0085]).
Claims 6, 13 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec in further view of US 11,302,776 B1 to Sundaresan et al. (hereinafter “Sundaresan” – previously cited reference).
Regarding claims 6, 13 and 18, Siemieniec discloses the method of claims 1, 9 and 15, wherein providing the masking layer comprises depositing a hardmask atop the SiC layer (hard mask 421 disposed over silicon carbide body 100; Fig. 1B; paragraph [0079]), and wherein directing ions into the SiC layer comprises delivering at least one of the following ion species through the opening: oxygen, argon, helium, hydrogen, phosphorus, nitrogen, and aluminum (silicon carbide body 100 may be implanted with ions including oxygen, hydrogen, phosphorous, nitrogen and aluminum; paragraph [0033]).
Siemieniec fails to disclose a silicon dioxide or silicon nitride hardmask.
However, Sundaresan discloses a silicon dioxide or silicon nitride hardmask (hard mask 206 having two silicon oxide layers with a silicon nitride layer therebetween; column 16, lines 55-59).
Siemieniec and Sundaresan are both considered to be analogous to the claimed invention because they are in the same field of semiconductor structure fabrication methods. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec to incorporate the teaching of Sundaresan in order to at least potentially provide high etch selectivity, compatibility with wet etching, and thermal stability.
Response to Arguments
Applicant's arguments filed February 3, 2026 have been fully considered. Applicant presents amendment to claims 1, 9 and 15 with corresponding arguments that these amendments overcome the 35 USC 102 rejection using Siemieniec. Examiner agrees that Siemieniec does not explicitly disclose the amended limitation. However, Siemieniec already discloses a portion of the mask spacers 423 not being formed in the SiC body 100 and so a new ground of rejection that was necessitated by the amendments has been made under 35 USC 103 using Siemieniec as outlined above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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