Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
Claims #1-12, 31-33 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are with respect to claim #1:
No where in the present claim language has the Applicant described nor demonstrated a process that the claimed wafer is undergoing that could/would cause a possible warp/bow to the claimed object.
The Examiner takes the position that it has not be shown/demonstrated how the method regulates or delegates a process that would allow partially preventing a bow in the wafer, as requested in the preset claim #1 language.
The Examiner further takes the position that the present claim language fails to provided much need information about the claimed process that would allow one having ordinary skill in the art before the effective filing date of the claimed invention to reproduce the claimed invention without undue experimentation; information about the bow, effects of the temperature, range of temperature chosen, process delivering the temperature.
Corrections to these concerns is requested.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/25/26 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant argues that, “Sakaue does not disclose or suggest "applying the back side treatment ... to an incoming wafer prior to performing the one or more processes on the front side of the incoming wafer," let alone where the back side treatment "at least partially prevents wafer bow," as recited in Applicant's independent claim 1. Rather, Sakaue describes correcting wafer bow that has already happened due to a previously performed film forming process. Paragraphs [0029] and [0031] of Chang simply do not disclose "using information about how wafer bow changes with temperature to determine properties of a back side treatment." Instead, these paragraphs merely describe controlling temperature during deposition of a compensation layer used to correct warpage that has already occurred during a front side process "Using information about how wafer bow changes with temperature..."
The Examiner has considered the Applicants arguments but respectfully disagrees for the following reasons;
No where in the present claim language has the Applicant described nor demonstrated a process that the claimed wafer is undergoing that could/would cause a possible warp/bow to the claimed object. The Examiner takes the position that there are number of processes that the wafer can be subjected to that could cause a warping action to the object; i.e. transferring, heating/annealing, deposition, ion bombardment, cooling, uneven stacking, mounting, etc.
The Examiner notes that a Chang show multiple possible processes that may cause warpage; as evident from paragraphs 0002, 0017. The Examiner further directs the Applicant to paragraph 0029, where Chang shows that varying various characteristics will control and decrease the stress and therefore reduce the bow. Furthermore, Chang states in paragraph 0033 that, “ stress compensation 350 is deposited at a temperature comparable to those associated with subsequent processing steps, ensuring that the stress accommodation properties of layer 350 are not compromised during the fabrication process; thus, changes, accommodations, to subsequent future processes are done based on learn parameters of previous processes.
The Examiner further takes the position that the present claim language fails to provided much need information about the claimed process that would allow one of ordinary skill in the art to reproduce the claimed invention without undue experimentation; information about the bow, effects of the temperature, range of temperature chosen, process delivering the temperature.
The Examiner further takes the position that the present specification seems to test wafers at various temperature that may occur in various processes. The Examiner takes the position that this is not an inventive step but rather an experiment to see what naturally occurs at various temperatures to a wafer; i.e. what are the repeatable, recordable events with exposing a wafer the various temperatures. The Examiner takes the position that present claim language and specification fails to demonstrate the change in a specific process based on a temperature that is not considered standard for that claimed process; i.e. Bow vs. Temperature: Bow deflection scales linearlyα with ΔT and with the square of the wafer diameter D2, while varying inversely with the square of the substrate thickness t2.Which may incorporate key explanations to changes in the following equations;
Key Variables
R: Radius of curvature of the wafer.
ΔT: Change in temperature (\(T - T_0\)).
αs , αf : Coefficients of thermal expansion (CTE) for the substrate and thin film.
ts, tf: Thickness of the substrate and the film layer.
\(E_s, \hat{E}_f\): Elastic moduli (Young's modulus) of the substrate and film.
\(D\): Diameter of the semiconductor wafer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims #1, 2, 9-13, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" and in further view of Misaka et al., (U.S. Pub. No. 2019/0153602), hereinafter referred to as "Misaka".
Chang shows, with respect to claim #1, method of performing a process on a wafer, comprising: using information about how the determined wafer bow changes with temperature to determine properties of a back side treatment of wafers (paragraph, 0029, 0031), which back side treatment counteracts the wafer bow; (c) applying the back side treatment identified in (b) to an incoming wafer (paragraph, 0027); by applying one or more layers (Adhesion layer) to a back side of the incoming wafer prior to performing the one or more processes on the front side of the incoming wafer (paragraph 0033, 0039-0040) and (d) performing the one or more processes on the front side of the incoming wafer (paragraph, 0023), whereby the back side treatment applied in (c) at least partially prevents the incoming wafer from bowing in response to the one or more processes (paragraph 0026).
Chang substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang fails to show, with respect to claim #1, a method comprising applying the back side treatment identified in (b) to an incoming wafer prior to performing the one or more processes on the front side of the incoming wafer; and (d) performing the one or more processes on the front side of the incoming wafer after applying the back side treatment.
Sakaue teaches, with respect to claim #1, a method comprising applying the back side treatment identified in (b) to an incoming wafer (fig. #2, item W) prior to performing the one or more processes on the front side of the incoming wafer (paragraph 0047); and (d) performing the one or more processes on the front side of the incoming wafer after applying the back side treatment (paragraph 0052, 0057-0058).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #1, to modified the invention of Chang as modified by the invention of Sakaue, which teaches, a method comprising applying the back side treatment identified in (b) to an incoming wafer prior to performing the one or more processes on the front side of the incoming wafer; and (d) performing the one or more processes on the front side of the incoming wafer after applying the back side treatment, to incorporate a structural condition that is achieved before additional structures are deposited, to prevent in interference or damage to upcoming material, as taught by Sakaue.
Chang as modified by Sakaue, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue fails to show, with respect to claim #1, a method wherein the information about how the wafer bow changes with temperature is indicative of wafer bowing caused by one or more processes performed on a front side of a wafer at temperatures the wafer will experience during the one or more processes performed on the front side of the wafer.
Misaka teaches, with respect to claim #1, a wherein the information about how the wafer bow changes with temperature is indicative of wafer bowing caused by one or more processes performed on a front side of a wafer at temperatures the wafer will experience during the one or more processes performed on the front side of the wafer (fig. #8 & 10) (paragraph 0027, 0049-0052).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #1, to modified the invention of Chang as modified by the invention of Sakaue, with the modification of the invention of Misaka, which teaches, a method wherein the information about how the wafer bow changes with temperature is indicative of wafer bowing caused by one or more processes performed on a front side of a wafer at temperatures the wafer will experience during the one or more processes performed on the front side of the wafer, to incorporate a structural condition that is achieved before additional structures are deposited, to prevent in interference or damage to upcoming material or device dysfunctionality, as taught by Misaka.
Chang shows, with respect to claim #2 a method wherein the one or more processes (fig. #3, item 120) performed on the front side of the wafer comprises a deposition process (paragraph 0023).
Chang shows, with respect to claim #9 a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures within a range of temperatures experienced by the incoming wafer during the one or more processes on the front side of the incoming wafer (paragraph 0033, 0039-0040).
Chang shows, with respect to claim #10 a method wherein the back side treatment comprises applying one or more layers (fig. #3, item 350) to the back side of the incoming wafer (paragraph 0027) counteract a stress on the incoming wafer due to the one or more front side processes (paragraph 0002, 0042).
Chang shows, with respect to claim #11 a method wherein using the information about how the determined wafer bow changes with temperature to determine properties of a back side treatment of the wafer comprises obtaining temperature versus bow information for test wafers having one or more deposited layers on the back sides of the test wafers (paragraph 0021, 0027).
Chang shows, with respect to claim #12 a method wherein a first test wafer has a layer of a first material (fig. #3, item 114) on its back side and a second test wafer has a deposited layer of a second material (fig. #3, item 350) on its back side (paragraph 0021, 0025, 0027).
Chang shows, with respect to claim #13 a method wherein using the information about how the determined wafer bow changes with temperature to determine properties of a back side treatment of the wafer further comprises determining a back side treatment that includes: depositing a first layer of the first material (fig. #3, item 114) to a first thickness on the wafer's back side, and depositing a second layer (fig. #3, item 350) of the second material to a second thickness on the wafer's back side (paragraph 0021, 0025, 0027).
Chang shows, with respect to claim #31 a method wherein performing the one or more processes on the front side of the incoming wafer comprises elevating a temperature of the wafer (paragraph 0023, 0029-0030).
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Claim #3, 5, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" and Misaka et al., (U.S. Pub. No. 2019/0153602), hereinafter referred to as "Misaka", as shown in the rejection of claim #1 above and in view of Bellotti et al., (U.S. Pub. No. 2018/0082960), hereinafter referred to as "Bellotti".
Chang as modified by Sakaue and Misaka, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue and Misaka fails to show, with respect to claim #3, a method wherein the one or more processes performed on the front side of the wafer comprises multilayer stack deposition.
Bellotti teaches, with respect to claim #3, a method wherein the one or more processes performed on the front side of the wafer (fig. #10, item 10T) comprises multilayer stack (fig. #10, item 70, 90, 100) deposition (paragraph 0051-0052).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #3, to modified the invention of Chang as modified by Sakaue and Misaka with the modification of Bellotti’s invention, which teaches, a method wherein the one or more processes performed on the front side of the wafer comprises multilayer stack deposition, to incorporate a structural condition to provide an ohmic contact, as taught by Bellotti.
Chang as modified by Sakaue fails to show, with respect to claim #5, a method wherein the one or more processes performed on the front side of the wafer comprises an etching process.
Bellotti teaches, with respect to claim #5, a method wherein the one or more processes performed on the front side of the wafer comprises an etching process (paragraph 0055).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #5, to modified the invention of Chang as modified by Sakaue and Misaka with the modification of Bellotti’s invention, which teaches, a method wherein the one or more processes performed on the front side of the wafer comprises an etching process, to incorporate a structural condition of which patterns are configured, as taught by Bellotti.
Chang as modified by Sakaue and Misaka, fail to show, with respect to claim #33, a method wherein applying the back side treatment comprises depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide and a silicon nitride layer at the back side.
Bellotti teaches, with respect to claim #33, a method wherein applying the back side treatment comprises depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide and a silicon nitride layer at the back side (paragraph 0008).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #33, to modified the invention of Chang as modified by Sakaue and Misaka with the modification of Bellotti’s invention, which teaches, a method wherein applying the back side treatment comprises depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide and a silicon nitride layer at the back side, to incorporate a structural condition to produce stress control on wafers, as taught by Bellotti.
//
Claim #4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" and Misaka et al., (U.S. Pub. No. 2019/0153602), hereinafter referred to as "Misaka", as shown in the rejection of claim #1 above and in further view of Wang et al., (U.S. Pub. No. 2018/0233400), hereinafter referred to as "Wang".
Chang as modified by Sakaue and Misaka, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue and Misaka, fails to show, with respect to claim #4, a method wherein the one or more processes performed on the front side of the wafer comprises oxide/nitride (ONON) deposition.
Wang teaches, with respect to claim #4, a method wherein the one or more processes performed on the front side of the wafer comprises oxide/nitride (ONON) deposition (paragraph 0035).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #4, to modified the invention of Chang as modified Sakaue and Misaka, with the modification of the invention taught by Wang, which teaches, a method wherein the one or more processes performed on the front side of the wafer comprises oxide/nitride (ONON) deposition, to incorporate a structural condition that would provide a protective layer formation that can also provide a stable layer preventing corrosion, as taught by Wang.
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Claim #6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" and Misaka et al., (U.S. Pub. No. 2019/0153602), hereinafter referred to as "Misaka", as shown in the rejection of claim #1 above and in further view of Fukuda et al., (U.S. Pub. No. 2007/0257085), hereinafter referred to as "Fukuda".
Chang as modified by Sakaue and Misaka, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue fails to show, with respect to claim #6, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature.
Misaka teaches, with respect to claim #6, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature (fig. #8 & 10) (paragraph 0027, 0049-0052).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #6, to modified the invention of Chang as modified by the invention of Sakaue, with the modification of the invention of Misaka, which teaches, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature, to incorporate a structural condition that is achieved before additional structures are deposited, to prevent in interference or damage to upcoming material or device dysfunctionality, as taught by Misaka.
Chang as modified by Sakaue and Misaka, fails to show, with respect to claim #6, a method further comprising determining how wafer bow changes with temperature by measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer increases.
Fukuda teaches, with respect to claim #6, a method further comprising determining how wafer bow changes with temperature by measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer increases (paragraph 0077-0078).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #6, to modified the invention of Chang as modified by Sakaue and Misaka, with the invention of Fukuda, which teaches, a method further comprising determining how wafer bow changes with temperature by measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer increases, to incorporate a structural condition wherein the temperature variation of different areas can be observed and mapped, as taught by Fukuda.
Chang as modified by Sakaue fails to show, with respect to claim #7, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature.
Misaka teaches, with respect to claim #7, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature (fig. #8 & 10) (paragraph 0027, 0049-0052).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #7, to modified the invention of Chang as modified by the invention of Sakaue, with the modification of the invention of Misaka, which teaches, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature, to incorporate a structural condition that is achieved before additional structures are deposited, to prevent in interference or damage to upcoming material or device dysfunctionality, as taught by Misaka.
Chang as modified by Sakaue and Misaka, substantially shows the claimed invention as shown in the rejection of claim #7 above.
Chang as modified by Sakaue and Misaka, fail to show, with respect to claim #7, a method further comprising determining how wafer bow changes with temperature by measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer decreases.
Fukuda teaches, with respect to claim #7, a method further comprising determining how wafer bow changes with temperature by measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer decreases (paragraph 0077-0078).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #7, to modified the invention of Chang as modified by Sakaue and Misaka, with the invention of Fukuda, which teaches, a method further comprising determining how wafer bow changes with temperature by measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer decreases, to incorporate a structural condition wherein the temperature variation of different areas can be observed and mapped, as taught by Fukuda.
Chang as modified by Sakaue fails to show, with respect to claim #8, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature.
Misaka teaches, with respect to claim #8, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature (fig. #8 & 10) (paragraph 0027, 0049-0052).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #8, to modified the invention of Chang as modified by the invention of Sakaue, with the modification of the invention of Misaka, which teaches, a method wherein data from the test wafer comprises the information about how the wafer bow changes with temperature, to incorporate a structural condition that is achieved before additional structures are deposited, to prevent in interference or damage to upcoming material or device dysfunctionality, as taught by Misaka.
Chang as modified by Sakaue and Misaka, substantially shows the claimed invention as shown in the rejection of claim #8 above.
Chang as modified by Sakaue and Misaka, fail to show, with respect to claim #8, a method further comprising determining how wafer bow changes with temperature by determining a hysteresis of wafer bow in response to at least one cycle of increasing temperature and decreasing temperature.
Fukuda teaches, with respect to claim #8, a method further comprising determining how wafer bow changes with temperature by determining a hysteresis of wafer bow in response to at least one cycle of increasing temperature and decreasing temperature (paragraph 0077-0078).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #8, to modified the invention of Chang as modified by Sakaue and Misaka, with the invention of Fukuda, which teaches, a method further by determining how wafer bow changes with temperature comprises determining a hysteresis of wafer bow in response to at least one cycle of increasing temperature and decreasing temperature, to incorporate a structural condition wherein the temperature variation of different areas can be observed and mapped, as taught by Fukuda.
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Claim #32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" and Misaka et al., (U.S. Pub. No. 2019/0153602), hereinafter referred to as "Misaka", as shown in the rejection of claim #1 above and in further view of KIM et al., (U.S. Pub. No. 2021/0214501), hereinafter referred to as "Kim".
Chang as modified by Sakaue and Misaka substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue and Misaka, fail to show, with respect to claim #32, a method, a method wherein applying the back side treatment results in a wafer bow of an amount below 100 pm when the wafer has a diameter of about 300 mm.
Kim teaches, with respect to claim #32, a method wherein applying the back side treatment results in a wafer bow of an amount below 100 pm when the wafer has a diameter of about 300 mm (paragraph 0105, 0107-0108).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention, with respect to claim #32, to modified the invention of Chang as modified by Sakaue and Misaka, with the modification the invention of Kim, which teaches, a method wherein applying the back side treatment results in a wafer bow of an amount below 100 pm when the wafer has a diameter of about 300 mm, to incorporate a structural condition to provide large area deposition sites for electrical components, as taught by Kim.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
08/12/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights