Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission of an RCE filed on 03/10/26 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/10/26 was filed in a timely manner; thus, the submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claim(s) #1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims #1, 2, 9-13, 31 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" and in view of SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue".
Chang shows, with respect to claim #1, method of performing a process on a wafer, comprising:(a) determining how wafer bow changes with temperature (paragraph 0033, 0039-0040), wherein the wafer bow is at least partially caused by one or more processes performed on a front side of a wafer (paragraph 0002); (b) using information about how the determined wafer bow changes with temperature to determine properties of a back side treatment of wafers (paragraph, 0029, 0031), which back side treatment counteracts the wafer bow; (c) applying the back side treatment identified in (b) to an incoming wafer (paragraph, 0027); by applying one or more layers (Adhesion layer) to a back side of the incoming wafer prior to performing the one or more processes on the front side of the incoming wafer (paragraph 0040) and (d) performing the one or more processes on the front side of the incoming wafer (paragraph, 0023), whereby the back side treatment applied in (c) at least partially prevents the incoming wafer from bowing in response to the one or more processes (paragraph 0026).
Chang substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang fails to show, with respect to claim #1, a method comprising applying the back side treatment identified in (b) to an incoming wafer prior to performing the one or more processes on the front side of the incoming wafer; and (d) performing the one or more processes on the front side of the incoming wafer after applying the back side treatment.
Sakaue teaches, with respect to claim #1, a method comprising applying the back side treatment identified in (b) to an incoming wafer (fig. #2, item W) prior to performing the one or more processes on the front side of the incoming wafer (paragraph 0047); and (d) performing the one or more processes on the front side of the incoming wafer after applying the back side treatment (paragraph 0052, 0057-0058).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #1, to modified the invention of Chang as modified by the invention of Sakaue, which teaches, a method comprising applying the back side treatment identified in (b) to an incoming wafer prior to performing the one or more processes on the front side of the incoming wafer; and (d) performing the one or more processes on the front side of the incoming wafer after applying the back side treatment, to incorporate a structural condition that is achieved before additional structures are deposited, to prevent in interference or damage to upcoming material, as taught by Sakaue.
Chang shows, with respect to claim #2 a method wherein the one or more processes (fig. #3, item 120) performed on the front side of the wafer comprises a deposition process (paragraph 0023).
Chang shows, with respect to claim #9 a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures within a range of temperatures experienced by the incoming wafer during the one or more processes on the front side of the incoming wafer (paragraph 0033, 0039-0040).
Chang shows, with respect to claim #10 a method wherein the back side treatment comprises applying one or more layers (fig. #3, item 350) to the back side of the incoming wafer (paragraph 0027) counteract a stress on the incoming wafer due to the one or more front side processes (paragraph 0002, 0042).
Chang shows, with respect to claim #11 a method wherein using the information about how the determined wafer bow changes with temperature to determine properties of a back side treatment of the wafer comprises obtaining temperature versus bow information for test wafers having one or more deposited layers on the back sides of the test wafers (paragraph 0021, 0027).
Chang shows, with respect to claim #12 a method wherein a first test wafer has a layer of a first material (fig. #3, item 114) on its back side and a second test wafer has a deposited layer of a second material (fig. #3, item 350) on its back side (paragraph 0021, 0025, 0027).
Chang shows, with respect to claim #13 a method wherein using the information about how the determined wafer bow changes with temperature to determine properties of a back side treatment of the wafer further comprises determining a back side treatment that includes: depositing a first layer of the first material (fig. #3, item 114) to a first thickness on the wafer's back side, and depositing a second layer (fig. #3, item 350) of the second material to a second thickness on the wafer's back side (paragraph 0021, 0025, 0027).
Chang shows, with respect to claim #31 a method wherein performing the one or more processes on the front side of the incoming wafer comprises elevating a temperature of the wafer (paragraph 0023, 0029-0030).
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Claim #3, 5, 33 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" as shown in the rejection of claim #1 above and in view of Bellotti et al., (U.S. Pub. No. 2018/0082960), hereinafter referred to as "Bellotti".
Chang as modified by Sakaue substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue fails to show, with respect to claim #3, a method wherein the one or more processes performed on the front side of the wafer comprises multilayer stack deposition.
Bellotti teaches, with respect to claim #3, a method wherein the one or more processes performed on the front side of the wafer (fig. #10, item 10T) comprises multilayer stack (fig. #10, item 70, 90, 100) deposition (paragraph 0051-0052).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #3, to modified the invention of Chang as modified by Sakaue with the modification of Bellotti’s invention, which teaches, a method wherein the one or more processes performed on the front side of the wafer comprises multilayer stack deposition, to incorporate a structural condition to provide an ohmic contact, as taught by Bellotti.
Chang as modified by Sakaue fails to show, with respect to claim #5, a method wherein the one or more processes performed on the front side of the wafer comprises an etching process.
Bellotti teaches, with respect to claim #5, a method wherein the one or more processes performed on the front side of the wafer comprises an etching process (paragraph 0055).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #5, to modified the invention of Chang as modified by Sakaue with the modification of Bellotti’s invention, which teaches, a method wherein the one or more processes performed on the front side of the wafer comprises an etching process, to incorporate a structural condition of which patterns are configured, as taught by Bellotti.
Chang as modified by Sakaue fails to show, with respect to claim #33, a method wherein applying the back side treatment comprises depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide and a silicon nitride layer at the back side.
Bellotti teaches, with respect to claim #33, a method wherein applying the back side treatment comprises depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide and a silicon nitride layer at the back side (paragraph 0008).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #33, to modified the invention of Chang as modified by Sakaue with the modification of Bellotti’s invention, which teaches, a method wherein applying the back side treatment comprises depositing a silicon oxide layer, a silicon nitride layer, or both a silicon oxide and a silicon nitride layer at the back side, to incorporate a structural condition to produce stress control on wafers, as taught by Bellotti.
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Claim #4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue", as shown in the rejection of claim #1 above and in view of Wang et al., (U.S. Pub. No. 2018/0233400), hereinafter referred to as "Wang".
Chang as modified by Sakaue, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue, fails to show, with respect to claim #4, a method wherein the one or more processes performed on the front side of the wafer comprises oxide/nitride (ONON) deposition.
Wang teaches, with respect to claim #4, a method wherein the one or more processes performed on the front side of the wafer comprises oxide/nitride (ONON) deposition (paragraph 0035).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #4, to modified the invention of Chang as modified Sakaue, with the modification of the invention taught by Wang, which teaches, a method wherein the one or more processes performed on the front side of the wafer comprises oxide/nitride (ONON) deposition, to incorporate a structural condition that would provide a protective layer formation that can also provide a stable layer preventing corrosion, as taught by Wang.
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Claim #6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue", as shown in the rejection of claim #1 above and in view of Fukuda et al., (U.S. Pub. No. 2007/0257085), hereinafter referred to as "Fukuda".
Chang as modified by Sakaue, substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue, fails to show, with respect to claim #6, a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer increases.
Fukuda teaches, with respect to claim #6, a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer increases (paragraph 0077-0078).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #6, to modified the invention of Chang as modified by Sakaue, with the invention of Fukuda, which teaches, a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer increases, to incorporate a structural condition wherein the temperature variation of different areas can be observed and mapped, as taught by Fukuda.
Chang as modified by Sakaue, fails to show, with respect to claim #7, a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer decreases.
Fukuda teaches, with respect to claim #7, a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer decreases (paragraph 0077-0078).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #7, to modified the invention of Chang as modified by Sakaue, with the invention of Fukuda, which teaches, a method wherein determining how wafer bow changes with temperature comprises measuring wafer bow of a test wafer at multiple different temperatures while the temperature of the test wafer decreases, to incorporate a structural condition wherein the temperature variation of different areas can be observed and mapped, as taught by Fukuda.
Chang as modified by Sakaue, fails to show, with respect to claim #8, a method wherein determining how wafer bow changes with temperature comprises determining a hysteresis of wafer bow in response to at least one cycle of increasing temperature and decreasing temperature.
Fukuda teaches, with respect to claim #8, a method wherein determining how wafer bow changes with temperature comprises determining a hysteresis of wafer bow in response to at least one cycle of increasing temperature and decreasing temperature (paragraph 0077-0078).
It would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #8, to modified the invention of Chang as modified by Sakaue, with the invention of Fukuda, which teaches, a method wherein determining how wafer bow changes with temperature comprises determining a hysteresis of wafer bow in response to at least one cycle of increasing temperature and decreasing temperature, to incorporate a structural condition wherein the temperature variation of different areas can be observed and mapped, as taught by Fukuda.
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Claim #32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al., (U.S. Pub. No, 2017/0162522), hereinafter referred to as "Chang" as modified by SAKAUE et al., (U.S. Pub. No. 2017/0117169), hereinafter referred to as "Sakaue" as shown in the rejection of claim #1 above and in view of KIM et al., (U.S. Pub. No. 2021/0214501), hereinafter referred to as "Kim".
Chang as modified by Sakaue substantially shows the claimed invention as shown in the rejection of claim #1 above.
Chang as modified by Sakaue fails to show, with respect to claim #32, a method, a method wherein applying the back side treatment results in a wafer bow of an amount below 100 pm when the wafer has a diameter of about 300 mm.
Kim teaches, with respect to claim #32, a method wherein applying the back side treatment results in a wafer bow of an amount below 100 pm when the wafer has a diameter of about 300 mm (paragraph 0105, 0107-0108).
With respect to claim #32, the term "about" is a relative term which renders the claim indefinite; it is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. “About” is defined as " almost or nearly used to indicate that a number, amount, time, etc., is not exact or certain” (see Merriam Webster online dictionary). This language is indefinite as the specification does not describe how much the value can deviate from the amounts labeled with the term “about”. The term “about” modifies a target, and implicitly requires boundaries at some maximum value above the target and at some minimum value below the target beyond which one is not “about” the target any more. Neither the claims, nor the specification, defines these boundaries. Thus, it is unclear whether one must be within some small percentage of deviation of the target (such as 0.01 %, 0.1 %, 1 %, 2 %, 5 %, 10 %, or some other percentage) or within a certain number of units of the target and specifically which of these possible values defines the boundaries. If one were to poll 100 people having ordinary skill in the art, there would be many different responses for the boundaries. Thus, determining whether one is infringing the limitation is subjective, rather than objective, and thus the claim is unclear. Therefore, the claim is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Furthermore, the Examiner takes the position that the applicant has not established the critical nature wherein the wafer has a diameter of about 300 mm to the method of reducing the bow in the wafer surface. “The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range.” In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir.1990). To establish unexpected results over a claimed range, applicants should compare a sufficient number of tests inside and outside the claimed range to show criticality of the claimed range. In re Hill, 284 F.2d 955, 128 USPQ 197(CCPA 1960). The Examiner notes that Kim does not state explicitly that the final choice of flatness is 100 pm or less. However, the Examiner takes the position that Kim shows a method of arriving at a choice of flatness (warpage removal) that uses the same process as the claimed inventive steps of the present application. Furthermore, the Examiner takes the position that Kim shows an equation that can be used to vary procedure processes to increase the amount of warpage removal at the discretion of the user. Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was made to have various ranges. Also, it would have been obvious to one having ordinary skill in the art at the time the invention was made, with respect to claim #32, to modified the invention of Chang as modified by Sakaue, with the modification the invention of Kim, which teaches, a method wherein applying the back side treatment results in a wafer bow of an amount below 100 pm when the wafer has a diameter of about 300 mm, to incorporate a structural condition to provide large area deposition sites for electrical components, as taught by Kim.
EXAMINATION NOTE
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andre’ Stevenson whose telephone number is (571) 272 1683 (Email Address, Andre.Stevenson@USPTO.GOV). The examiner can normally be reached on Monday through Friday from 7:30 am to 4:30 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on 571-272 2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Andre’ Stevenson Sr./
Art Unit 2899
03/27/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899