Prosecution Insights
Last updated: April 19, 2026
Application No. 17/919,730

ORGANIC SPACER FOR INTEGRATED CIRCUITS

Non-Final OA §102
Filed
Oct 18, 2022
Examiner
CHEN, JACK S J
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Ndtm US LLC
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
82%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
432 granted / 565 resolved
+8.5% vs TC avg
Moderate +6% lift
Without
With
+5.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
33 currently pending
Career history
598
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
30.0%
-10.0% vs TC avg
§102
34.2%
-5.8% vs TC avg
§112
26.3%
-13.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 565 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species I, with claims 21-29 indicated by Applicant to read thereon, in the reply filed on 9/5/2025 is acknowledged. Claims 30-40 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/5/2025. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 21-29 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Swee Seng, US Pub. No. 2006/0022323 A1. Re claim 21. Swee Seng discloses an apparatus comprising: a silicon substrate 120 (e.g., fig. 3A, paragraph 61) or semiconductor substrate 130, 230A (e.g., figs. 3D-5, paragraphs 45, 65, 82); a silicon die 130, 130A, 130B, 230B (e.g., figs. 3D-5 and paragraphs 45, 76, 82); and a spacer 126, 150, 250 (e.g., figs. 3D-5 and paragraphs 47, 62, 64, 76, 83) disposed between the silicon die 130, 130A, 130B, 230B and the semiconductor substrate 120, 130, 230A, wherein the spacer comprises an organic compound (e.g., polyimide, resin, epoxy, paragraphs 47, 62, 64, 76, 83; which is the same material as instant claim 22), and wherein the spacer is provided to reduce a coefficient of thermal expansion (CTE) mismatch between the semiconductor substrate and silicon die due the it’s intrinsic properties of the material (e.g., organic compound such as polyimide, resin, epoxy), see figs. 1-8B and cols. 1-12 for more details. Furthermore, it should be noted that a recitation of the intended use and/or function of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use and/or function, then it meets the claim Re claim 22. The apparatus of claim 21, wherein the organic compound comprises an epoxy mold compound (EMC) or an organic solder mask material (e.g., polyimide, resin, epoxy, paragraphs 47, 62, 64, 76, 83). Re claim 23. The apparatus of claim 21, wherein the silicon die 130A includes a film layer (e.g.. a bottom portion of 130A (fig. 3B) or the dielectric and/or adhesive layer (figs. 3F, 4 and 5)), and wherein the film layer is in contact with the spacer 126 (fig. 3B). Re claim 24. The apparatus of claim 21, wherein the silicon die 130B, 230B (figs. 3D-F, 5, 130 in Fig. 4) is a first silicon die 130B, 230B (figs. 3D-F, 5, upper die 130 in Fig. 4), and the apparatus further comprises a second silicon die 130A, 230A (figs. 3D-F, 5; lower die 130 in Fig. 4) in contact with the semiconductor substrate (e.g., the portion(s) under the second die). Re claim 25. The apparatus of claim 24, wherein the second silicon die 130A, 230A (figs. 3D-F, 5; lower die 130 in Fig. 4) is free from contact with the first silicon die 130B, 230B (figs. 3D-F, 5, upper die 130 in Fig. 4) or the EMC spacer. Re claim 26. The apparatus of claim 24, wherein the apparatus further comprises a third silicon die (middle die 130 in fig. 4) disposed between first silicon die (upper die 130 in fig. 4) and the second silicon die (lower die 130 in fig. 4). Re claim 27. The apparatus of claim 24, wherein each respective silicon die includes a respective film layer (e.g., a lower portion of the of each die 130 or adhesive/insulating/passivation layer in fig. 4). Re claim 28. The apparatus of claim 21, wherein the silicon die is a first silicon die (middle die 130 in fig. 4), wherein a first side of the first silicon die is in contact with the spacer (lower spacer, i.e., spacer between lower and middle die 130 in fig. 4), and wherein a second side of the first silicon die is in contact with a second silicon die (upper die 130 in fig. 4). Re claim 29. The apparatus of claim 28, wherein the first silicon die (middle die 130 in fig. 4) includes a first film layer (fig. 4, e.g., layer between middle die 130 and lower spacer) on its first side contacting the spacer (fig. 4, e.g., lower spacer), and wherein the second silicon die (upper die 130 in fig. 4) includes a second film layer (fig. 4, e.g., layer between upper die 130 and upper spacer) in contact with second side of the first silicon die (middle die 130 in fig. 4). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACK S CHEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Oct 18, 2022
Application Filed
Aug 19, 2025
Response after Non-Final Action
Feb 09, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598861
DISPLAY PANELS
2y 5m to grant Granted Apr 07, 2026
Patent 12593721
INTERNAL THERMAL TRANSFER FOR MEMORY DEVICE
2y 5m to grant Granted Mar 31, 2026
Patent 12593666
METHODS, SYSTEMS, AND APPARATUS FOR CONDUCTING A RADICAL TREATMENT OPERATION PRIOR TO CONDUCTING AN ANNEALING OPERATION
2y 5m to grant Granted Mar 31, 2026
Patent 12588265
SEMICONDUCTOR STRUCTURE WITH ENHANCED PLACEHOLDER POSITION MARGIN
2y 5m to grant Granted Mar 24, 2026
Patent 12575379
MEASUREMENT OF LATERAL DOPANT CONCENTRATION AND DISTRIBUTION IN HIGH ASPECT RATIO TRENCH STRUCTURES
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
82%
With Interview (+5.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 565 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month