DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 01/08/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 01/08/2026 in reply to the non-final rejection mailed on 09/08/2025, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 11-20, & 26 are cancelled, and Claim 31 is added. Accordingly, pending in this Office action are claims 1-10, 20-25, & 27-31.
Claim Rejections - 35 USC § 102 & 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, & 31 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Yu (US 20150364386).
Regarding Claim 1, Yang (see, e.g., figs. 9a-9t, annotated figure 1) shows a method comprising:
forming a first package component comprising:
forming a first dielectric layer 32 (see, e.g., fig. 9h, para.0085) comprising a first top surface;
forming a first conductive feature (see, e.g., figs. 9k-n), wherein the first conductive feature comprises:
a via 36 (lower portion, see, e.g., annotated figure 1) extending into the first dielectric layer;
and a metal bump 36 (upper portion, see, e.g., annotated figure 1) comprising a second top surface higher than the first top surface of the first dielectric layer,
wherein the via and the metal bump are formed in a same plating process (see, e.g., para.0088);
dispensing a photo-sensitive layer 40 (see, e.g., fig. 9o, para.0092),
wherein the photo-sensitive layer covers the metal bump (fig. 9o);
and performing a process to form a recess 40a (see, e.g., fig. 9p, para.0093) in the photo-sensitive layer,
wherein the metal bump is exposed to the recess (see, e.g., fig. 9p),
and wherein the photo-sensitive layer comprises a third top surface higher than the metal bump;
and bonding a second package component 46 (see, e.g., fig. 9t, para.0097) to the first package component,
wherein a solder region 54 (see, e.g., para.0098) extends into the recess to bond the metal bump to a second conductive feature 50 (see, e.g., para.0098) in the second package component 46.
Yang (see, e.g., para.0088-0090) teaches a photolithography process to form the metal bump 36. Yang (see, e.g., para.0093) states the forming of the recess 40a can use a suitable process and does not limit the forming to etching.
Yang, however, fails to show,
performing a photolithography process to form the recess in the photo-sensitive layer
Although Yang does not explicitly state a photolithography process forms the recess, Yu (see, e.g., fig. 2, para.0030) teaches a photolithography process (light exposure) forming a recess in a photo-sensitive layer 203 would be an obvious and suitable process for forming a recess in a photo-sensitive layer.
Therefore, it would be obvious to one of ordinary skill in the art to photolithography process of Yu as the process to form the recess in the photo-sensitive layer of Yang.
Regarding Claim 2, Yang, in view of Yu (see, e.g., fig. 2, para.0030), shows the method of claim 1,
wherein the performing the photolithography process comprises:
performing a light-exposure process on the photo-sensitive layer 40 (203);
and developing the photo-sensitive layer to remove a portion of the photo-sensitive layer covering the metal bump 36 (113).
Yu (see, e.g., fig. 2, para.0030) states the limitations for performing the photolithography process comprising light-exposure on photo-sensitive layer 203 & removing a portion covering the metal bump 113. The process of Yu is applied to the photo-sensitive layer 40 and metal bump 36 of Yang.
Regarding Claim 5, Yang (see, e.g., para.0078, para.0085), in view of Yu shows the method of claim 1,
wherein the first dielectric layer 24 & 32 comprises an additional photo-sensitive layer 24 (see, e.g., para.0078)
Regarding Claim 31, Yang (see, e.g., figs. 9l-o, para.0089-0090), in view of Yu, shows the method of claim 1,
wherein the via and the metal bump are formed using a same plating mask 38 (see, e.g., figs. 9l-m, para.0089);
and wherein the method further comprises:
removing the plating mask to reveal a top surface of the first dielectric layer (in openings 38a, see, e.g., figs. 9m-n, para.0090),
wherein the photo-sensitive layer is formed after the plating mask is removed (see, e.g., fig. 9o),
and the photo-sensitive layer physically contacts the top surface of the first dielectric layer (see, e.g., fig. 9o)
Regarding the limitation, “removing the plating mask to reveal a top surface of the first dielectric layer,” Yang, in view of Yu, states openings 38a are formed as part of the plating mask 38 is removed and then layers 34 & 36 are removed, revealing a top surface of the first dielectric layer. Therefore, removing the plating mask contributes to revealing the top surface of the first dielectric layer and renders the limitation obvious.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Yu (US 20150364386) and further in view of Williamson (US 20200251436) & Chu (US 20190385951).
Regarding Claim 3, Yang, in view of Yu, shows the method of claim 1,
Yang, in view of Yu, however, fails to show
wherein the recess extends laterally beyond edges of the metal bump,
Williamson (see, e.g., fig. 5b, para.0040), in a similar method to Yang, in view of Yu, teaches a configuration, wherein a recess 517 extending laterally beyond the edges of a metal bump 504 would form reliable solder joints that prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the method of Yang, in view of Yu, to form reliable solder joints that prevent solder wicking and bridging.
Yang, in view of Yu and further in view of Williamson, however, fails to show
and wherein a portion of the photo-sensitive layer is directly underlying the recess.
Chu (see, e.g., fig. 1t, para.0071), in a similar method to Yang, in view of Yu and further in view of Williamson, teaches a configuration, wherein a portion of the photo-sensitive layer 534 is directly underlying the recess OP4 due to the angle of the recess. The configuration would be a suitable and obvious shape for forming the recess of the photo-sensitive layer.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Chu in the method of Yang, in view of Yu and further in view of Williamson, as an obvious shape for forming the recess of the photo-sensitive layer.
Claims 4, 6, & 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Yu (US 20150364386) and further in view of Williamson (US 20200251436).
Regarding Claim 4, Yang, in view of Yu, shows the method of claim 1,
Yang, in view of Yu, however, fails to show
wherein a sidewall of the metal bump is exposed to the recess,
and wherein the solder region extends to a level lower than the second top surface of the metal bump to contact the sidewall of the metal bump.
Williamson (see, e.g., fig. 5b, para.0040), in a similar method to Yang, in view of Yu, teaches a configuration, wherein a sidewall of the metal bump 504 is exposed to the recess 517 and wherein the solder region extends to a lower level than the second top surface of the metal bump to contact the sidewall of the metal bump, would form reliable solder joints that prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the method of Yang, in view of Yu, to form reliable solder joints that prevent solder wicking and bridging.
Regarding Claim 6, Yang (see, e.g., figs. 9o-p, para.0092-0093), in view of Yu, shows the method of claim 5,
and wherein in the photolithography process, the first dielectric layer is not patterned.
Yang (see, e.g., figs. 9o-p, para.0092-0093), in view of Yu, shows the photolithography process used to form the recess is applied only to the photo-sensitive layer 40 and not to the first dielectric layer 32.
Yang, in view of Yu, however, fails to show
wherein the recess extends to the first top surface of the first dielectric layer,
Williamson (see, e.g., fig. 5b, para.0019, para.0040), in a similar method to Yang, in view of Yu, teaches a configuration, wherein the recess 517 extends to the first top surface of the substrate 502. 502 is a package substrate made of a dielectric material. The configuration would form reliable solder joints that prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson, to extend the recess to the first top surface of the first dielectric layer of the method of Yang, in view of Yu, to form reliable solder joints that prevent solder wicking and bridging.
Regarding Claim 7, Yang (see, e.g., para.0085, para.0092), in view of Yu and further in view of Williamson, shows the method of claim 6,
wherein the first dielectric layer 32 and the photo-sensitive layer 40 are formed of a same photo-sensitive material.
Yang (see, e.g., para.0085, para.0092) states 32 and 40 can be made of the same materials.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Yu (US 20150364386) and further in view of Kim (US 20190198354).
Regarding Claim 8, Yang, in view of Yu, shows the method of claim 1
Yang, in view of Yu, however, fails to show
further comprising, after the photo-sensitive layer is dispensed and before the photolithography process is performed, performing a planarization process on the photo-sensitive layer.
Kim (see, e.g., figs. 2b-d, para.0040-0042, para.0052), in a similar method to Yang, in view of Yu, teaches a step wherein after dispensing photo-sensitive layer 124 and before a subsequent photolithography process, performing a planarization process would be an obvious step and provide a uniform and level surface prior to forming a recess.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the step of Kim in the method of Yang, in view of Yu, as an obvious step and to provide a uniform and level surface prior to forming a recess.
Claims 1, 9, & 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen (US 20170005052).
Regarding Claim 1, Chen (see, e.g., figs. 2-9, annotated figure 2) shows a method comprising:
forming a first package component 100 comprising:
forming a first dielectric layer 108 comprising a first top surface;
forming a first conductive feature, wherein the first conductive feature comprises:
a via 128 (lower portion, see, e.g., annotated figure 2) extending into the first dielectric layer;
and a metal bump 128 (upper portion, see, e.g., annotated figure 2) comprising a second top surface higher than the first top surface of the first dielectric layer
wherein the via and the metal bump are formed in a same plating process (see, e.g., fig. 5);
dispensing a photo-sensitive layer 126 (fig. 8),
wherein the photo-sensitive layer covers the metal bump;
and performing a photolithography process to form a recess in the photo-sensitive layer (see, e.g., fig. 8, para.0032),
wherein the metal bump is exposed to the recess,
and wherein the photo-sensitive layer comprises a third top surface higher than the metal bump;
and bonding a second package component to the first package component (see, e.g., para.0022),
wherein a solder region 132 extends into the recess to bond the metal bump to a second conductive feature in the second package component (see, e.g., para.0023).
Regarding Claim 9, Chen (see, e.g., fig. 8, annotated figure 2, para.0032) shows the method of claim 1,
wherein at a time the photolithography process is started, the third top surface of the photo-sensitive layer comprises: a lower portion laterally offset from the metal bump 128 (upper portion, see, e.g., annotated figure 2);
and a higher portion directly over the metal bump (over 128’’, see, e.g., annotated figure 2),
wherein the higher portion is higher than the lower portion.
Regarding Claim 10, Chen (see, e.g., fig. 9, annotated figure 2) shows the method of claim 9,
wherein after the photolithography process is finished, the third top surface of the photo-sensitive layer comprises a raised portion (formed from higher portion, see, e.g., annotated figure 2) surrounding the recess,
and wherein the raised portion is a part of the higher portion.
Claims 21-25 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20210335714) in view of Yu (US 20150364386) and further in view of Williamson (US 20200251436).
Regarding Claim 21, Yang (see, e.g., figs. 9a-9t, annotated figure 1) shows a method comprising:
forming a first package component comprising:
forming a conductive feature (see, e.g., figs. 9k-n) comprising:
forming a via 36 (lower portion, see, e.g., annotated figure 1) embedded in a dielectric layer 32 (see, e.g., fig. 9h, para.0085);
and forming a metal bump 36 (upper portion, see, e.g., annotated figure 1) protruding higher than a first top surface of the dielectric layer
wherein the via and the metal bump are formed in a same plating process (see, e.g., para.0088);
and a photo-sensitive structure 40 (see, e.g., fig. 9o, para.0092) extending from a lower level to a higher level,
wherein the lower level is lower than a second top surface of the metal bump,
and the higher level is higher than the second top surface of the metal bump;
and plating a solder region 54 (see, e.g., para.0098),
wherein the photo-sensitive structure is joined to the metal bump,
Yang (see, e.g., para.0088-0090) teaches a photolithography process to form the metal bump 36. Yang (see, e.g., para.0093) states the forming of the recess 40a can use a suitable process and does not limit the forming to etching.
Yang, however, fails to show,
performing a coating and light-exposure process to form the photo-sensitive structure
Although Yang does not explicitly state a photolithography process forms the recess, Yu (see, e.g., fig. 2, para.0026, para.0030) teaches a photolithography process (light exposure & coating) forming the photo-sensitive structure 203 would be an obvious and suitable process for forming the photo-sensitive structure.
Therefore, it would be obvious to one of ordinary skill in the art to photolithography process of Yu as the process to form the photo-sensitive structure of Yang.
Yang, in view of Yu, however, fails to show
wherein the solder region extends laterally beyond edges of the metal bump.
Williamson (see, e.g., fig. 5b, para.0040), in a similar method to Yang, in view of Yu, teaches a configuration, wherein the solder region 511 extends laterally beyond the edges of the metal bump 504b would form reliable solder joints that prevent solder wicking and bridging.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Williamson in the method of Yang, in view of Yu, to form reliable solder joints that prevent solder wicking and bridging.
Regarding Claim 22, Yang (see, e.g., para.0092), in view of Yu and further in view of Williamson, shows the method of claim 21,
wherein the photo-sensitive structure 40 comprises a photo-sensitive material selected from the group consisting of polyimide, polybenzoxazole (PBO), and benzocyclobutene (BCB) (see, e.g., para.0092).
Regarding Claim 23, Yang (see, e.g., para.0085, para.0092), in view of Yu and further in view of Williamson, shows the method of claim 22,
wherein both of the dielectric layer 32 and the photo-sensitive structure 40 comprise photo-sensitive materials (polyimide, see, e.g., para.0085, para.0092).
Regarding Claim 24, Yang (see, e.g., fig. 9o, para.0085, para.0092), in view of Yu and further in view of Williamson, shows the method of claim 23,
wherein the dielectric layer 32 and the photo-sensitive structure 40 are formed of a same photo-sensitive material (see, e.g., para.0085, para.0092),
and are in contact with each other to form a distinguishable interface in between (see, e.g., fig. 9o).
Regarding Claim 25, Yang, in view of Yu and further in view of Williamson (see, e.g., fig. 5b, para.0040) shows the method of claim 21,
wherein the solder region contacts a sidewall of the photo-sensitive structure (see, e.g., fig. 5b, para.0040).
Claims 27-30 are rejected under 35 U.S.C. 103 as being unpatentable over Su (US 20170133351) in view of Liao (US 20190096851) and further view of Yang (US 20150364386).
Regarding Claim 27, Su (see, e.g., fig. 8, annotated figure 3) shows a method comprising:
forming a device die comprising:
forming a first structure 66 (see, e.g., fig. 7, para.0029);
forming a first metal bump and a second metal bump 70 (upper portion, see annotated figure 3) neighboring each other and extending higher than the first structure;
and forming a second photo-sensitive structure 68 (see, e.g., para.0030) over and directly and physically contacting the first structure 66;
plating a first solder region and a second solder region 72/74 (see annotated figure 3) extending into the second photo-sensitive structure (see, e.g., para.0031),
wherein a portion of the second photo-sensitive structure 68 separates the first solder region from the second solder region (between first and second solder regions, see e.g., annotated figure 3),
and wherein the first metal bump and the second metal bump 70 (upper portions) are underlying a first upper portion of the first solder region and a second upper portion of the second solder region, respectively (see, e.g., annotated figure 3);
Su (see, e.g., para.0029) states the first structure is an encapsulant.
Su, however, fails to show
a first photo-sensitive structure.
Liao (see, e.g., fig. 1a, para.0015), in a similar method to Su, teaches that an encapsulant 19 can be a photo-sensitive structure, such as polyimide, and would be a suitable and obvious structure for an encapsulant.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the photo-sensitive structure of Liao as a suitable and obvious structure for the first structure 66 encapsulant in the method of Su.
Su, in view of Liao, however, fails to show
and joining a second package component to the device die comprising:
bonding a first conductive feature 78 ( see, e.g., para.0032) to the first metal bump through the first solder region;
and bonding a second conductive feature 78 (see, e.g., para.0032) to the second metal bump through the second solder region.
Yang (see, e.g., fig. 9t, para.0097-0098) in a similar method to Su, in view of Liao, teaches a configuration wherein joining the device die to a package component 46 wherein first and second conductive features 48 are bonding to the first metal bump 36 through the first and second solder regions 54 would be an obvious use for the device die of Su, in view of Liao.
It would have been obvious at the time of filing the invention to one of ordinary skill in the art to use the configuration of Yang as an obvious use structure in method of Su, in view of Liao, as an obvious use for the device die.
Regarding Claim 28, Su (see, e.g., fig. 8, annotated figure 3), in view of Liao and further in view of Yang, shows the method of claim 27,
wherein the first solder region is wider than the first metal bump.
Regarding Claim 29, Su (see, e.g., fig. 8, annotated figure 3), in view of Liao and further in view of Yang, shows the method of claim 27,
wherein after the joining, the second photo-sensitive structure comprises a lower portion directly underlying the first upper portion of the first solder region,
and wherein the lower portion has a top surface level with the first metal bump.
Regarding Claim 30, Su, in view of Liao (see, e.g., para.0015, para.0017), in view of Liao and further in view of Yang, shows the method of claim 27,
wherein the first photo-sensitive structure 66 (19) and the second photo-sensitive structure 68 (20) are formed of a same formation process
Liao (see, e.g., para.0015, para.0017) states first photo-sensitive structure 19 and the second photo-sensitive structure 20 can both be formed of a spin-coating or lamination process. The claim language “formed of a same formation process” does not require simultaneous formation. The formation process of a spin-coating or lamination process of Liao is applied to the first photo-sensitive structure 66 (19) and the second photo-sensitive structure 68 of Su, and further in view of Yang.
Response to Arguments
Applicant’s arguments, see page 6, filed 01/08/2026, with respect to the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ) rejection of Claim 21 have been fully considered and are persuasive. The 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ) rejection of Claim 21 has been withdrawn.
Applicant's arguments, see pages 6-12 filed 01/08/2026, with respect claims 1-10 & 21-30 have been fully considered but they are not persuasive. The new grounds of rejection remaps previous prior art references and combines additional references not applied in the prior Office action and overcomes the amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814