DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed 12/08/2025 have been fully considered but are moot in view of the new grounds of rejection as detailed below as necessitated by Applicant’s claim amendments. Applicant’s arguments on page 6 state that a Terminal Disclaimer was submitted herewith but the current record does not show that a Terminal Disclaimed has been filed and therefore the obvious-type double patenting rejection is updated in light of the claim amendments as detailed below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims of U.S. Patent No. 11,476,369 in view of U.S. Patent Application Publication Number 2019/0013312 A1 to Saggio et al., “Saggio”.
Although the claims at issue are not identical, they are not patentably distinct from each other because of the anticipating limitations in bold:
Pending claims
claim 1, A SiC semiconductor device, comprising:
a substrate of a first conductivity type;
a drift region disposed on the substrate;
a junction field effect transistor (JFET) region of the first conductivity type, the JFET region being disposed on the drift region;
a body region of a second conductivity type, the body region being disposed on the drift region and adjacent to the JFET region;
a Schottky contact disposed over the JFET region and over a portion of the body region; and
a MOSFET having a source region of the first conductivity type that is electrically connected to the Schottky contact, a drain region of the first conductivity type, a gate, and a gate oxide disposed over the body region and the source region.
U.S. Patent Number 11476369
14. A SiC semiconductor device, comprising:
a substrate of a first conductivity type;
a drift region disposed on the substrate;
a junction field effect transistor (JFET) region of the first conductivity type, the JFET region being disposed on the drift region;
a body region of a second conductivity type, the body region being disposed on the drift region and adjacent to the JFET region;
a Schottky contact disposed over the JFET region and over a portion of the body region; a lateral channel layer of the first conductivity type, extending laterally over the body region and the JFET region, and partially adjacent to the Schottky contact; and a MOSFET having a source region of the first conductivity type that is electrically connected to the Schottky contact, a drain region of the first conductivity type, a gate, and a gate oxide disposed over the body region, the lateral channel layer, and the source region.
U.S. Patent Number 11476369 fails to clearly claim wherein the Schottky contact defines a Schottky interface with the JFET region.
Saggio teaches (Fig. 3, Fig. 4) wherein a Schottky contact (source 43) defines a Schottky interface (37, ¶ [0066]) with a JFET region (35).
It would have been obvious to one having ordinary skill in the art to have formed the device of U.S. Patent Number 11476369 as claimed with the Schottky interface directly to the JFET as exemplified by Saggio in order to desirably form a direct Schottky contact within the cell thereby reducing the size of the device (Saggio ¶ [0022],[0087]).
Pending claim 2 is anticipated by U.S. Patent Number 11476369’s claim 14.
Pending claim 3 is anticipated by U.S. Patent Number 11476369’s claim 14.
Pending claim 4 is anticipated by U.S. Patent Number 11476369’s claim 14.
Pending claim 5 is anticipated by U.S. Patent Number 11476369’s claim 14.
Pending claim 6 is anticipated by U.S. Patent Number 11476369’s claim 15.
Pending claim 7 is anticipated by U.S. Patent Number 11476369’s claim 16.
Pending claim 8 is anticipated by U.S. Patent Number 11476369’s claim 18.
Pending claims
Claim 9, A Silicon Carbide (SiC) semiconductor device, comprising:
an n-type substrate;
a drift region disposed on the n-type substrate;
a p-type body region disposed on the drift region;
a vertical Junction Field Effect Transistor (JFET) region disposed on the drift region;
a Schottky contact disposed over the vertical JFET region; and
a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a source region electrically connected to the p-type body region and to the Schottky contact,
a gate and gate oxide disposed at least partially on the p-type body region, and
a drain contact electrically connected to the n-type substrate.
U.S. Patent Number 11476369
1. A Silicon Carbide (SiC) semiconductor device, comprising:
an n-type substrate;
a drift region disposed on the n-type substrate;
a p-type body region disposed on the drift region;
a vertical Junction Field Effect Transistor (JFET) region disposed on the drift region;
a Schottky contact disposed over the p-type body region and the vertical JFET region;
a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a source region electrically connected to the p-type body region and to the Schottky contact,
a gate and gate oxide disposed at least partially on the p-type body region, and
a drain contact electrically connected to the n-type substrate; and an n-type lateral channel layer at least partially overlapping the gate oxide, the Schottky contact, the p-type body region, and the vertical JFET region, and electrically connecting the MOSFET and the vertical JFET region.
U.S. Patent Number 11476369 fails to clearly claim wherein the Schottky contact defines a Schottky interface with the JFET region.
Saggio teaches (Fig. 3, Fig. 4) wherein a Schottky contact (source 43) defines a Schottky interface (37, ¶ [0066]) with a JFET region (35).
It would have been obvious to one having ordinary skill in the art to have formed the device of U.S. Patent Number 11476369 as claimed with the Schottky interface directly to the JFET as exemplified by Saggio in order to desirably form a direct Schottky contact within the cell thereby reducing the size of the device (Saggio ¶ [0022],[0087]).
Pending claim 10 is anticipated by U.S. Patent Number 11476369’s claim 1.
Pending claim 11 is anticipated by U.S. Patent Number 11476369’s claim 1.
Pending claim 12 is anticipated by U.S. Patent Number 11476369’s claim 1.
Pending claim 13 is anticipated by U.S. Patent Number 11476369’s claim 3.
Pending claim 14 is anticipated by U.S. Patent Number 11476369’s claim 4.
Pending claim 15 is anticipated by U.S. Patent Number 11476369’s claim 6.
Pending claim 16 is anticipated by U.S. Patent Number 11476369’s claim 13.
Pending claim 17 is anticipated by U.S. Patent Number 11476369’s claim 5.
Pending claim 18 is anticipated by U.S. Patent Number 11476369’s claim 10.
Pending claims
Claim 19, A method of making a SiC semiconductor device, the method comprising:
providing a drift region on a SiC substrate of a first conductivity type;
providing a body region of a second conductivity type on the drift region;
providing a JFET region of the first conductivity type on the drift region and adjacent to the body region;
providing a Schottky contact laterally overlapping an entirety of the JFET region; and
providing a MOSFET having a source region electrically connected to the body region and to the Schottky contact, a gate and gate oxide disposed at least partially on the body region, and a drain contact electrically connected to the substrate.
U.S. Patent Number 11476369
19. A method of making a SiC semiconductor device, the method comprising:
providing a drift region on a SiC substrate of a first conductivity type;
providing a body region of a second conductivity type on the drift region;
providing a JFET region of the first conductivity type on the drift region and adjacent to the body region;
providing a lateral channel layer of the first conductivity type, extending laterally across the body region and the JFET region;
providing a Schottky contact laterally overlapping an entirety of the JFET region and a portion of the lateral channel layer; and
providing a MOSFET having a source region electrically connected to the body region and to the Schottky contact, a gate and gate oxide disposed at least partially on the body region and on the lateral channel layer, and a drain contact electrically connected to the substrate.
U.S. Patent Number 11476369 fails to clearly claim wherein the Schottky contact defines a Schottky interface with the JFET region.
Saggio teaches (Fig. 3, Fig. 4) wherein a Schottky contact (source 43) defines a Schottky interface (37, ¶ [0066]) with a JFET region (35).
It would have been obvious to one having ordinary skill in the art to have performed the method of U.S. Patent Number 11476369 as claimed with the Schottky interface directly to the JFET as exemplified by Saggio in order to desirably form a direct Schottky contact within the cell thereby reducing the size of the device (Saggio ¶ [0022],[0087]).
Pending claim 20 is anticipated by U.S. Patent Number 11476369’s claim 19.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,9,10,17,19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication Number 2019/0013312 A1 to Saggio et al., “Saggio”.
Regarding claim 1, Saggio discloses a SiC semiconductor device (Title, Fig. 3, Fig. 4), comprising:
a substrate (47, ¶ [0052]) of a first conductivity type (N as pictured, from Fig. 1 N-type SiC body 2, ¶ [0005]);
a drift region (46, ¶ [0052]) disposed on the substrate;
a junction field effect transistor (JFET) region (35, ¶ [0054],[0055]) of the first conductivity type (N type, same as drift layer, formed from e.g. Fig. 1 body 2 ¶ [0005]) the JFET region being disposed on the drift region;
a body region (e.g. 23, ¶ [0053]) of a second conductivity type (P type), the body region (23) being disposed on the drift region (46) and adjacent to the JFET region (35);
a Schottky contact (source metal 43, ¶ [0064],[0066]) disposed over the JFET region (35) and over a portion of the body region (23), and defining a Schottky interface (37, ¶ [0066]) with the JFET region (35); and
a MOSFET having a source region (e.g. 24, ¶ [0066]) of the first conductivity type (N type, labelled N) that is electrically connected to the Schottky contact (source 43), a drain region (44) of the first conductivity type (lower portion of 47, similar to Applicant’s drain metal 170 contacting substrate 101), a gate (29), and a gate oxide (28) disposed over the body region (23) and the source region (24).
Regarding claim 9, Saggio discloses a Silicon Carbide (SiC) semiconductor device (Title, Fig. 3, Fig. 4), comprising:
an n-type substrate (47, ¶ [0052], N as pictured, from Fig. 1 N-type SiC body 2, ¶ [0005]);
a drift region (46, ¶ [0052]) disposed on the n-type substrate;
a p-type body region (e.g. 23, ¶ [0053]) disposed on the drift region;
a vertical Junction Field Effect Transistor (JFET) region (35, ¶ [0054],[0055]) disposed on the drift region;
a Schottky contact (source metal 43, ¶ [0064],[0066]) disposed over the vertical JFET region, and defining a Schottky interface (37, ¶ [0066]) with the JFET region; and
a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) having a source region (e.g. 24, ¶ [0066]) electrically connected to the p-type body region (23) and to the Schottky contact (source 43), a gate (29) and gate oxide (28) disposed at least partially on the p-type body region (23), and a drain contact (44, ¶ [0065]) electrically connected to the n-type substrate (47).
Regarding claim 10, Saggio discloses the SiC semiconductor device of claim 9, and Saggio further discloses wherein the Schottky contact (source 43) is disposed over the p-type body region (23).
Regarding claim 17, Saggio discloses the SiC semiconductor device of claim 9, and Saggio further discloses wherein, during a flow of on-state current of the MOSFET (Fig. 5, turn-on state of MOSFET 54), an inversion channel (inherent) of the MOSFET is formed at a boundary of the gate oxide (28) to the p-type body region (23, since flow must occur from source terminal 43 through source 24 through p-body 23 to JFET 35 through drift 46 to drain 44).
Regarding claim 19, Saggio discloses a method of making a SiC semiconductor device, the method comprising:
providing a drift region (46, ¶ [0052]) on a SiC substrate of a first conductivity type (47, ¶ [0052], N as pictured, from Fig. 1 N-type SiC body 2, ¶ [0005]);
providing a body region (e.g. 23, ¶ [0053])of a second conductivity type (P type) on the drift region;
providing a JFET region (35, ¶ [0054],[0055]) of the first conductivity type on the drift region and adjacent to the body region;
providing a Schottky contact (source metal 43, ¶ [0064],[0066]) laterally overlapping an entirety of the JFET region, and defining a Schottky interface (37, ¶ [0066]) with the JFET region; and
providing a MOSFET having a source region (e.g. 24, ¶ [0066]) electrically connected to the body region and to the Schottky contact, a gate (29) and gate oxide (28) disposed at least partially on the body region, and a drain contact (44, ¶ [0065]) electrically connected to the substrate.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
U.S. Patent Application Publication Number 2021/0305422 A1 to Sheng et al. discloses a SiC semiconductor device (FIG. 3a,3), comprising:
a substrate (P-type region 33, ¶ [0045]);
a drift region (lower portion of 18, ¶ [0028]) disposed on the substrate;
a junction field effect transistor (JFET) region (FIG. 3a region of 18 below 29 and including 32, ¶ [0028],[0036]) of the first conductivity type (N-type), the JFET region being disposed on the drift region (lower portion of 18);
a body region (19, ¶ [0036]) of a second conductivity type (P-type), the body region being disposed on the drift region (lower 18) and adjacent to the JFET region (FIG. 3a region of 18 to the right of 19);
a Schottky contact (source metal 27, ¶ [0036]) disposed over the JFET region (upper portion of 18) and over a portion of the body region (part of source metal 27 is over 19), and defining a Schottky interface (201, ¶[0036]) with the JFET region (region 32 which is a part of upper 18); and
a MOSFET (e.g. 29) having a source region (20, ¶ [0036]) of the first conductivity type that is electrically connected to the Schottky contact, a drain region (portion of 33 near drain 16, similar to Applicant’s drain electrode 170 connected to substrate 101) of the first conductivity type (P-type), a gate (25), and a gate oxide (24) disposed over the body region (19) and (indirectly over, similar to Applicant’s 150) the source region (21).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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/Eric A. Ward/Primary Examiner, Art Unit 2891