DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/18/2026 has been entered.
Terminal Disclaimer
The terminal disclaimer filed on 05/18/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 11476369 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Arguments
Applicant's arguments filed 05/18/2026 have been fully considered but they are moot in view of the updated grounds of rejection to address Applicant’s claim amendments or indication of allowable subject matter as detailed below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2019/0013312 A1 to Saggio et al., “Saggio”, in view of U.S. Patent Application Publication Number 2020/0161445 A1 to Miyamoto et al., “Miyamoto”.
Regarding claim 1, Saggio discloses a SiC semiconductor device (Title, Fig. 3, Fig. 4), comprising:
a substrate (47, ¶ [0052]) of a first conductivity type (N as pictured, from Fig. 1 N-type SiC body 2, ¶ [0005]);
a drift region (46, ¶ [0052]) disposed on the substrate;
a junction field effect transistor (JFET) region (35, ¶ [0054],[0055]) of the first conductivity type (N type, same as drift layer, formed from e.g. Fig. 1 body 2 ¶ [0005]) the JFET region being disposed on the drift region;
a body region (e.g. 23, ¶ [0053]) of a second conductivity type (P type), the body region (23) being disposed on the drift region (46) and adjacent to the JFET region (35);
a Schottky contact (source metal 43, ¶ [0064],[0066]) disposed over the JFET region (35) and over a portion of the body region (23), and defining a Schottky interface (37, ¶ [0066]) with the JFET region (35); and
a MOSFET having a source region (e.g. 24, ¶ [0066]) of the first conductivity type (N type, labelled N) that is electrically connected to the Schottky contact (source 43), a drain region (44) of the first conductivity type (lower portion of 47, similar to Applicant’s drain metal 170 contacting substrate 101), a gate (29), and a gate oxide (28) disposed over the body region (23) and the source region (24), and
a source terminal (“S”) electrically connected to the Schottky contact (source metal 43) and the source region (e.g. 24), and
a first interlayer dielectric (dielectric cap 33, ¶ [0061],[0062]) disposed between the gate (29) and the Schottky contact (43).
Saggio fails to clearly teach additionally a second interlayer dielectric disposed between the gate and the source terminal.
Miyamoto teaches (e.g. FIG. 1, FIG. 4) a second interlayer dielectric (e.g. one or more of “IL” or “FI”, ¶ [0055],[0058],[0060]) between a gate (“GE”, ¶ [0056],[0057]) and a source terminal (“SE”, ¶ [0060],[0061]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Saggio with one or more additional dielectrics as taught by Miyamoto in order to precisely determine the position of the ohmic contact part (e.g. Miyamoto FIG. 17 openings in “IL” and “FI” determine placement of “SI”, ¶ [0119],[0120], similarly in FIG. 30) and/or in order to incorporate a gate protecting capping layer (“IF2” may be silicon nitride ¶ [0057] which is known to be an etch stop or protecting material).
Regarding claim 19, Saggio discloses a method of making a SiC semiconductor device, the method comprising:
providing a drift region (46, ¶ [0052]) on a SiC substrate of a first conductivity type (47, ¶ [0052], N as pictured, from Fig. 1 N-type SiC body 2, ¶ [0005]);
providing a body region (e.g. 23, ¶ [0053])of a second conductivity type (P type) on the drift region;
providing a JFET region (35, ¶ [0054],[0055]) of the first conductivity type on the drift region and adjacent to the body region;
providing a Schottky contact (source metal 43, ¶ [0064],[0066]) laterally overlapping an entirety of the JFET region, and defining a Schottky interface (37, ¶ [0066]) with the JFET region; and
providing a MOSFET having a source region (e.g. 24, ¶ [0066]) electrically connected to the body region and to the Schottky contact, a gate (29) and gate oxide (28) disposed at least partially on the body region, and a drain contact (44, ¶ [0065]) electrically connected to the substrate, a source terminal (“S”) electrically connected to the Schottky contact (source metal 43) and the source region (e.g. 24), and
a first interlayer dielectric (dielectric cap 33, ¶ [0061],[0062]) disposed between the gate (29) and the Schottky contact (43).
Saggio fails to clearly teach additionally a second interlayer dielectric disposed between the gate and the source terminal.
Miyamoto teaches (e.g. FIG. 1, FIG. 4) a second interlayer dielectric (e.g. one or more of “IL” or “FI”, ¶ [0055],[0058],[0060]) between a gate (“GE”, ¶ [0056],[0057]) and a source terminal (“SE”, ¶ [0060],[0061]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have performed the method of Saggio with one or more additional dielectrics as taught by Miyamoto in order to precisely determine the position of the ohmic contact part (e.g. Miyamoto FIG. 17 openings in “IL” and “FI” determine placement of “SI”, ¶ [0119],[0120], similarly in FIG. 30) and/or in order to incorporate a gate protecting capping layer (“IF2” may be silicon nitride ¶ [0057] which is known to be an etch stop or protecting material).
Allowable Subject Matter
Claims 9-18 are allowed.
Claims 2-8,20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art e.g. Saggio teaches a semiconductor device including a JFET region with Schottky and ohmic contact as discussed above.
Prior art generally teaches wherein polysilicon may form a Schottky contact, e.g. U.S. Patent Application Publication Number 2014/0145289 A1 to Zhang et al. Schottky layer 24 ¶ [0005].
However, prior art fails to reasonably teach or suggest a source terminal electrically connected to the polysilicon Schottky contact and the source region; a first interlayer dielectric disposed between the gate and the polysilicon Schottky contact; and a second interlayer dielectric disposed between the gate and the source terminal, together with all of the other limitations of claim 9 as claimed. Claims 10-18 are allowable insofar as they depend upon and include all of the limitations of allowable claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
Prosecution Insights