DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Embodiment 1 in the reply filed on 9/22/2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 22 and 38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 22 and 38 recite the limitation "thinned die" in lines 7 and 10 respectively. There is insufficient antecedent basis for this limitation in the claim.
Claims 22 and 38 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are: the steps of thinning the wafer to produce the claimed “thinned die”.
Examiner’s note: claims 22 and 38 recite “a thinned die” but do not recite a step that produces the thinned die from the claimed wafer. Hence, it is unclear in claims if the thinned die is a result of processing the wafer, at which point in the manufacturing process the thinning is intended to occur, or a new component apart from the wafer, etc.
For the purposes of examination in this office action, it is noted that the Uzoh reference describes the wafer as a thin slab of semiconductor material; hence, it will be assumed that the material is thinned as some point of the manufacturing process or simply formed initially to be thin, and this disclosure is applied to the limitation of “a thinned die”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 7, 9, 11, 15, 16, 22-24, 38, and 40 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uzoh (U.S. Pub #2018/0308819).
With respect to claim 1, Uzoh teaches a method of forming a microelectronic assembly, the method comprising:
attaching a wafer (Fig. 3, 302) to a support layer (Fig. 3, 308);
singulating the wafer with the support layer attached to a dicing structure (Fig. 3, 306) to form a plurality of semiconductor die components (Fig. 3, step 3, 310; Paragraph 34), each semiconductor die component of the plurality of semiconductor die components having a die and a support layer section of the support layer attached to the die, the support layer section (Fig. 3, step 5, 308) disposed between the die (Fig. 3, step 5, 310) and the dicing structure (Fig. 3, step 5, 306); and
directly bonding a first semiconductor die component of the plurality of semiconductor die components to a substrate without an intervening adhesive (Fig. 3, step 10 and Paragraph 69), such that the die is disposed between the substrate and the support layer section.
With respect to claim 2, Uzoh teaches after the directly bonding, removing the support layer section from the die (Fig. 3, step 12 and Paragraph 45).
With respect to claim 4, Uzoh teaches after attaching the wafer to the support layer (Fig. 3, step 2), attaching the support layer to the dicing structure (Fig. 3, step 3).
With respect to claim 7, Uzoh teaches singulating the wafer and the support layer in a single dicing process (Paragraph 34).
With respect to claim 9, Uzoh teaches before the singulating, providing a protective layer (Fig. 3, 304 and Paragraph 34) over a bonding surface of the wafer.
With respect to claim 11, Uzoh before providing the protective layer, forming the bonding surface, forming the bonding surface comprising planarizing the wafer (Fig. 3 step 1, 302; the surface is flat/planar, Paragraph 7 and 23).
With respect to claim 15, Uzoh teaches before directly bonding, removing the first semiconductor die component from the dicing structure and flipping the first semiconductor die component such that a bonding surface of the die faces the substrate (Fig. 3, steps 6-7, the top surface of 310 in step 6 is flipped downward to bond to the substrate 314, the bottom surface of 310 having the layer 308 is the upper surface in step 7).
With respect to claim 16, Uzoh teaches providing the support layer, the support layer comprising an ultraviolet (UV) release polymer sheet or a thermal release polymer sheet (Fig. 3, 308 and Paragraph 35).
With respect to claim 22, Uzoh teaches a method of forming a microelectronic assembly, the method comprising:
attaching a support layer (Fig. 3, 308) to a dicing structure (Fig. 3, 306);
attaching a wafer (Fig. 3, 302) to the support layer;
providing a protective layer (Fig. 3, 304) on the wafer;
singulating the wafer, the protective layer, and the support layer to form a semiconductor die component having a thinned die (Paragraph 4, “a thin slab of material”) and a support layer section stacked together (Fig. 3, step 3);
removing the protective layer from the semiconductor die component to expose a bonding surface of the thinned die (Fig. 3, step 4-6; Paragraph 34-36);
detaching the semiconductor die component from the dicing structure (Paragraph 40);
attaching the semiconductor die component to a substrate (Fig. 3, step 10, 314) such that the thinned die is interposed between the support layer section (Fig. 3, step 10, 308) and the substrate and the bonding surface of the thin die is directly bonded to the substrate without an intervening adhesive (Paragraph 69); and
after attaching the semiconductor die component to the substrate, detaching the support layer section from the thinned die to expose a back surface of the thinned die (Fig. 3, step 12 and Paragraph 45).
With respect to claim 23, Uzoh teaches that singulating the wafer, the protective layer, and the support layer comprises forming a second semiconductor die component having a second thinned die and a second support layer section stacked together (Fig. 3, multiple die sections 310).
With respect to claim 24, Uzoh teaches removing the protective layer from the second semiconductor die component to expose a bonding surface of the second thinned die (Fig. 3, step 4-6; Paragraph 34-36);
detaching the second semiconductor component from the dicing tape (Paragraph 40)and attaching it to the substrate such that the second thinned die is interposed between the second support layer section and the substrate (Fig. 3 step 14), and the bonding surface of the second thinned die is directly bonded to the substrate without an intervening adhesive (Paragraph 69); and
detaching the second support layer section from the second thinned die to expose a back surface of the second thinned die (Fig. 3, step 12 and Paragraph 45).
With respect to claim 38, Uzoh teaches a method of forming a microelectronic assembly, comprising:
attaching a support layer (Fig. 3, 308) to a dicing structure (Fig. 3, 306);
attaching a wafer (Fig. 3, 302) to the support layer;
singulating the wafer and the support layer to form a plurality of semiconductor die components (Fig. 3 step 3, 310), wherein each of the plurality of semiconductor die components comprises a thinned die (Paragraph 4, “a thin slab of material”) and a support layer section stacked together;
detaching each of the plurality of semiconductor die components from the dicing structure (Paragraph 40);
attaching each of the plurality of semiconductor die components to a substrate (Fig. 3 step 10, 314) such that each of the thinned dies is interposed between the substrate and a corresponding support layer section and such that bonding surfaces of each of the thinned dies are directly bonded to the substrate without an intervening adhesive (Paragraph 69); and
detaching the support layer sections from each of the thinned dies to expose a back surface of each of the thinned dies (Fig. 3 step 12, Paragraph 45).
With respect to claim 40, Uzoh teaches singulating the wafer and the support layer in a single dicing process (Paragraph 34).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, in view of Chen et al (U.S. Pub #2021/0057332).
With respect to claim 3, Uzoh does not teach providing a second semiconductor die component having a second die and a second support layer section attached to the second die; and after the removing, directly bonding the second die to the die without an adhesive such that the second die is disposed between the die and the second support layer section.
Chen teaches providing a second semiconductor die component (Fig. 4B, 10B) having a second die; and
after the removing, directly bonding the second die to the die (Fig. 4B, 10C) without an adhesive (Paragraph 47).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to remove a second die and support layer section of Uzoh, and directly bond to the first die such that the second die is disposed between the die and the second support layer section, as taught by Chen in order to provide a die stack having improved bandwidth (Paragraph 59).
With respect to claim 25, Uzoh does not teach providing a second semiconductor die component having a second thinned die and a second support layer section attached to the second thinned die; and
directly bonding the second thinned die to the thinned die without an adhesive such that the second thinned die is disposed between the thinned die and the second support layer section.
Chen teaches providing a second semiconductor die component (Fig. 4B, 10B) having a second die; and
after the removing, directly bonding the second die to the die (Fig. 4B, 10C) without an adhesive (Paragraph 47).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to remove a second die and support layer section of Uzoh, and directly bond to the first die such that the second die is disposed between the die and the second support layer section, as taught by Chen in order to provide a die stack having improved bandwidth (Paragraph 59).
Claims 4 rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, in view of Uzoh et al (U.S. Pub #2018/0331066)
With respect to claim 4, Uzoh ‘066 teaches after attaching the wafer to the support layer (Fig. 2a, 208), attaching the support layer to the dicing structure (Fig. 2b, 212).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to attaching the wafer to the support layer first as taught by Uzoh ‘066 in order to achieve the predictable result of providing the support layer between the wafer and dicing structure.
Claims 5 rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, in view of Uenda et al (U.S. Pub #2012/0126380)
With respect to claim 5, Uzoh does not teach before attaching the wafer to the support layer, attaching the support layer to the dicing structure.
Uenda teaches a before attaching the wafer (Fig. 4, 4) to the support layer, attaching the support layer (Fig. 3, 40) to the dicing structure (Fig. 3, 2).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to attaching the wafer to the support layer first as taught by Uenda in order to achieve the predictable result of providing the support layer between the wafer and dicing structure.
Claims 6 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, in view of Esteron et al (U.S. Pub #2021/0043512).
With respect to claim 6 and 39, Uzoh does not teach singulating the wafer before singulating the support layer.
Esteron teaches singulating a wafer before singulating a support layer (Fig. 5C, the singulating saw 522 separates the upper wafer before reaching the lower support layer 523).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to singulating the wafer before singulating the support layer as taught by Esteron in order to achieve the predictable result of separating the wafer and support layer into chip sections.
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, in view of Takyu et al (U.S. Pub #2005/0003636)
With respect to claim 17, Uzoh does not teach the support layer comprising a porous support layer.
Takyu teaches a support layer for wafer dicing, wherein the support layer comprising a porous support layer (Paragraph 64).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a porous layer on the dicing structure of Uzoh as taught by Takyu in order to achieve the predictable result of holding/supporting the wafer during dicing.
Claim 19 rejected under 35 U.S.C. 103 as being unpatentable over Uzoh, in view of Sun et al (U.S. Pub #2008/0003780).
With respect to claim 19, Uzoh does not teach that attaching the wafer to the support layer comprises attaching the wafer to the support layer with an adhesive, wherein the adhesive comprises an ultraviolet (UV) adhesive configured to lose adhesion after being exposed to UV radiation, the method comprising detaching the support layer section from the die by exposing the adhesive to UV radiation.
Sun teaches attaching the wafer to the support layer comprises attaching the wafer to the support layer (Fig. 2C, 255) with an adhesive (Fig. 2C, 250 and Paragraph 40),
wherein the adhesive comprises an ultraviolet (UV) adhesive configured to lose adhesion after being exposed to UV radiation (Paragraph 40), the method comprising
detaching the support layer section (Fig. 3, 255) from the die by exposing the adhesive to UV radiation (Fig. 3, and Paragraph 51, 53).
It would have been obvious to one of ordinary skill in the art at the time the invention was effectively filed to provide a support layer and adhesive as taught by Sun in order to achieve the predictable result of providing a detachable support layer for a die.
Allowable Subject Matter
Claim 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN P SANDVIK whose telephone number is (571)272-8446. The examiner can normally be reached M-F: 10-6.
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/BENJAMIN P SANDVIK/Primary Examiner, Art Unit 2812