DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/26/2025 has been entered.
Response to Amendment
Applicant's amendments on 11/5/2025 have been reviewed and entered. Claims 1, 8, 10, 14, 17, and 24-25 have been amended, and claims 4, 11, 13, 20, and 26-27 have been canceled by the applicant. Accordingly, claims 1-3, 5-10, 12, 14,19, and 21-25 remain for examination.
Applicant’s amendment to claim 8 and cancellation of claim 11 have overcome the claim objections previously set forth in the Final Office Action mailed on 9/4/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5-8, 17, and 21-25 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Hideki (JP 2012060028 A).
Regarding claim 1, Hideki teaches a silicon-on-insulator transistor (silicon on insulator (SOI) transistor, Fig. 3, [0026]), comprising:
a silicon layer (SOI layer 5, see Illustrative Fig. 1 which is an annotated version of Hideki’s Fig. 3, [0026]) including a channel region (while Hideki does not mention a channel region, a person of ordinary skill in the art would understand that an SOI transistor would include a channel region, and for the transistor structure disclosed by Hideki the channel region is the SOI layer 5 under the gate electrode 15 as shown in Illustrative Fig. 1; see also Fig. 5 of Yeo (US 2004/0217420 A1) for a three dimensional illustration of an SOI transistor) having a width (width W, Illustrative Fig. 1) extending from a first edge (first edge, Illustrative Fig. 1) of the silicon layer (SOI layer 5, Illustrative Fig. 1) to a second edge (second edge, Illustrative Fig. 1) of the silicon layer (SOI layer 5, Illustrative Fig. 1);
a gate structure (gate electrode 15, Illustrative Fig. 1, [0017]) overlaying the channel region (channel region, Illustrative Fig. 1);
and
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a gate oxide layer (comprising gate oxide film 7, first silicon oxide film 9, Illustrative Fig. 1, [0025]-[0026]) disposed between gate structure (gate electrode 15, Illustrative Fig. 1) and the silicon layer (SOI layer 5, Illustrative Fig. 1), wherein the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 1) comprises a first portion (first portion, Illustrative Fig. 1: first portion corresponds to the flat portion of the first silicon oxide film 9 on the left side) extending along the first edge (first edge, Illustrative Fig. 1, [0026]: end portion of the upper surface) of the silicon layer (SOI layer 5, Illustrative Fig. 1), a second portion (second portion, Illustrative Fig. 1: second portion corresponds to gate oxide film 7) extending from the first portion (first portion, Illustrative Fig. 1) across the width (width W, Illustrative Fig. 1) of the channel region (channel region, Illustrative Fig. 1) to a third portion (third portion, Illustrative Fig. 1: third portion corresponds to the flat portion of the first silicon oxide film 9 on the right side) extending along the second edge (second edge, Illustrative Fig. 1, [0026]) of the silicon layer (SOI layer 5, Illustrative Fig. 1), wherein the first portion (first portion, Illustrative Fig. 1) and the third portion (third portion, Illustrative Fig. 1) each has a substantially uniform first thickness (thicknesses within the dashed lines indicating the borders of the first and third portions are uniform, [0031]: the first silicon oxide film 9 having a thickness of about 40 nm is formed at the thickest portion on the upper end portion of the mesa type SOI layer 5) that is greater than a substantially uniform second thickness of the second portion (second portion, Illustrative Fig. 1, [0027]: “the first silicon oxide film 9 is formed thicker than the gate oxide film 7 in the vertical direction at the upper surface end portion of the mesa-shaped SOI layer 5”).
Regarding claim 5, Hideki teaches the silicon-on-insulator transistor of claim 1, wherein the second portion (second portion, Illustrative Fig. 1: second portion corresponds to gate oxide film 7) of the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 1) is in an active region (channel region, Illustrative Fig. 1).
Regarding claim 6, Hideki teaches the silicon-on-insulator transistor of claim 1, wherein the first portion (first portion, Illustrative Fig. 1) of the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 1), the first edge (first edge, Illustrative Fig. 1) of the silicon layer (SOI layer 5, see Illustrative Fig. 1), and the gate structure (the portion of the gate electrode over the first edge, Illustrative Fig. 1) on the first edge (first edge, Illustrative Fig. 1) defines a first edge transistor (parasitic MOS transistor, [0018]: “the parasitic MOS transistor formed at the end portion of the upper surface of the mesa-type SOI layer 5”).
Regarding claim 7, Hideki teaches the silicon-on-insulator transistor of claim 6, wherein a threshold voltage of the first edge transistor (parasitic MOS transistor, [0018]) is greater than zero volts ([0018]: forming the first silicon oxide film 9 is thicker than the gate oxide film 7 in the vertical direction increases the threshold voltage of the parasitic MOS transistor, and therefore the threshold voltage of the parasitic MOS transistor is larger than zero volts).
Regarding claim 8, Hideki teaches the silicon-on-insulator transistor of claim 6, wherein a threshold voltage of the first edge transistor (parasitic MOS transistor, [0018]) is greater than a threshold voltage of a transistor with a gate oxide layer thickness that is less than the first thickness ([0018]: “At the end of the upper surface of the mesa type SOI layer 5, the first silicon oxide film 9 is formed thicker than the gate oxide film 7 in the vertical direction. As a result, the threshold voltage of the parasitic MOS transistor formed at the end portion of the upper surface of the mesa-type SOI layer 5 can be increased, and the operation of the parasitic MOS transistor is suppressed, thereby realizing a highly reliable SOI transistor.” which indicated that a threshold voltage of the first edge transistor is greater than a threshold voltage of a transistor with a gate oxide layer thickness that is less than the first thickness).
Regarding claim 17, Hideki teaches a method (Fig. 4, [0028]) of forming a silicon-on-insulator transistor (silicon on insulator (SOI) transistor, Fig. 3, [0026]), comprising:
providing a silicon layer (SOI layer 5, Fig. 4(3), [0029]) having a channel region (while Hideki does not mention a channel region, a person of ordinary skill in the art would understand that an SOI transistor would include a channel region, and for the transistor structure disclosed by Hideki the channel region is the SOI layer 5 under the gate electrode 15 as shown in Illustrative Fig. 1; see also Fig. 5 of Yeo (US 2004/0217420 A1) for a three dimensional illustration of an SOI transistor), wherein the channel region (see channel region as indicated in Illustrative Fig. 2, which is an annotated version of Fig. 3; this region is equivalent to the silicon on insulator (SOI) layer 5 as shown in Fig. 4(3)) has a width (width W, Illustrative Fig. 2) extending from a first edge (first edge, Illustrative Fig. 2) of the silicon layer (SOI layer 5, Illustrative Fig. 2) to a second edge (second edge, Illustrative Fig. 2) of the silicon layer (SOI layer 5, Illustrative Fig. 2);
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providing a gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 2 and Fig. 4(1-5), [0033]: while not shown in the figures, after step 5 in Fig. 4, there is another step which includes that “the gate oxide film 7 is formed, the thickness of the first silicon oxide film 9 is increased, and the gate electrode 15 is formed, thereby completing the SOI transistor.”); and
providing a gate structure (Illustrative Fig. 2, [0033]: “the gate electrode 15 is formed, thereby completing the SOI transistor”) at least partially overlaying the silicon layer (SOI layer 5, Illustrative Fig. 2), wherein:
the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 2) is disposed between the partial overlay (the regions between the gate electrode 15 and SOI layer 5 is filled with gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 2; see also Fig. 5 of Yeo (US 2004/0217420 A1) for a three-dimensional illustration of an SOI transistor) of the gate structure (gate electrode 15, , Illustrative Fig. 2) and the silicon layer (SOI layer 5, Illustrative Fig. 2); and
the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 2, [0025]-[0026]) comprises a first portion (first portion, Illustrative Fig. 2: first portion corresponds to the flat portion of the first silicon oxide film 9 on the left side) extending along the first edge (first portion, Illustrative Fig. 2: first portion corresponds to the flat portion of the first silicon oxide film 9 on the left side) of the silicon layer (SOI layer 5, Illustrative Fig. 2), a second portion (second portion, Illustrative Fig. 2: second portion corresponds to gate oxide film 7) extending from the first portion (first portion, Illustrative Fig. 2) across the width (width W, Illustrative Fig. 2) of the channel region (channel region, Illustrative Fig. 2) to a third portion (third portion, Illustrative Fig. 2: third portion corresponds to the flat portion of the first silicon oxide film 9 on the right side) extending along the second edge (second edge, Illustrative Fig. 2, [0026]) of the silicon layer (SOI layer 5, Illustrative Fig. 2), wherein the first portion (first portion, Illustrative Fig. 2) and the third portion (third portion, Illustrative Fig. 2) each has a substantially uniform first thickness (thicknesses within the dashed lines indicating the borders of the first and third portions are uniform, [0031]: the first silicon oxide film 9 having a thickness of about 40 nm is formed at the thickest portion on the upper end portion of the mesa type SOI layer 5) that is greater than a substantially uniform second thickness of the second portion first portion (second portion, Illustrative Fig. 1, [0027]: “the first silicon oxide film 9 is formed thicker than the gate oxide film 7 in the vertical direction at the upper surface end portion of the mesa-shaped SOI layer 5”).
Regarding claim 21, Hideki teaches the method of claim 17, wherein the second portion (second portion, Illustrative Fig. 2: second portion corresponds to gate oxide film 7) of the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 2) is in an active region (channel region, Illustrative Fig. 2).
Regarding claim 22, Hideki teaches the method of claim 17, wherein the first portion (first portion, Illustrative Fig. 2) of the gate oxide layer (comprising gate oxide film 7 and first silicon oxide film 9, Illustrative Fig. 2), the first edge (first edge, Illustrative Fig. 2) of the silicon layer (SOI layer 5, see Illustrative Fig. 2), and the gate structure (the portion of the gate electrode over the first edge, Illustrative Fig. 2) on the first edge (first edge, Illustrative Fig. 2) defines a first edge transistor (parasitic MOS transistor, [0018]: “the parasitic MOS transistor formed at the end portion of the upper surface of the mesa-type SOI layer 5”).
Regarding claim 23, Hideki teaches the method of claim 22, wherein a threshold voltage of the first edge transistor (parasitic MOS transistor, [0018]) is greater than zero volts ([0018]: forming the first silicon oxide film 9 is thicker than the gate oxide film 7 in the vertical direction increases the threshold voltage of the parasitic MOS transistor, and therefore the threshold voltage of the parasitic MOS transistor is larger than zero volts).
Regarding claim 24, Hideki teaches the method of claim 22, wherein a threshold voltage of the first edge transistor (parasitic MOS transistor, [0018]) is greater than a threshold voltage of a transistor with a gate oxide layer having a thickness that is less than the first thickness ([0018]: “At the end of the upper surface of the mesa type SOI layer 5, the first silicon oxide film 9 is formed thicker than the gate oxide film 7 in the vertical direction. As a result, the threshold voltage of the parasitic MOS transistor formed at the end portion of the upper surface of the mesa-type SOI layer 5 can be increased, and the operation of the parasitic MOS transistor is suppressed, thereby realizing a highly reliable SOI transistor.” which indicated that a threshold voltage of the first edge transistor is greater than a threshold voltage of a transistor with a gate oxide layer thickness that is less than the first thickness).
Regarding claim 25, Hideki teaches a silicon-on-insulator transistor (silicon on insulator (SOI) transistor, [0026]), comprising:
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a silicon layer (SOI layer 5, see Illustrative Fig. 3 which is an annotated version of Hideki’s Fig. 3, [0026]) having a channel region (while Hideki does not mention a channel region, a person of ordinary skill in the art would understand that an SOI transistor would include a channel region, and for the transistor structure disclosed by Hideki the channel region is the SOI layer 5 under the gate electrode 15 as shown in Illustrative Fig. 1; see also Fig. 5 of Yeo (US 2004/0217420 A1) for a three dimensional illustration of an SOI transistor), wherein the channel region (channel region, Illustrative Fig. 3) has a width (width W, Illustrative Fig. 3) extending from a first edge (first edge, Illustrative Fig. 3) of the silicon layer (SOI layer 5, Illustrative Fig. 3) to a second edge (second edge, Illustrative Fig. 3) of the silicon layer (SOI layer 5, Illustrative Fig. 3); and
a gate oxide layer (comprising gate oxide film 7, first silicon oxide film 9, Illustrative Fig. 3, [0025]-[0026]) for receiving a portion of a gate structure (gate electrode 15, Illustrative Fig. 1, [0017]; the region between the gate electrode 15 and the SOI layer 5 is filled with gate oxide layer), wherein:
the gate oxide layer (comprising gate oxide film 7, first silicon oxide film 9, Illustrative Fig. 3) comprises a first portion (first portion, Illustrative Fig. 3: first portion corresponds to the flat portion of the first silicon oxide film 9 on the left side) extending along the first edge (first edge, Illustrative Fig. 3, [0026]) of the silicon layer (SOI layer 5, Illustrative Fig. 3), a second portion (second portion, Illustrative Fig. 3: second portion corresponds to gate oxide film 7) extending from the first portion (first portion, Illustrative Fig. 3) across the width (width W, Illustrative Fig. 3) of the channel region (channel region, Illustrative Fig. 3) to a third portion (third portion, Illustrative Fig. 3: third portion corresponds to the flat portion of the first silicon oxide film 9 on the right side) extending along the second edge (second edge, Illustrative Fig. 3, [0026]) of the silicon layer (SOI layer 5, Illustrative Fig. 3), wherein the first portion (first portion, Illustrative Fig. 3) and the third portion (third portion, Illustrative Fig. 3) each has a substantially uniform first thickness (thicknesses within the dashed lines indicating the borders of the first and third portions are uniform, [0031]: the first silicon oxide film 9 having a thickness of about 40 nm is formed at the thickest portion on the upper end portion of the mesa type SOI layer 5) that is greater than a substantially uniform second thickness of the second portion (second portion, Illustrative Fig. 1, [0027]: “the first silicon oxide film 9 is formed thicker than the gate oxide film 7 in the vertical direction at the upper surface end portion of the mesa-shaped SOI layer 5”)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Hideki as applied to claims 1, 5-8, 17, and 21-25 above, and further in view of Ichikawa (US 2003/0006463 A1).
Regarding claim 3, while Hideki teaches the silicon-on-insulator transistor of claim 1,
Hideki does not teach that the gate structure is flared.
Ichikawa, on the other hand, teaches a device on a silicon-on-insulator substrate (NMOS transistor in an SOI device, Fig. 3, [0048]-[0050]), wherein the gate structure is flared (the gate length GLE of the gate electrode 23 is larger than the gate length GLI of the gate electrode 23, Fig. 3, [0050]).
Ichikawa further discloses that having the gate length (GLE) in the edge areas larger than the gate length (GLI) in the active region provides the benefit of reducing the susceptibility of the device to breakdown in the edge areas of the active region than in the case of the conventional structure. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to make the gate structure in the device of Hideki flared, as taught by Ichikawa, so that the gate length in the edge areas is larger than the gate length in the active region, to obtain the benefit of reduced the susceptibility of the device to breakdown in the edge areas of the active region.
Regarding claim 19, Hideki teaches the method of claim 17,
Hideki does not teach that the gate structure is flared.
Ichikawa, on the other hand, teaches a device on a silicon-on-insulator substrate (NMOS transistor in an SOI device, Fig. 3, [0048]-[0050]), wherein the gate structure is flared (the gate length GLE of the gate electrode 23 is larger than the gate length GLI of the gate electrode 23, Fig. 3, [0050]).
Ichikawa further discloses that having the gate length (GLE) in the edge areas larger than the gate length (GLI) in the active region provides the benefit of reducing the susceptibility of the device to breakdown in the edge areas of the active region than in the case of the conventional structure. Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to make the gate structure in the device of Hideki flared, as taught by Ichikawa, so that the gate length in the edge areas is larger than the gate length in the active region, to obtain the benefit of reduced the susceptibility of the device to breakdown in the edge areas of the active region.
Allowable Subject Matter
Claims 2, 9-10, 12, 14-16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2, disclosing that “the first portion of the gate oxide layer covers an entirety of the first edge of the silicon later”, is dependent on claim 1. Therefore, claim 2 would be allowable if this limitation is incorporated with claim 1, or if claim 2 is written in an independent form by incorporating limitations of claim 1.
Claim 9, disclosing that “the first portion of the gate oxide layer is in a first dual-gate region”, is dependent on claim 1. Therefore, claim 9 would be allowable if this limitation is incorporated with claim 1, or if claim 9 is written in an independent form by incorporating limitations of claim 1.
Claims 10, 12, and 14-16, which are directly or indirectly dependent on claim 9, would be allowable if the objection on claim 9 is overcome to render claim 9 to be allowed.
Claim 18, disclosing that “the first portion of the gate oxide layer covers an entirety of the first edge of the silicon later”, is dependent on claim 17. Therefore, claim 2 would be allowable if this limitation is incorporated with claim 17, or if claim 18 is written in an independent form by incorporating limitations of claim 17.
Response to Arguments
It has been acknowledged that the applicant amended claims 1, 8, 10, 14, 17, and 24-25 and canceled claims 4, 11, 13, 20, and 26-27 per response dated on 11/5/2025.
Applicant's arguments with respect to claims have been fully considered. The Examiner agrees with the Applicant on that the amendments to independent claims 1, 17, and 25 overcame claim rejections made previously on claims 1 and 17 based on the prior art Ichikawa (US 2003/0006463 A1, embodiment in Fig. 7, [0008]) and on claim 25 based on prior art Wu (US 2017/0062616 A1).
However, amended independent claims 1, 17, and 25 are now rejected under new grounds based on a new prior-art, Hideki (JP 2012060028 A), in the current office action. Rejections are also made on claims 3, 5-8, 19, and 21-24 based on this new prior-art or its combination with Ichikawa. The rejections on claims 2, 9-10, 12, 14-16, and 18 are withdrawn, as no prior-art made the limitations of these claims anticipated or obvious after the amendments. Accordingly, claims 2, 9-10, 12, 14-16, and 18 are now objected due to their direct or indirect dependency on a rejected claim as detailed above.
For the purpose of compact prosecution, the Examiner notes that incorporating more limitations regarding the first, second, and third portions of the gate oxide layer into independent claims, or incorporating the objected claims into independent claims could make the independent claims 1, 17, and 25 also allowable.
The Examiner is available for an interview at Applicant’s convenience if the Applicant would like to discuss the application.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812