DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/28/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 13-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Seng et al. (US PGPub 2014/0138833, hereinafter referred to as “Seng”).
Seng discloses the semiconductor method as claimed. See figures 1A-8 and corresponding text, where Seng teaches, in claim 13, a method of fabricating a semiconductor device, the method comprising:
providing a bonding surface (310, 200, 120) on a die (100) comprising a semiconductor material (figures 1A; [0030]), wherein the bonding surface (310, 200, 120) comprises a conductive material (200) having a substantially planar surface extending in first and second directions, and one or more corners (202) of the substantially planar surface are radiused or chamfered in the first and second directions (figure 1C; [0044-0046]).
Seng teaches, in claim 14, wherein the one or more corners have a radius of curvature or chamfer dimension of about 100 microns to about 200 microns, or about 200 microns to about 300 microns ([0030]).
Seng teaches, in claim 15, wherein opposing edges of the bonding surface extend along a perimeter of the die at a distance of less than about 25 microns therefrom ([0041]).
Seng teaches, in claim 16, wherein providing the bonding surface comprises: singulating the die from a semiconductor wafer using a laser ablation process to define a surface of the die as the bonding surface comprising the substantially planar surface having the one or more corners that are radiused or chamfered (figure 4B; [0061]).
Seng teaches, in claim 17, wherein the laser ablation process comprises a greater duration of lasing at the one or more corners of the die than at opposing edges thereof ([0061]).
Seng teaches, in claim 18, wherein providing the bonding surface comprises: singulating the die from a semiconductor wafer using a laser ablation process to define a surface of the die having laser-ablated corners that are radiused or chamfered (figures 1C, 3A and 4A-4C; [0060-0062]); and
forming a metal layer (120) on the surface of the die as the bonding surface having the one or more corners that are aligned with the laser-ablated corners (figures 3A-3B; [0052-0057]).
Seng teaches, in claim 19, wherein the metal layer is a backside metallization layer that defines a contact area between the die and a package substrate (figures 3A-3B; [0052-0057]).
Seng teaches, in claim 20, a method of fabricating a semiconductor device, the method comprising:
forming a metal layer (120) on a semiconductor wafer (700a);
patterning the metal layer (120) to define respective bonding surfaces on portions of the semiconductor wafer (700a) corresponding to respective semiconductor dies (100), wherein scribe lines (199) of the semiconductor wafer (700a) between the respective semiconductor dies (100) and adjacent the respective bonding surfaces (120) are free of the metal layer (120) or have a reduced thickness of the metal layer (120) thereon relative to the portions of the wafer (700a) corresponding to the respective semiconductor dies (100); and
after patterning the metal layer (120), singulating the respective semiconductor dies (100) from the semiconductor wafer (700a) along the scribe lines (199) that are free of or have the reduced thickness of the metal layer adjacent the respective bonding surfaces (figures 4A-4C; [0060-0062]).
Seng teaches, in claim 21, wherein forming and patterning the metal layer comprises: forming a mask on the scribe lines of the semiconductor wafer; and performing a sputtering or plating process to selectively deposit the metal layer on areas of the semiconductor wafer that are exposed by the mask such that the scribe lines of the semiconductor wafer are free of the metal layer (figures 4A-4C; [0060-0062]).
Seng teaches, in claim 22, wherein the scribe lines are free of the metal layer or have a reduced thickness of the metal layer responsive to patterning the metal layer, and
wherein singulating the respective semiconductor dies from the semiconductor wafer is performed using a dicing process along the scribe lines (figures 4A-4C; [0060-0062]).
Seng teaches, in claim 23, wherein the respective bonding surfaces comprise opposing edges that extend along a perimeter of the respective semiconductor dies at a distance of less than about 25 microns therefrom (figures 4A-4C; [0041], [0060-0062]).
Seng teaches, in claim 24, wherein the respective bonding surfaces comprise one or more non-orthogonal corners (figure 1C; [0044-0046]).
Seng teaches, in claim 25, wherein the respective bonding surfaces comprise a substantially planar surface extending in first and second directions, the substantially planar surface includes the one or more non-orthogonal corners, and the one or more non-orthogonal corners are radiused or chamfered in the first and second directions (figure 1C; [0044-0046]).
Seng teaches, in claim 26, wherein the substantially planar surface provides a contact area between the die and a substrate, wherein the contact area extends in the first and second directions and includes the one or more corners that are radiused or chamfered in the first and second directions (figure 1C; [0044-0046]).
Seng teaches, in claim 27, wherein the semiconductor material comprises silicon (Si), silicon carbide (SiC), or gallium nitride (GaN), and wherein an elastic modulus of the semiconductor material is greater than that of the conductive material by about 1.5 times or more ([0032]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 April 2, 2026
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