Prosecution Insights
Last updated: October 02, 2026
Application No. 17/935,509

HIGH RELIABILITY SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME

Non-Final OA §102§103
Filed
Sep 26, 2022
Priority
May 24, 2019 — continuation of 11/488,923
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wolfspeed Inc.
OA Round
4 (Non-Final)
86%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
50%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
838 granted / 977 resolved
+17.8% vs TC avg
Minimal -36% lift
Without
With
+-36.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
39 currently pending
Career history
1027
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
44.3%
+4.3% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 977 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the amendment filed on 7/06/26. Currently, claims 1-5, 7-23, and 25-27 are pending. Claims 1-5 and 7-12 are withdrawn. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 13 and 16-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rodriguez et al. (US PGPub 2018/0204786 hereinafter referred to as “Rodriguez”). Rodriguez discloses the semiconductor method as claimed. See figures 1-13 and corresponding text, where Rodriguez teaches, in claim 13, a method of fabricating a semiconductor device, the method comprising: providing a bonding surface (58) on a die (60) comprising a semiconductor material, wherein the bonding surface comprises a conductive material (54) having a substantially planar surface extending in first and second directions, and one or more corners (63, 64) of the substantially planar surface are radiused or chamfered in the first and second directions, wherein the one or more corners are within edges of the die (60) (figure 9; [0034-0036]). Rodriguez teaches, in claim 16, wherein providing the bonding surface comprises: singulating the die from a semiconductor wafer using a laser ablation process. Rodriguez teaches, in claim 17, wherein the laser ablation process comprises a greater duration of lasing at the one or more corners of the die than at opposing edges thereof (figure 9; [0034-0036]). Rodriguez teaches, in claim 18, wherein providing the bonding surface comprises: singulating the die from a semiconductor wafer using a laser ablation process to define a surface of the die having laser-ablated corners that are radiused or chamfered; and forming a metal layer on the surface of the die as the bonding surface having the one or more corners that are aligned with the laser-ablated corners (figure 9; [0034-0036]). Rodriguez teaches, in claim 19, wherein the metal layer (50) is a backside metallization layer that defines a contact area between the die and a package substrate (figure 9; [0034-0036]). Rodriguez teaches, in claim 20, a method of fabricating a semiconductor device, the method comprising: forming a metal layer (50) on a semiconductor wafer (40); patterning the metal layer (50) to define respective bonding surfaces on portions of the semiconductor wafer (40) corresponding to respective semiconductor dies, wherein scribe lines of the semiconductor wafer (40) between the respective semiconductor dies (60) and adjacent the respective bonding surfaces are free of the metal layer (50) or have a reduced thickness of the metal layer (50) thereon relative to the portions of the semiconductor wafer (40) corresponding to the respective semiconductor dies (60); and after patterning the metal layer (50), singulating the respective semiconductor dies (60) from the semiconductor wafer (40) along the scribe lines that are free of or have the reduced thickness of the metal layer adjacent the respective bonding surfaces, wherein the respective bonding surfaces comprise one or more non-orthogonal corners that are within edges of the respective semiconductor dies (figure 9; [0034-0036]). Rodriguez teaches, in claim 21, wherein forming and patterning the metal layer comprises: forming a mask on the scribe lines of the semiconductor wafer; and performing a sputtering or plating process to selectively deposit the metal layer on areas of the semiconductor wafer that are exposed by the mask such that the scribe lines of the semiconductor wafer are free of the metal layer (figure 9; [0034-0036]). Rodriguez teaches, in claim 22, wherein the scribe lines are free of the metal layer or have a reduced thickness of the metal layer responsive to patterning the metal layer, and wherein singulating the respective semiconductor dies from the semiconductor wafer is performed using a dicing process along the scribe lines (figure 9; [0034-0036]). Rodriguez teaches, in claim 23, wherein the respective bonding surfaces comprise opposing edges that extend along a perimeter of the respective semiconductor dies at a distance of less than about 25 microns therefrom (figure 9; [0034-0036]). Rodriguez teaches, in claim 25, wherein the respective bonding surfaces comprise a substantially planar surface extending in first and second directions, the substantially planar surface includes the one or more non-orthogonal corners, and the one or more non-orthogonal corners are radiused or chamfered in the first and second directions (figure 9; [0034-0036]). Rodriguez teaches, in claim 26, wherein the substantially planar surface provides a contact area between the die and a substrate, wherein the contact area extends in the first and second directions) and includes wherein the one or more corners are within the contact area and are radiused or chamfered in the first and second directions (figure 9; [0034-0036]). Rodriguez teaches, in claim 27, wherein the semiconductor material comprises silicon (Si), silicon carbide (SiC), or gallium nitride (GaN), and wherein an elastic modulus of the semiconductor material is greater than that of the conductive material by about 1.5 times or more (figure 9; [0034-0036]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 14 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rodriguez et al. (US PGPub 2018/0204786 hereinafter referred to as “Rodriguez”) as applied to claim 13 above. Rodriguez discloses the semiconductor method substantially as claimed. See the rejection above. However, Rodriguez fails to explicitly teach, in claim 14, wherein the one or more corners have a radius of curvature or chamfer dimension of about 100 microns to about 200 microns, or about 200 microns to about 300 microns. Rodriguez teaches, forming sidewalls (67) that have three portions (63, 64, 65) (implied corners) that prevents delamination of the glue from occurring along the sides of the die ([0035]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the one or more corners have a radius of curvature or chamfer dimension of about 100 microns to about 200 microns, or about 200 microns to about 300 microns, in the method of Rodriguez, according to the teachings of Rodriguez with the motivation of preventing delamination. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), However, Rodriguez fails to explicitly teach, in claim 15, wherein opposing edges of the bonding surface extend along a perimeter of the die at a distance of less than about 25 microns therefrom. Rodriguez teaches, forming sidewalls (67) that have three portions (63, 64, 65) (implied corners) that prevents delamination of the glue from occurring along the sides of the die ([0035]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein opposing edges of the bonding surface extend along a perimeter of the die at a distance of less than about 25 microns therefrom, in the method of Rodriguez, according to the teachings of Rodriguez with the motivation of preventing delamination. Furthermore, a variable which achieves a recognized result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation, because "obvious to try" is not a valid rationale for an obviousness finding. In KSR International Co. v. Teleflex Inc., 550 U.S. 398 (2007), Response to Arguments Applicant’s arguments with respect to claim(s) 13-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection. Applicant’s arguments, see Remarks, filed 07/06/26, with respect to the rejection(s) of claim(s) 20-27 under 35 U.S.C. 102(a)(1) Seng et. al. (US PGPub 2014/0138833, hereinafter referred to as “Seng”) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Rodriguez et al. (US PGPub 2018/0204786 hereinafter referred to as “Rodriguez”). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 September 19, 2026
Read full office action

Prosecution Timeline

Show 1 earlier event
Mar 03, 2025
Non-Final Rejection mailed — §102, §103
Jun 02, 2025
Response Filed
Oct 29, 2025
Final Rejection mailed — §102, §103
Jan 28, 2026
Request for Continued Examination
Feb 03, 2026
Response after Non-Final Action
Apr 07, 2026
Non-Final Rejection mailed — §102, §103
Jul 06, 2026
Response Filed
Sep 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
86%
Grant Probability
50%
With Interview (-36.2%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 977 resolved cases by this examiner. Grant probability derived from career allowance rate.

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