DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Watanabe et al. (US 2017/0047296 A1) in view of Yang et al. (PG Pub. No. US 2022/0384326 A1).
Regarding claim 10, Watanabe teaches a package substrate (¶ 0075 & figs. 1, 46 among others: 1), comprising:
a substrate (¶¶ 0076, 0168: 2 and/or 20) having an upper board surface and a lower board surface (¶ 0170: top and bottom surfaces 2a, 2b), wherein a plurality of scribe line regions (¶ 0169: dicing lines 20c) are arranged on the upper board surface to define a plurality of die-bonding regions and to separate any adjacent two of the plurality of die-bonding regions (fig. 17: 20c arranged on surface 2a to define and separate die regions 20a including bonding leads 2f), and each of the plurality of die-bonding regions has at least one thru-hole penetrating the upper board surface or the lower board surface (¶ 0079 & fig. 19: wirings 2d disposed in through holes penetrating at least one surface 2a or 2b) and includes:
a substrate conductor (¶ 0077: wirings 2d) disposed in the through hole (fig. 19: 2d includes conductive material disposed in through holes penetrating at least one surface 2a or 2b), wherein the substrate conductor has an upper conductive end (¶ 0073: 2f on upper surface 2a) and a lower conductive end (¶ 0073: 2g on lower surface 2b) that are exposed at the upper board surface and the lower board surface of the substrate, respectively (fig. 19: 2f and 2g exposed on respective upper and lower surfaces 2a and 2b); and
a core material body (¶ 0077: 2e) disposed in the substrate and adjacent to the substrate conductor (fig. 19: 2e disposed in 2/20 and adjacent to 2d); and
a plurality of chips (¶ 0085: MC1-MC4) fixedly disposed in the plurality die-bonding regions, respectively (fig. 42: MC1-MC4 fixedly disposed in regions 20a), wherein each of the plurality of chips is electrically connected to the corresponding substrate conductor through the upper conductive end thereof (fig. 42: MC1-MC4 electrically connected to portions of 2d on surface 2a);
wherein the plurality of scribe line regions define a plurality of scribe lines (¶ 0169), and a dicing process is performed by dicing along the plurality of scribe lines to form a plurality of chip assemblies (since claim 10 is directed to a product, the claim is limited by structure. Therefore, the process limitation ‘a dicing process is performed…’ does not carry patentable weight).
Watanabe further teaches an embodiment (fig. 31 among others) including substrate conductors penetrating from an upper substrate surface to a lower substrate surface (¶ 0238 & fig. 30: 3TSV, AM4 penetrate from upper surface to lower surface of substrate WH).
Watanabe does not explicitly teach the embodiment of fig. 46 includes the through hole penetrating from the upper board surface to the lower board surface, the substrate conductor entirely disposed in the through hole, or the core material body entirely disposed in the thru-hole and arranged inside of the substrate conductor, wherein the substrate and the substrate conductor are jointly connected to an entirety of a first surface of the core material body arranged adjacent to the upper board surface, and a second surface of the core material body arranged adjacent to the lower board surface is partially connected to the substrate conductor.
Yang teaches a substrate (fig. 24A) having an upper surface and a lower surface (upper and lower surfaces including elements 668), a plurality of die-bonding regions (¶ 0326-0327: substrate includes regions for bonding IC chips) having thru-holes (¶ 0327: 969) penetrating from the upper surface to the lower surface (fig. 24A: 969 penetrates from upper to lower surface PCB comprising core layer 661), a substrate conductor (¶ 0328: 467) entirely disposed in the thru-hole (fig. 24B: 467 entirely disposed in 969), and a core material body (¶ 0099: 907) entirely disposed in the thru-hole and arranged inside of the substrate conductor (fig. 24B: 908 entirely disposed in 969 and arranged inside 467), wherein the substrate and the substrate conductor are jointly connected to an entirety of a first surface of the core material body arranged adjacent to the upper board surface (fig. 24B: substrate of fig. 24A and 467 jointly connected to an entirety of a first surface of the 661 arranged adjacent to the upper board surface), and a second surface of the core material body arranged adjacent to the lower board surface is partially connected to the substrate conductor (fig. 24B: second surface of 24B arranged adjacent to lower surface of board of fig. 24A at least partially connected to 467).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the substrate conductor of Watanabe with the structure and material of Yang, as a means to provide vertical connection to transmit signals or clocks or deliver power or ground in a vertical direction (Yang, ¶ 0093) and allowing smaller multi-chip packages (Yang, ¶ 0003). Furthermore, the through-hole of Yang penetrating from the upper board surface to the lower board surface of Watanabe can be formed by a single process, improving manufacturing efficiency.
Regarding claim 11, Watanabe in view of Wu teaches the package substrate according to claim 10, wherein a plurality of marking regions (Watanabe, ¶ 0178: AMS) that surrounds the plurality of die-bonding regions are further arranged on the upper board surface for disposing a plurality of alignment marks on the substrate (Watanabe, fig. 17: AMS disposed on surface 2a surrounding plurality of regions 20a), so as to locate the plurality of die- bonding regions during a die bonding process and allow the plurality of chips to be disposed in the die-bonding regions, respectively (Watanabe, ¶ 0180: AMS provides detection of device regions 20a).
Regarding claim 12, Watanabe in view of Yang teaches the package substrate according to claim 11, wherein each of the marking regions is provided with a marking conductor (Watanabe, ¶ 018: AMS formed of wiring material), which has an upper marking end exposed at the upper board surface of the substrate to serve as one of the plurality of alignment marks (Watanabe, fig. 17: upper end of AMS exposed at upper board surface).
Regarding claim 13, Watanabe in view of Yang teaches the package substrate according to claim 12, wherein the plurality of dicing lines partially overlap the plurality of marking regions (Watanabe, fig. 17: 20c overlaps edge of marking region 20b), and the marking conductor in each of the plurality of marking regions is not disposed in an overlapping portion where the plurality of scribe lines overlap with the plurality of marking regions (Watanabe, fig. 17: AMS not disposed in overlapping/edge region).
Regarding claim 14, Watanabe in view of Yang teaches the package substrate according to claim 12, wherein a redundant region is further arranged on the upper board surface of the substrate to surround the plurality of die-bonding regions and the plurality of marking regions (Watanabe, fig. 17: outermost region of 20 surround AMS and 20a/20c).
Claims 16 is rejected under 35 U.S.C. 103 as being unpatentable over Watanabe in view of Yang as applied to claim 14 above, and further in view of Ogawa et al. (PG Pub. No. US 2006/0192287 A1).
Regarding claim 16, Watanabe in view of Yang teaches the package substrate according to claim 14, comprising a redundant region (Watanabe, fig. 17 among others: portion of region 20b absent AMS structure), wherein the plurality of scribe line regions are partially overlapped with the redundant region (Watanabe, fig. 17: edge portions of 20c overlap with inner perimeter of 20b).
Watanabe in view of Yang does not teach wherein the redundant region is provided with a redundant electrical conductor, and the redundant conductor is not disposed in an overlapping portion where the plurality of scribe lines overlap the redundant region.
Ogawa teaches a package substrate (¶ 0050 & fig. 1 among others) including a redundant region (peripheral region 202 of fig. 4a and/or 4b) provided with a redundant electrical conductor (¶ 0082: pattern units 301 disposed in peripheral region 202).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the package substrate of Watanabe in view of Yang with a redundant electrical conductor, as a means to suppress a warpage of the package substrate (Ogawa, ¶ 0023).
Furthermore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to not dispose the redundant electrical connector in an overlapping portion where the plurality of scribe lines overlap the redundant region, as a means to avoid pattern defects and/or debris during a package dividing step.
Since all the claimed elements were known in the prior art, and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, the combination would have yielded nothing more than predictable results to one of ordinary skill in the art. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 538, 416, 82 USPQ2d 1385, 1395 (2007); Sakraida v. AG Pro, Inc., 425 U.S. 273, 282, 189 USPQ 449, 453 (1976); Anderson' s-Black Rock, Inc. v. Pavement Salvage Co., 396 U.S. 57, 62-63, 163 USPQ 673, 675 (1969); Great Atlantic & P. Tea Co. v. Supermarket Equip. Corp., 340 U.S. 147, 152, 87 USPQ 303, 306 (1950). See MPEP § 2143.02.
Regarding claim 17, Watanabe teaches a package substrate (figs. 1, 22 and 46 among others), comprising:
a substrate (2, 20) having an upper board surface and a lower board surface (fig. 22: 20 includes upper surface 2a and lower surface 2b), wherein a plurality of scribe line regions (¶ 0169: 20c) are arranged on the upper board surface to define a plurality of die-bonding regions and to separate any adjacent two of the plurality of die-bonding regions (fig. 17: 20c arranged on surface 2a to define and separate die bonding regions 20a), and each of the plurality of die-bonding regions has a thru-hole penetrating the substrate (fig. 22 among others: at least portions 2e include penetrating holes comprising conductors 2d) and includes:
a substrate conductor (¶ 0077: 2d) disposed in the thru-hole (fig. 22: 2d at least partially penetrates portions 2e), wherein the substrate conductor has an upper conductive end and a lower conductive end (fig. 19: 2d includes upper and lower ends); and
a core material body (¶ 0078: 2e) disposed in the thru-hole and adjacent to the substrate conductor (fig. 19: portions of 2e disposed in through-holed of 2e and adjacent to 2d); and
a plurality of chips (¶ 0085: LC and/or MC1-MC4) fixedly disposed in the plurality die-bonding regions (fig. 46: LC/MC fixedly disposed in regions 20a), respectively,
wherein each of the plurality of chips is electrically connected to the corresponding substrate conductor through the upper conductive end thereof (fig. 46: each LC/MC electrically connected to upper end of 2d);
wherein the plurality of scribe line regions define a plurality of scribe lines that do not overlap with metal conductors (figs. 17, 19 among others: 20c do not overlap at least metal conductors 2d), and a dicing process is performed by dicing along the plurality of scribe lines to form a plurality of chip assemblies (since claim 17 is directed to a product, the claim is limited by structure. Therefore, the process limitation ‘a dicing process is performed…’ does not carry patentable weight).
Watanabe further teaches an embodiment (fig. 31 among others) including substrate conductors penetrating from an upper substrate surface to a lower substrate surface (¶ 0238 & fig. 30: 3TSV, AM4 penetrate from upper surface to lower surface of substrate WH).
Watanabe does not teach the through hole(s) of fig. 46 penetrate from the upper board surface to the lower board surface, such that the conductive ends are exposed at the upper board surface and the lower board surface of the substrate, the substrate conductor entirely disposed in the thru-hole, and the core material body entirely disposed in the thru-hole and arranged inside of the substrate conductor.
Yang teaches a substrate (fig. 24A) having an upper surface and a lower surface (fig. 24A among others: upper and lower surfaces comprising elements 668), a thru-hole (¶ 0327: 969) penetrating from the upper board surface to the lower board surface (fig. 24B among others: 969 penetrates from upper surface to lower surface of the substrate of fig. 24A), a substrate conductor (¶¶ 0097, 0103: 467 and/or 907) entirely disposed in the thru-hole (fig. 24B: 467/907 entire disposed in 969), and a core material body (¶ 0099: 901 and/or 908) entirely disposed in the thru-hole and arranged inside of the substrate conductor (fig. 24B among others: 901/908 entirely disposed in 969 and arranged inside of 467/907).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the substrate conductor of Watanabe with the structure and material of Yang, as a means to provide vertical connection to transmit signals or clocks or deliver power or ground in a vertical direction (Yang, ¶ 0093) and allowing smaller multi-chip packages (Yang, ¶ 0003). Furthermore, the through-hole of Yang penetrating from the upper board surface to the lower board surface of Watanabe can be formed by a single process, improving manufacturing efficiency.
Response to Arguments
Applicant’s arguments with respect to claims 10-14 and 16-17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shimizu et al. (PG Pub. No. US 2015/0245473 A1) teaches a substrate conductor (¶ 0030: 21) entirely disposed in a substrate thru-hole (fig. 4B: 21 entirely disposed in through hole 20X of substrate 20), and a core material body (¶ 0030: resin 22) entirely disposed in the thru-hole and arranged inside of the substrate conductor (fig. 4B: 22 entirely disposed in 20X and arranged inside 21).
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/BRIAN TURNER/Examiner, Art Unit 2818
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