DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 7/22/25 has been entered.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 7/22/25, 9//09/25, 10/09/25, and 11/07/25. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US PGPub 2013/0161757, hereinafter referred to as “Huang”).
Huang discloses the semiconductor device as claimed. See figures 3-4i and corresponding text, where Huang teaches, in claim 1, a structure comprising a semiconductor substrate (1); a first semiconductor layer (3) on the semiconductor substrate (1), the first semiconductor layer (3) comprising a porous semiconductor material ([0031]); a first cavity (see Fig. 4c and [0032]) in the porous semiconductor material (3) of the first semiconductor layer (3); a second semiconductor layer (5) inside the first cavity (see Fig. 4c and [0032]) in the first semiconductor layer (3), the second semiconductor layer (5) comprising a single-crystal semiconductor material ([0033]); and a first device structure (6, 7, 8, 9) including a first doped region (8, 9) in the second semiconductor layer (5).
Huang teaches, in claim 2, wherein the first device structure is a field-effect transistor, and the first doped region is a source or a drain of the field-effect transistor ([0028]).
Huang teaches, in claim 3, wherein the first semiconductor layer abuts the second semiconductor layer (figure 3; [0028]).
Huang teaches, in claim 4, wherein the first semiconductor layer surrounds the second semiconductor layer on multiple sides (figure 3; [0028]).
Huang teaches, in claim 5, wherein the porous semiconductor material of the first semiconductor layer is positioned between the second semiconductor layer and the semiconductor substrate (figure 3; [0032]).
Huang teaches, in claim 6, wherein the porous semiconductor material is porous silicon, and the single-crystal semiconductor material of the second semiconductor layer is single-crystal silicon (figure 3; [0032]).
Huang teaches, in claim 7, further comprising:
a second cavity in the porous semiconductor material of the first semiconductor layer, the second cavity spaced in a lateral direction from the first cavity; and
a third semiconductor layer in the second cavity in the first semiconductor layer, the third semiconductor layer comprising the single-crystal semiconductor material (see Fig. 3 and [0032]).
Huang teaches, in claim 8, further comprising: a second device structure including a second doped region in the third semiconductor layer (figure 3; [0028]).
Huang teaches, in claim 9, wherein the first semiconductor layer includes a portion of the porous semiconductor material that is positioned in the lateral direction between the second semiconductor layer and the third semiconductor layer (figure 3; [0032]).
Huang teaches, in claim 10, wherein the porous semiconductor material of the first semiconductor layer is positioned between the second semiconductor layer and the semiconductor substrate, and the porous semiconductor material of the first semiconductor layer is positioned between the third semiconductor layer and the semiconductor substrate (see Fig. 4c and [0032]).
Huang teaches, in claim 11, wherein the portion of the first semiconductor layer abuts the second semiconductor layer, and the portion of the first semiconductor layer abuts the third semiconductor layer (see Fig. 3 and [0028]).
Huang teaches, in claim 12, wherein the porous semiconductor material of the first semiconductor layer is positioned between the second semiconductor layer and the semiconductor substrate, and the porous semiconductor material of the first semiconductor layer is positioned between the third semiconductor layer and the semiconductor substrate.
Huang teaches, in claim 13, further comprising:
a shallow trench isolation region (4) in the first semiconductor layer, the shallow trench isolation region comprising a dielectric material, and the shallow trench isolation region positioned in the lateral direction between the second semiconductor layer and the third semiconductor layer (figure 3; [0028]).
Huang teaches, in claim 14, wherein the first semiconductor layer has a first electrical resistivity, and further comprising:
a high-resistivity region in the first semiconductor layer, the high-resistivity region having a second electrical resistivity greater than the first electrical resistivity of the first semiconductor layer, and the high-resistivity region positioned in the lateral direction between the second semiconductor layer and the third semiconductor layer (figure 3; [0021]).
Huang teaches, in claim 15, wherein the semiconductor substrate has a first electrical resistivity, and the first semiconductor layer has a second electrical resistivity that is greater than the first electrical resistivity of the semiconductor substrate (figure 3; [0021]).
Huang teaches, in claim 16, wherein the first semiconductor layer is thicker than the second semiconductor layer (figure 3; [0028]).
Huang teaches, in claim 17, wherein the first device structure including a second doped region in the second semiconductor layer (figure 3; [0028]).
Huang teaches, in claim 18, wherein the first device structure includes a gate electrode that overlaps with a portion of the second semiconductor layer positioned between the first doped region and the second doped region (figure 3; [0028]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 January 7, 2026