Prosecution Insights
Last updated: April 19, 2026
Application No. 17/942,479

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §103
Filed
Sep 12, 2022
Examiner
BRADFORD, PETER
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
84%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
586 granted / 733 resolved
+11.9% vs TC avg
Minimal +4% lift
Without
With
+4.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
42 currently pending
Career history
775
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
41.1%
+1.1% vs TC avg
§102
24.3%
-15.7% vs TC avg
§112
32.5%
-7.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 733 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The amended title overcomes the previous objection. The claim amendments overcome the previous objections. See the new rejections below. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 8, 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee, KR 2018-0003253 A, in view of Choi, US 2019/0181199 A1. Claim 1: Lee discloses an insulating layer (237) disposed on a base layer (210); a first lower electrode (242 (FIG. 2) of a pixel 116 (FIG. 1)) disposed on the insulating layer; a second lower electrode (242 of a different pixel 116) disposed on the insulating layer and spaced apart from the first lower electrode; a pixel definition layer (251/351) disposed on the insulating layer and including pixel openings exposing at least a portion of each of the first lower electrode and the second lower electrode (FIG. 2 or FIG. 3), the pixel definition layer is a light blocking material; “The bank 251 can have an optical density (OD) indicating the degree of blocking of light at 4 or less at a thickness of 3µm of the bank 251. Optical density (OD) is measured in OD meter (OD meter).” [0085]. Note that an optical density of 4 blocks 99.99% of light. PNG media_image1.png 364 460 media_image1.png Greyscale Lee does not disclose the claimed sacrificial layer. However, this was known in the art. See Choi, which discloses: and a sacrificial layer (STP) disposed between the pixel definition layer (142) and the insulating layer and comprising first side surfaces defining sacrificial openings corresponding to the pixel openings (FIG. 4), wherein the first side surfaces are overlapped by the pixel definition layer in a plan view, and the pixel definition layer contacts and covers the first side surfaces in a cross-sectional view (Choi FIG. 7). PNG media_image2.png 317 813 media_image2.png Greyscale Note: the pixel of FIG. 7 has here been duplicated to show multiple pixels. The sacrificial layer STP functions as an etch stop layer to allow for the formation of grooves BG, which prevents leakage current ([0066]). It would have been obvious to have had the sacrificial layer STP in Lee for this reason. Claim 2: the sacrificial layer comprises: a first sacrificial pattern (left) adjacent to the first lower electrode; and a second sacrificial pattern (right) adjacent to the second lower electrode and spaced apart from the first sacrificial pattern, and the sacrificial openings comprise: a first sacrificial opening defined in the first sacrificial pattern and exposing the at least the portion of the first lower electrode; and a second sacrificial opening defined in the second sacrificial pattern and exposing the at least the portion of the second lower electrode. See the annotated figure above. Claim 3: the pixel definition layer comprises: a first pixel definition pattern (BN, left) overlapping the first sacrificial pattern in the plan view; and a second pixel definition pattern (BN, right) overlapping the second sacrificial pattern in the plan view and spaced apart from the first pixel definition pattern. Claim 4: Choi discloses the first sacrificial pattern comprises a first side surface and a second side surface opposing the first side surface of the first sacrificial pattern, and the second side surface of the first sacrificial pattern is spaced farther from the first lower electrode than the first side surface of the first sacrificial pattern, the first side surface of the first sacrificial pattern defining the first sacrificial opening, the second sacrificial pattern comprises a first side surface and a second side surface opposing the first side surface of the second sacrificial pattern, and the second side surface of the second sacrificial pattern and is spaced farther from the second lower electrode than the first side surface of the second sacrificial pattern, the first side surface of the second sacrificial pattern defining the second sacrificial opening, the second side surface of the first sacrificial pattern is overlapped by the first pixel definition pattern in the plan view, the second side surface of the second sacrificial pattern is overlapped by the second pixel definition pattern in the plan view, and at least a portion of the second side surface of the first sacrificial pattern faces at least a portion of the second side surface of the second sacrificial pattern. PNG media_image3.png 319 813 media_image3.png Greyscale Claim 5: Choi discloses a cover layer (OL) overlapping a separation space between the first pixel definition pattern and the second pixel definition pattern in the plan view and comprising an organic material. Claim 8: the pixel definition layer has an optical density equal to or greater than about 1.0 (Lee, [0085]). Claim 10: at least a portion of the sacrificial layer overlaps at least a portion of an end area of each of the first lower electrode and the second lower electrode in the plan view (Choi FIG. 7). Claim 11: Lee discloses a first light emitting element (116, left) comprising a lower electrode (242), an upper electrode (246), and a light emitting layer (244) disposed between the lower electrode and the upper electrode; a second light emitting element (116, right) comprising a lower electrode (242), an upper electrode (246), and a light emitting layer (244) disposed between the lower electrode and the upper electrode; transistors (220) electrically connected to the lower electrode of the first light emitting element and the lower electrode of the second light emitting element; a first pixel definition pattern (251 for left pixel) including a first pixel opening through which at least a portion of the lower electrode of the first light emitting element is exposed; a second pixel definition pattern (251 for right pixel) including a second pixel opening through which at least a portion of the lower electrode of the second light emitting element is exposed; wherein each of the first pixel definition pattern and the second pixel definition pattern is a light blocking material. “The bank 251 can have an optical density (OD) indicating the degree of blocking of light at 4 or less at a thickness of 3µm of the bank 251. Optical density (OD) is measured in OD meter (OD meter).” [0085]. Note that an optical density of 4 blocks 99.99% of light. Lee does not disclose the claimed sacrificial patterns, but these were known in the art. See Choi, which discloses a first sacrificial pattern (STP, left) overlapped by the first pixel definition pattern in a plan view; and a second sacrificial pattern (STP, right) overlapped by the second pixel definition pattern and spaced apart from the first sacrificial pattern in the plan view, wherein the transistors do not overlap an area between the first pixel definition pattern and the second pixel definition pattern, in the plan view; wherein, in a cross-sectional view, the first pixel definition pattern covers and contacts a side surface of the first sacrificial pattern and the second pixel definition pattern covers and contacts a side surface of the second sacrificial pattern (FIG. 7). PNG media_image4.png 275 502 media_image4.png Greyscale The sacrificial layer STP functions as an etch stop layer to allow for the formation of grooves BG, which prevents leakage current ([0066]). It would have been obvious to have had the sacrificial layer STP in Lee for this reason. Claim 13: Choi discloses a cover layer (OL) overlapping a separation space between the first pixel definition pattern and the second pixel definition pattern in the plan view. Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Choi and SoJung Lee, US 2021/0119183 A1. Claim 5: SoJung Lee discloses a layer 131 101 covering a separation space between the first pixel definition pattern and the second pixel definition pattern in the plan view and comprising an organic material. It would have been obvious to have used this as a way to direct the light emitted from the pixel. Claim 6: the material of layer 131 is reflective (SoJung Lee FIG. 3), and thus comprises a light blocking material. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Choi and in evidence of Swinnen, US 2008/0166525 A1. Choi discloses that sacrificial layer can be silicon oxide ([0015]) and the electrode can be copper ([0063]). There are echants that etch silicon oxide faster than copper. See e.g. Swinnen [0050]. Additionally, there are other etchants that are selective to these and other materials that these two layers can be made of. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER BRADFORD whose telephone number is (571)270-1596. The examiner can normally be reached 10:30-6:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469.295.9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER BRADFORD/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Sep 12, 2022
Application Filed
Sep 04, 2025
Non-Final Rejection — §103
Nov 07, 2025
Interview Requested
Nov 13, 2025
Examiner Interview Summary
Nov 13, 2025
Applicant Interview (Telephonic)
Dec 08, 2025
Response Filed
Mar 21, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
84%
With Interview (+4.1%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 733 resolved cases by this examiner. Grant probability derived from career allow rate.

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