Prosecution Insights
Last updated: April 19, 2026
Application No. 17/944,511

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME

Non-Final OA §103§112
Filed
Sep 14, 2022
Examiner
CULBERT, CHRISTOPHER A
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Display Co., Ltd.
OA Round
2 (Non-Final)
41%
Grant Probability
Moderate
2-3
OA Rounds
3y 8m
To Grant
46%
With Interview

Examiner Intelligence

Grants 41% of resolved cases
41%
Career Allow Rate
137 granted / 333 resolved
-26.9% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
81 currently pending
Career history
414
Total Applications
across all art units

Statute-Specific Performance

§103
55.8%
+15.8% vs TC avg
§102
20.9%
-19.1% vs TC avg
§112
22.1%
-17.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 333 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office action is in response to Amendments filed 11/18/2025. Claim Rejections - 35 USC § 112 Claims 5-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 5 requires that the one-side sub-semiconductor layer be between the nanoporous layer and the main semiconductor layer. This feature was not described in the Application which shows that the main semiconductor layer and the nanoporous layer are in direct contact (see Applicant’s Fig. 5). Claims 6-15 depend from claim 5 and are, therefore, also rejected. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0013766 A1) in view of Zhu et al. (US 2020/0227255 A1). Regarding claim 1, Kim discloses a display device (Fig. 7) comprising: first banks (BNK1 and BNK2) spaced apart from one another and disposed on a substrate (SUB); a first electrode and a second electrode (CNE2 and CNE2) disposed on the respective first banks to cover the respective first banks, the first electrode and the second electrode being spaced apart from each other; and a light-emitting element (LD) disposed between the first electrode and the second electrode. Kim does not disclose the specific structure of the light-emitting element as claimed. Zhu, in the same field of endeavor, discloses a light-emitting element (800 in Fig. 8A) comprising: an active layer (“Active Layers”); a first semiconductor layer (combination of porous GaN DBR and n-GaN); and a second semiconductor layer (p-GaN) disposed between the active layer and first electrode (top electrode), and the first semiconductor layer comprises: a main semiconductor layer (combination of n-GaN and Porous GaN DBR); and a nanoporous layer (Porous GaN DBR) disposed in the main semiconductor layer (as it is a part of the main semiconductor layer, it is disposed in the main semiconductor layer). As such, Kim differs from the claimed invention by the substitution of a light-emitting element with a nanoporous structure with a light-emitting element without a nanoporous structure. However, light-emitting elements with a nanoporous structure and the corresponding function was known in the art (see discussion of Zhu, above). As such, it would have been obvious to one having ordinary skill in the art before the Application's effective filing date to have substituted the known light-emitting element with a nanoporous structure as taught by Zhu for the light-emitting element of Kim and the results of the substitution would have been predictable. (see MPEP § 2143(I)(B)). Regarding claim 2, Kim in view of Zhu discloses the display device of claim 1, as discussed above. Zhu further discloses wherein the main semiconductor layer directly contacts an outer surface of the nanoporous layer (see Fig. 8A). Regarding claim 3, Kim in view of Zhu discloses the display device of claim 2, as discussed above. Zhu further discloses wherein the main semiconductor layer includes GaN doped with n-type Si (¶ 0044). Regarding claim 4, Kim in view of Zhu further discloses weherein the second semiconductor layer includes GaN doped with p-type dopant (see Fig. 8A). Response to Arguments Applicant’s arguments have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of a different mapping of Kim in view of Zhu, as discussed above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A CULBERT/Examiner, Art Unit 2815
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Prosecution Timeline

Sep 14, 2022
Application Filed
Aug 25, 2025
Non-Final Rejection — §103, §112
Nov 18, 2025
Response Filed
Mar 01, 2026
Non-Final Rejection — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MICRO-LED STRUCTURE AND MICRO-LED CHIP INCLUDING SAME
2y 5m to grant Granted Dec 16, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
41%
Grant Probability
46%
With Interview (+4.4%)
3y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 333 resolved cases by this examiner. Grant probability derived from career allow rate.

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