DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant has not specifically confirmed the election of claims 1-13 and 20-24 in the reply filed on 1/2/2026, but has cancelled claims 1-2 and has indicated that “Claims 3 to 13 and 20 to 24 are now in the application” and that “Claims 14 to 19 and 25 to 26 were previously withdrawn”. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
2nd Non-Final Rejection - Reasons
New rejections are being presented in this office action that are not the result of applicant’s amendments to claims. As such, the office action is a non-final rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 3-5 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticpated by Lee (US 20140182911), hereinafter Lee.
Regarding claim 3, Lee (US 20140182911) (refer to Figure 2F) teaches an embedded die package comprising a laminated body (para 31 describes "insulating layers 120 may be laminated on upper and lower surfaces of the core 110 in which the electronic component 200 is embedded"), and a die comprising a semiconductor device (200, described as “electronic component 200” which “may be “an IC, a semiconductor chip” in para 29) embedded within the laminated body, wherein:
the die comprises a patterned layer of conductive metallization (202, described as "positive and negative external electrodes 202" in para 30) on a front-side of the die providing electrical contact areas (i.e. “external electrodes 202” describe in para 30) of the semiconductor device (200); and
the laminated body comprises a layer stack comprising at least one dielectric layer (120, described as "insulating layers 120” in para 31) that embeds the die (200) and a first conductive layer patterned (conductive layer pattern that forms 130) to define interconnect areas (130, described as “external circuit pattern 130”);
a plurality of electrically conductive micro-vias (121 and 131 – see para 35; also see Figure 2F) interconnecting interconnect areas (130) of the first conductive layer and electrical contact areas (202) of the semiconductor device (200);
wherein a surface of the conductive metallization of said electrical contact areas (202) of the semiconductor (200) comprises first regions (202b, described as " low roughness surface 202b” of “the external electrode 202" in para 34) on which conductive micro-vias (121 and 131) are formed (see Figure 2F), and
second regions (202a, described as “rough surface 202a” in para 32; see Figure 2F) embedded by package dielectric (120), the second regions having surface characteristics different from surface characteristics of the first regions (for example, para 33 teaches that 202b have lower surface roughness compared to 202a).
Regarding claim 4, Lee (refer to Figure 2F) teaches the embedded die package of claim 3, wherein a first surface roughness of said first regions (202b) is less than (see para 33) a second surface roughness of said second regions (202a).
Regarding claim 5, Lee (refer to Figure 2F) teaches the embedded die package of claim 3, but does not specifically state that “for a specified laser wavelength range for laser drilling, an optical absorption of said first regions is less than an optical absorption of said second regions”. However, given that said first regions (202b) that have lower surface roughness; i.e. they are relatively more polished, that said second regions (202b), it follows that first regions will reflect a larger portion of the incident light of laser due to limited scattering. The above mentioned scattering is disclosed by Lee as "laser scattered reflection is made from the rough surface of the external electrode, resulting in defective processing of vias having an irregular shape rather than having a uniform size and generation of voids on the bonding surface with the external electrode 202 when the insulating layer 120 is laminated" (see para 45). From the above, it follows that for a specified laser wavelength range for laser drilling, an optical absorption of said first regions (i.e. regions of relatively lower surface roughness) is less than an optical absorption of said second regions (i.e. regions of relatively higher surface roughness).
Regarding claim 20, Lee (refer to Figure 2F) teaches a semiconductor die (200, described as “electronic component 200” which “may be “an IC, a semiconductor chip” in para 29) comprising a plurality of contact pads (202, described as "positive and negative external electrodes 202" in para 30) configured for embedded die packaging (para 31) wherein conductive interconnects to said plurality of contact pads are to be provided by conductive microvias (121 and 131 – see para 35; also see Figure 2F), a surface of each of said plurality of contact pads having a surface treatment to define target areas (202b) for laser drilling of microvias (para 33; also see para 38).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 6-7 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ikeda (US 2020/0389969), hereinafter Ikeda.
Regarding claim 6, Lee (refer to Figure 2F) teaches the embedded die package of claim 3, but does not further teach “an area of a protective masking layer provided on said first regions of the surface of the electrical contact areas of the semiconductor device at a base of each micro-via”. Ikeda teaches that it is known in the art that a region of a conductor of a conductive line may be roughened to a target surface roughness by etching (para 74) and further that it is also known to selectively etch by forming an area of protective masking layer (described as “etching mask” in para 73) on regions are to be protected from etching (para 73). It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that said first regions (which are not be roughened) at a base of each micro-via to be protected during a roughening process such as etching by a mask (as explained above); i,e, “an area of a protective masking layer provided on said first regions of the surface of the electrical contact areas of the semiconductor device at a base of each micro-via”. The ordinary artisan would have been motivated to modify Lee for at least the purpose of preventing roughening (which would cause an increase in surface roughness) of a region of the micro-via used for forming high speed interconnections or for grounding, such as on “said first regions of the surface of the electrical contact areas of the semiconductor device at a base of each micro-via”, thus enabling avoidance of undesirable scattering losses and impeded signal transmission for high speed signals and ground plane connections at micro-via base, while still providing good adhesion for the remainder of the interconnect (para 31 of Harkness).
Regarding claim 7, Lee (refer to Figure 2F) teaches the embedded die package of claim 3, but does not further teach “an area of a protective masking layer provided on said first regions surrounding a base of the conductive microvias”. Ikeda teaches that it is known in the art that a region of a conductor of a conductive line may be roughened to a target surface roughness by etching (para 74) and further that it is also known to selectively etch by forming an area of protective masking layer (described as “etching mask” in para 73) on regions are to be protected from etching (para 73). It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that said first regions (which are not be roughened) at a base of each of the conductive micro-vias are protected during a roughening process such as etching by a mask (as explained above); i,e, “an area of a protective masking layer provided on said first regions surrounding a base of the conductive microvias”. The ordinary artisan would have been motivated to modify Lee for at least the purpose of preventing roughening (which would cause an increase in surface roughness) of a region of the micro-via used for forming high speed interconnections or for grounding, such as on “on said first regions surrounding a base of the conductive microvias”, thus enabling avoidance of undesirable scattering losses and impeded signal transmission for high speed signals and ground plane connections at micro-via base, while still providing good adhesion for the remainder of the interconnect (para 31 of Harkness).
Regarding claim 9, Lee (refer to Figure 2F) teaches the embedded die package of claim 6, but does not teach that “the protective masking layer comprises a material that resistant to surface treatments for roughening said second regions of the electrical contact areas”. Ikeda, as applied to claim 6 above, not only teaches the protective masking layer (described as “etching mask” in para 73), but also that a material like polyimide performs the protective function of a mask (para 86). It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that the protective masking layer can perform it’s intended function during a process like etching; i.e. wherein “the protective masking layer comprises a material that resistant to surface treatments for roughening said second regions of the electrical contact areas”. The ordinary artisan would have been motivated to modify Lee for at least the purpose of using the protective masking layer as photosensitive mask material for an etching process for roughening (para 73 of Ikeda); also see rejection of claim 6.
Regarding claims 10-11, Lee (refer to Figure 2F) teaches the embedded die package of claim 6, but does not teach that “the protective masking layer is a polymer dielectric which is resistant to surface roughening treatments for roughening said second regions of the electrical contact areas” (as recited in claim 10), and further wherein “the polymer dielectric comprises a polyimide” (as recited in claim 11). Ikeda, as applied to claim 6 above, not only teaches the protective masking layer (described as “etching mask” in para 73), but also that a material like polyimide performs the protective function of a mask (para 86). It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that the protective masking layer can perform it’s intended function during a process like etching by using a known material like polyimide; i.e. wherein “the protective masking layer is a polymer dielectric which is resistant to surface roughening treatments for roughening said second regions of the electrical contact areas” (as recited in claim 10), and further wherein “the polymer dielectric comprises a polyimide” (as recited in claim 11). The ordinary artisan would have been motivated to modify Lee for at least the purpose of using the protective masking layer as mask material for an etching process for roughening (para 73 of Ikeda) using a material like polyimide that is photosensitive and enables forming an appropriate pattern by performing exposure and development (para 86 of Ikeda); also see rejection of claim 6.
Regarding claims 12-13, Lee (refer to Figure 2F) teaches the embedded die package of claim 3, but does not teach “an area of a protective masking layer is provided on a surface of the electrical contact areas of the semiconductor device within each micro-via” (as recited in claim 12), and further wherein “said area of the protective masking layer comprises a layer of gold” (as recited in claim 13). Ikeda teaches that it is known in the art that a region of a conductor of a conductive line may be roughened to a target surface roughness by etching (para 74) and further that it is also known to selectively etch by forming an area of protective masking layer (described as “etching mask” in para 73) on regions are to be protected from etching (para 73) and that in some locations, an area of the protective masking layer may comprise a layer of gold (para 86, especially last sentence). It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that a surface of the electrical contact areas of the semiconductor device within each micro-via (which are not be roughened) are provided with a protective masking layer to protect them during a roughening process such as etching by a mask (as explained above) and a film comprising gold surface protective film may also be provided in the area for protection (para 86 of Ikeda); i,e, “an area of a protective masking layer is provided on a surface of the electrical contact areas of the semiconductor device within each micro-via” (as recited in claim 12), and further wherein “said area of the protective masking layer comprises a layer of gold” (as recited in claim 13). The ordinary artisan would have been motivated to modify Lee for at least the purpose of preventing roughening (which would cause an increase in surface roughness) of a region of the micro-via used for forming high speed interconnections or for grounding (para 31 of Harkness) while also protecting areas in the same region that may be exposed by using a film comprising gold (para 86 of Ikeda), thus enabling good soldering (para 86 of Ikeda) in subsequent processing while also avoiding undesirable scattering losses and impeded signal transmission for high speed signals and ground plane connections at micro-via base, while still providing good adhesion for the remainder of the interconnect (para 31 of Harkness); also see rejection of claim 3.
Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Wang (US 20180366436), hereinafter Wang.
Regarding claim 21, Lee (refer to Figure 2F) teaches the semiconductor die of claim 20, but does not teach wherein “the plurality of contact pads are provided by a conductive metal redistribution layer (RDL) and the surface treatment comprises a protective layer of a dielectric material”. Wang (US 20180366436) also teaches an embedded die packaging structure (see Figure 1-13) comprising a die (103, para 20), conductive microvias (143, described as "through-mold vias 143" in para 50; also see para 52), a conductive metal redistribution layer or RDL (145, described as “RDL 145”, which may comprise “metal layer 147” and “dielectric layer 148” – para 55 – see Figure 1-13) and 147 forms contact pads to which 143 connects (para 56), i.e. the plurality of contact pads (formed by 147) are provided by a conductive metal redistribution layer or RDL (145) and the surface treatment comprises a protective layer (148) of a dielectric material (as explained above). Note that pads formed by 147 are exposed by the protective layer (148) in the region where the conductive microvias (143) are to contact 147. It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that the plurality of contact pads are provided by a conductive metal redistribution layer (RDL) and the surface treatment comprises a protective layer of a dielectric material. The ordinary artisan would have been motivated to modify Lee for at least the purpose of using a structure with one or more redistribution layers that are known to improve layout of wiring and interconnections, thus providing a larger number of interconnections for a given real estate of the embedded die package.
Regarding claim 22, Lee (refer to Figure 2F) teaches the semiconductor die of claim 20, but does not teach wherein “wherein the plurality of contact pads are provided by a conductive metal redistribution layer (RDL) and the surface treatment comprises a protective layer of polyimide, or other suitable dielectric material”. Wang (US 20180366436) also teaches an embedded die packaging structure (see Figure 1-13) comprising a die (103, para 20), conductive microvias (143, described as "through-mold vias 143" in para 50; also see para 52), a conductive metal redistribution layer or RDL (145, described as “RDL 145”, which may comprise “metal layer 147” and “dielectric layer 148” – para 55 – see Figure 1-13) and 147 forms contact pads to which 143 connects (para 56), i.e. the plurality of contact pads (formed by 147) are provided by a conductive metal redistribution layer or RDL (145) and the surface treatment comprises a protective layer (148) of a dielectric material (as explained above). Note that pads formed by 147 are exposed by the protective layer (148) in the region where the conductive microvias (143) are to contact 147. It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee so that wherein the plurality of contact pads are provided by a conductive metal redistribution layer (RDL) and the surface treatment comprises a protective layer of a suitable dielectric material. The ordinary artisan would have been motivated to modify Lee for at least the purpose of using a structure with one or more redistribution layers that are known to improve layout of wiring and interconnections, thus providing a larger number of interconnections for a given real estate of the embedded die package.
Regarding claim 23, Lee (refer to Figure 2F) teaches the semiconductor die of claim 20, but does not teach wherein “wherein the plurality of contact pads are provided by a first conductive metal redistribution layer (RDL) and a second conductive metal redistribution layer patterned to provide an additional thickness of RDL in target areas for laser drilling”. Wang (US 20180366436) also teaches an embedded die packaging structure (see Figure 1-13) comprising a die (103, para 20), conductive microvias (143, described as "through-mold vias 143" in para 50; also see para 52) which may be laser drilled (para 50), a conductive metal redistribution layer or RDL (145, described as “RDL 145”, which may comprise “metal layer 147” and “dielectric layer 148” – para 55 – see Figure 1-13) and 147 forms contact pads to which 143 connects (para 56), i.e. the plurality of contact pads (formed by 147) are provided by a conductive metal redistribution layer or RDL (145) and the surface treatment comprises a protective layer (148) of a dielectric material (as explained above). Note that pads formed by 147 are exposed by the protective layer (148) in the region where the conductive microvias (143) are to contact 147. It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee to utilize multiple RDLs such as a first RDL stacked on a second RDL (or even multiple RDLs) so that the plurality of contact pads are provided by a first conductive metal redistribution layer (RDL) and a second conductive metal redistribution layer patterned to provide an additional thickness of RDL in target areas for laser drilling. The ordinary artisan would have been motivated to modify Lee for at least the purpose of using a structure with one or more redistribution layers that are known to improve layout of wiring and interconnections, with additional RDLs further providing a larger number of interconnections for a given real estate of the embedded die package.
Regarding claim 24, Lee (refer to Figure 2F) teaches the semiconductor die of claim 20, but does not teach wherein “the plurality of contact pads are provided by a first conductive metal redistribution layer (RDL1); a second conductive metal redistribution layer (RDL2) patterned to provide an additional thickness of RDL in target areas for laser drilling; and the surface treatment comprises a protective layer of polyimide, or other suitable dielectric material, on the additional thickness of RDL defining said target areas for laser drilling”. Wang (US 20180366436) also teaches an embedded die packaging structure (see Figure 1-13) comprising a die (103, para 20), conductive microvias (143, described as "through-mold vias 143" in para 50; also see para 52) which may be laser drilled (para 50), a conductive metal redistribution layer or RDL (145, described as “RDL 145”, which may comprise “metal layer 147” and “dielectric layer 148” – para 55 – see Figure 1-13) and 147 forms contact pads to which 143 connects (para 56), i.e. the plurality of contact pads (formed by 147) are provided by a conductive metal redistribution layer or RDL (145) and the surface treatment comprises a protective layer (148) of a dielectric material (as explained above). Note that pads formed by 147 are exposed by the protective layer (148) in the region where the conductive microvias (143) are to contact 147. It would have been obvious to one of ordinary skills in the art before the time of the effective filing of the claimed invention to modify Lee to utilize multiple RDLs such as a first RDL stacked on a second RDL (or even multiple RDLs) so that the plurality of contact pads are provided by a first conductive metal redistribution layer (RDL) and a second conductive metal redistribution layer patterned to provide an additional thickness of RDL in target areas for laser drilling the plurality of contact pads are provided by a first conductive metal redistribution layer (RDL1); a second conductive metal redistribution layer (RDL2) patterned to provide an additional thickness of RDL in target areas for laser drilling; and the surface treatment comprises a protective layer of polyimide, or other suitable dielectric material, on the additional thickness of RDL defining said target areas for laser drilling. The ordinary artisan would have been motivated to modify Lee for at least the purpose of using a structure with one or more redistribution layers that are known to improve layout of wiring and interconnections, with additional RDLs further providing a larger number of interconnections for a given real estate of the embedded die package.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Claim 8 is allowable because the prior art of record does not teach or suggest, singularly or in combination, at least the limitations that require “a disk of a protective masking layer provided on each of said first regions, the disk having a diameter that extends laterally of the base of the conductive microvia by an alignment tolerance for laser drilling”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AJAY ARORA whose telephone number is (571)272-8347. The examiner can normally be reached 9 AM - 5 PM.
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/AJAY ARORA/Primary Examiner, Art Unit 2892
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