DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/9/2025 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 12/1/2025. Claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claims 1, 8 & 15 each cites “wherein a top surface of said first level comprises said first oxide region” is not clear. In early claimed limitations, the claims require a first oxide layer overlaying said first metal layers, wherein said first oxide layer comprises a first oxide region. The first oxide region should belong to said first oxide layer instead. Thus, this causes a confusion in the claims, and Applicant is suggested to revise and clarify the claims to avoid any further confusions.
Claims 2-7, 9-14 & 16-20 are rejected as being dependent on claims 1, 8 & 15.
For best understanding and examination purpose, the claim(s) will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,136,562; 11,735,462 & 11,876,011; and claims 15-20 of U.S. Patent No. 11,101,266. Although the claims at issue are not identical, they are not patentably distinct from each other because they require 3D device having first/second levels, metal layers, DRAM or SRAM, bonding between first/second levels, and oxide-to-oxide bonds, etc.
Note: below table includes comparison between current application & US Patent no. 12,136,562.
Current Application 17/945,671
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors,
wherein said first level comprises control circuits and wherein said control circuits comprise a plurality of said first transistors;
a first oxide layer overlaying said first metal layers,
wherein said first oxide laver comprises a first oxide region and a first metal region.
wherein said first metal region is connected to at least one of said first metal layers; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein said second level comprises a plurality of DRAM memory cells and at least one metal layer for connecting said plurality of DRAM memory cells,
wherein said plurality of DRAM memory cells each comprise at least one of said second transistors.
wherein a top surface of said first level comprises said first oxide region and a bottom surface of said second level comprises a second oxide region,
wherein said second level overlays said first level,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
8. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising first transistors,
wherein said first transistors each comprise a single crystal channel;
first metal layers interconnecting at least said first transistors,
wherein said first level comprises control circuits and wherein said control circuits comprise a plurality of said first transistors;
a first oxide layer overlaying said first metal layers.
wherein said first oxide layer comprises a first oxide region and a first metal region wherein said first metal region is connected to at least one of said first metal layers; and
a second level comprising a second single crystal layer, said second level comprising second transistors,
wherein said second level comprises a plurality of SRAM memory cells and at least one metal layer for connecting said plurality of SRAM memory cells,
wherein said plurality of SRAM memory cells each comprise at least one of said second transistors.
wherein a top surface of said first level comprises said first oxide region and a bottom surface of said second level comprises a second oxide region,
wherein said second level overlays said first level,
wherein said second level is bonded to said first level, and
wherein said bonded comprises oxide to oxide bonds.
US Patent No. 12,136,562
1. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; a first oxide layer disposed over said second metal layer; a second oxide layer disposed over said first oxide layer; and a second level comprising at least one array of memory cells and second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said second level overlays said first level, wherein said at least one of said second transistors comprises at least two independent gates, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide-to-oxide bonds.
3. The device according to claim 1, wherein at least a portion of said memory cells are DRAM type memory cells.
15. A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; a first oxide layer disposed over said second metal layer; a second oxide layer disposed over said first oxide layer; and a second level comprising at least one array of memory cells and second transistors, wherein each of said memory cells comprises at least one of said second transistors, wherein said second level overlays said first level, wherein said memory cells are SRAM type memory cells, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide-to-oxide bonds.
20. The device according to claim 15, wherein said bonded comprises direct metal-to-metal bonds that are disposed on a same level as the direct oxide-to-oxide bonds.
Allowable Subject Matter
5. Claims 1-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph and Double Patenting, set forth in this Office action.
Response to Arguments
6. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/22/26
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