DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the amendment filed 11/10/2025 in which claims 12, 14, 16, 19, 20, 27, and 29 were amended.
Claims 12-31 remain pending and are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 20-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakanishi (US 2016/0163654 and Nakanishi hereinafter).
As to claims 20-23: Nakanishi discloses [claim 20] an inverter stage (Figs. 23-25; [0170]), comprising: a plurality of reverse conducting IGBT devices (1BT; [0172]), a reverse conducting IGBT device (1BT) of the plurality of reverse conducting IGBT devices including: an IGBT (TR; [0180]) in a first region (1C; [0180]) of a semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN; [0182]) having (interpreted to mean “comprising”) a first conductivity type (MN has n-type conductivity; [0182]), the IGBT (TR) including; a body region (EP; [0184]) adjacent to a first side (top surface) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) and extending into the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) a first distance (as shown) along a first direction (vertical direction of Fig. 25), the body region (EP) having a second conductivity type (p-type; [0184]) different from the first conductivity type (n-type); a diode (DIO; [0183]) in a second region (1D; [0180]) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN), the diode (DIO) including an anode region (AP; [0047]) adjacent to the first side (top surface) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) and extending into the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) a second distance (as shown in Fig. 25) along the first direction (vertical direction), the second distance being smaller than the first distance (as shown in Fig. 25, AP doesn’t extend vertically into MN as far as EP), the anode region (AP) having the second conductivity type (p-type; [0047]); a structural layer (IF; [0185]) on the first region (1C), the anode region (AP) at least partially offset with respect to the structural layer (as shown, 2 is not formed in region 1D such that AP has regions that are not covered by, i.e. offset with, the structural layer IF); a contact structure (comprising BM and EED within openings between IF; [0186]) in the structural layer (IF) and at least partially overlapping and in contact (electrical contact) with the body region (EP); and a first electrical terminal (portion of EED outside of openings in IF and AED; [0179] and [0186]) on the anode region (AP) and the contact structure (comprising BM and EED in openings of IF) and in contact with the anode region (AP) and the contact structure (comprising BM and EED in openings of IF); [claim 21] wherein the contact structure (comprising BM and EED in openings of IF) includes a conductive plug (EED in openings of IF) in the structural layer (IF) and a barrier layer (BM) between the conductive plug (EED in openings of IF) and the structural layer (IF); [claim 22] wherein the body region (EP extends to the top of SB away from the trench) has a first surface (top surface) coplanar with the first side (top surface) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN away from the trench); [claim 23] wherein the anode region (AP) has a second surface (top surface) coplanar with the first side (top surface) of the semiconductor substrate (AP is formed at the top surface of the substrate SB comprising MN, EP, CHP, AP, UP, and HN).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 12-19 and 27-31 are rejected under 35 U.S.C. 103 as being unpatentable over Konishi et al (US 2022/0157976 and Konishi hereinafter) in view of Mo et al (US 2005/0079676 and Mo hereinafter) in view of Kamibaba et al (US 2018/0294258 and Kamibaba hereinafter).
As to claims 12-19: Konishi discloses [claim 12] a reverse-conducting IGBT device (Fig 35; RC-IGBT; [0170]), comprising: an IGBT ([0060]) in a first region (area above 11; [0170]) of a semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3; [0065]) having (interpreted to mean “comprising”) a first conductivity type (region 10 has n-type conductivity; [0069]), the IGBT including: a body region (5; [0068]) having a second conductivity type (p-type; [0068]) opposite to the first conductivity type (n-type), the body region (5) adjacent to a first side (top surface; [0068]) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3); a contact region (3; [0068]) within the body region (5); a source region (4; [0068]) having the first conductivity type (n-type; [0068]) and in the body region (5); and a trench gate (29; [0060]) extending through the body region (5); a diode ([0170]) in a second region (area above 21; [0170]) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3), the diode including an anode region (5; [0170]) adjacent to the first side (top surface) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3), the anode region (5) having the second conductivity type (p-type; [0068]); a structural layer (2; [0072]) on the first region (area above 11); a contact hole (contact hole; [0090]) in the structural layer (2) and at least partially aligned with the contact region (3); a barrier layer (barrier metal; [0078]) in the contact hole (contact hole), configured to prevent metal ions diffusion (inherent to the type of materials of barrier layer such as Ti, TiN, etc.; [0078]); a metal plug (portion of 1 within contact hole; [0077]-[0078]) in the contact hole (contact hole) on the barrier layer (barrier metal); a first electrical terminal (portion of 1 outside contact hole in area above 11 and all of 1 above 21; [0077]-[0078]) on the anode region (5 above 21) and the metal plug (portion of 1 within contact hole in area above 11) and in electrical contact with the anode region (5 above 21) and the metal plug (portion of 1 within contact hole in area above 11), the first electrical terminal (portion of 1 outside contact hole in area above 11 and all of 1 above 21) being of a conductive material including an alloy of Aluminum and Silicon (1 can be AlSi; [0077]); a cathode terminal (21; [0170]) of the diode and an emitter terminal (11 can be made to function as an emitter and 1 can be made to function as a collector as it is intended use of the device; [0079]) of the IGBT on a second side (bottom surface) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3) that is opposite to the first side (top surface); and a second electrical terminal (12; [0079]) on the cathode terminal (21) and the emitter terminal (11) and in electrical contact with the cathode terminal (21) and the emitter terminal (11); [claim 13] wherein the metal plug (minute region can be tungsten, which is the area within the contact hole; [0077]) is of Tungsten, and the first electrical terminal (portion of 1 outside contact hole in area above 11 and all of 1 above 21) is of one or more of AlSiCu or AlSi (outside the minute region, 1 can be AlSi; [0077]); [claim 14] wherein the barrier layer (barrier metal) is one or more of a bi-layer of Ti and TiN, Ti Silicide, or TiW (Ti, TiN, or TiSi; [0078]); [claim 15] wherein the structural layer (2) is of dielectric material (SiO2; [0090]); [claim 16] wherein: the first electrical terminal (1) is a collector terminal of the IGBT (1 is referred to as an emitter, but the collector and emitter can be interchanged to function as claimed as this is intended use) and an anode terminal of the diode ([0170]); [claim 17] wherein the IGBT and the diode are connected to one another in anti-parallel configuration ([0003]); [claim 18] further comprising an enrichment region (3 above 21; [0068] and [0170]) in the anode region (area above 21) including dopant species of the second conductivity type (p-type; [0068]); [claim 19] wherein the contact region (3 above 11) has the second conductivity type (p-type; [0068]) and a dopant concentration (p+; [0068]) higher than a dopant concentration (p; [0068]) of the body region (5), and wherein the contact hole (contact hole) extends through the structural layer (2) and is at least partially aligned with the contact region (3 above 11).
Konishi fails to expressly disclose where [claim 12] the barrier layer being coupled to the contact region and separated from the source region.
Konishi discloses in Fig. 35 that the structural layer appears to cover most, if not all, of the source region 4 and exposes the contact region 3. However, it is not definitive in the drawings as there could be some small amount of exposed source region 4.
Mo discloses a gate trench structure comprising a body and drift region ([0002] and [0028]) in Fig. 1 and 1B where the source region 32A/32B in certain areas is completely covered by the structural layer 35 ([0026]). The claim does not state that the source region in all areas of the substrate is completely separated from the barrier layer, only that it is separated from the barrier layer. The broadest reasonable interpretation of “separated” is that as long as the source region is spaced from or not contacted by the barrier layer in some area of the substrate, the claim limitation is met. Therefore, as Mo discloses that the source region is covered by the structural layer in the “B” cross-section such that no overlying metal containing layer would contact the source region 32A/32B in that area, the source region is separated from any overlying metal containing layer such as a barrier layer.
Kamibaba discloses in Fig. 1 and [0043] an IGBT 101 with a barrier metal 12 that contacts exposed doped regions in the substrate, including the body contact region 3.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), all the claimed elements (the IGBT as disclosed by Konishi with a structural layer over at least a portion of the source region and exposing the contact region and the barrier layer between the source electrode and the structural layer, the structural layer of Mo that covers the entire source region in certain areas of the substrate and exposes the contact region, and the barrier layer of Kamibaba that is formed on all exposed doped regions in the substrate in the contact holes of the structural layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (to provide a barrier layer over the entire substrate surface such that the barrier layer directly contacts the contact region and is separated from the source region at least in certain areas of the substrate by the structural layer) with no change in their respective functions, and the combination would have yielded predictable results (an IGBT with reduced tun-on loss ([0010] of Konishi) with enhanced ruggedness and reduced degradation ([0027] of Mo) and reduced contact resistance ([0044] of Kamibaba)) to one of ordinary skill in the art before the effective filing date of the claimed invention.
As to claims 27-31: Konishi discloses [claim 27] a device (Fig. 35; [0170]), comprising: a substrate (comprising 10, 9, 6, 5, 4, and 3; [0065]) with a first surface (top surface), the substrate (comprising 10, 9, 6, 5, 4, and 3) including: a first region (region above 11; [0170]) including: a body region (5; [0062]) of a first conductivity type (p-type; [0062]) in the first surface (top surface); a plurality of source regions (4; [0064]) of a second conductivity type (n-type; [0064]) different from the first conductivity type (p-type) in the first surface (top surface); a contact body region (3; [0064]) within the body region (5) in the first surface (top surface); and an IGBT ([0060] and [0170]); a second region (region above 21; [0170]) including an anode region (5; [0170]) of the first conductivity type (p-type; [0062]) in the first surface (top surface) and a diode ([0170]); a structural layer (2; [0072]) on the first region (region above 11); a contact structure (comprising 1 in the contact hole; [0075] and [0090]) in the structural layer (2) and in contact (electrical contact through 3) with the body region (5) and the contact body region (3), the contact structure having a first sidewall (left sidewall) transverse to a second sidewall (second sidewall); and a first terminal (1 above 21; [0075]) on the anode region (5 above 21) and the contact structure (comprising 1 in the contact hole) and coupled to the anode region (5 above 21) and the contact structure (comprising 1 in the contact hole); [claim 28] wherein the body region (5 extends to the top of the substrate and is what 3 and 4 are formed in) and the plurality of source regions (4) are coplanar with the first surface (top surface) of the substrate (comprising 10, 9, 6, 5, 4, and 3); [claim 29] wherein the contact body region (3) is coplanar with the first surface (top surface) of the substrate (comprising 10, 9, 6, 5, 4, and 3), the contact body region (3) having the first conductivity type (p-type; [0064]); [claim 30] wherein the first (area above 11) and second (area above 21) regions each include at least one trench (7; [0064]) extending into the substrate (comprising 10, 9, 6, 5, 4, and 3) from the first surface (top surface), the at least one trench (7) including a conductive region (29 or 14; [0061] and [0071]) and a dielectric layer (8; [0061] and [0071]) separating the conductive region (29 or 14) from the substrate (comprising 10, 9, 6, 5, 4, and 3); [claim 31] wherein the dielectric layer (8) and the conductive region (29) of the at least one trench (7) in the first region (area above 11) are both coplanar with the first surface (top surface) and directly abutting the structural layer (2).
Konishi fails to expressly disclose where [claim 27] the contact structure being separated from the source region.
Konishi discloses in Fig. 35 that the structural layer appears to cover most, if not all, of the source region 4 and exposes the contact region 3. However, it is not definitive in the drawings as there could be some small amount of exposed source region 4.
Mo discloses a gate trench structure comprising a body and drift region ([0002] and [0028]) in Fig. 1 and 1B where the source region 32A/32B in certain areas is completely covered by the structural layer 35 ([0026]). The claim does not state that the source region in all areas of the substrate is completely separated from the barrier layer, only that it is separated from the barrier layer. The broadest reasonable interpretation of “separated” is that as long as the source region is spaced from or not contacted by the barrier layer in some area of the substrate, the claim limitation is met. Therefore, as Mo discloses that the source region is covered by the structural layer in the “B” cross-section such that no overlying metal containing layer would contact the source region 32A/32B in that area, the source region is separated from any overlying metal containing layer such as a barrier layer.
Kamibaba discloses in Fig. 1 and [0043] an IGBT 101 with a barrier metal 12 that contacts exposed doped regions in the substrate, including the body contact region 3.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because, as stated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), all the claimed elements (the IGBT as disclosed by Konishi with a structural layer over at least a portion of the source region and exposing the contact region and the barrier layer between the source electrode and the structural layer, the structural layer of Mo that covers the entire source region in certain areas of the substrate and exposes the contact region, and the barrier layer of Kamibaba that is formed on all exposed doped regions in the substrate in the contact holes of the structural layer) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (to provide a barrier layer over the entire substrate surface such that the barrier layer directly contacts the contact region and is separated from the source region at least in certain areas of the substrate by the structural layer) with no change in their respective functions, and the combination would have yielded predictable results (an IGBT with reduced tun-on loss ([0010] of Konishi) with enhanced ruggedness and reduced degradation ([0027] of Mo) and reduced contact resistance ([0044] of Kamibaba)) to one of ordinary skill in the art before the effective filing date of the claimed invention.
Claims 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Nakanishi in view of Konishi.
As to claims 24-26: Nakanishi discloses [claim 24] wherein the first region (Fig. 25; 1C) include at least one trench (groove; [0185]) extending from the first side (top surface) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) into the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN); [claim 25] wherein each trench (groove) includes a dielectric layer (IF within groove; [0185]) entirely covering inner sidewalls and bottoms of the trench (groove) and a conductive region (GE; [0185]) in the trench (groove), the conductive region (GE) being insulated from the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) by the dielectric layer (IF within groove); [claim 26] wherein each dielectric layer (IF within groove) has a first surface (top surface) coplanar with the first side (top surface) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN) and each conductive region (GE) has a second surface (top surface) coplanar with the first side (top surface) of the semiconductor substrate (SB comprising MN, EP, CHP, AP, UP, and HN).
Nakanishi fails to expressly disclose [claim 24] wherein the second region include at least one trench extending from the first side of the semiconductor substrate into the semiconductor substrate; [claim 25] wherein each trench includes a dielectric layer entirely covering inner sidewalls and bottoms of the trench and a conductive region in the trench, the conductive region being insulated from the semiconductor substrate by the dielectric layer; [claim 26] wherein each dielectric layer has a first surface coplanar with the first side of the semiconductor substrate and each conductive region has a second surface coplanar with the first side of the semiconductor substrate.
Konishi discloses an inverter in Fig. 35 [claim 24] wherein the second region (area above 21; [0170]) include at least one trench (7; [0060]) extending from the first side (top surface) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3) into the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3); [claim 25] wherein each trench (7) includes a dielectric layer (8; [0060]) entirely covering inner sidewalls and bottoms of the trench (7) and a conductive region (D/13; [0120]) in the trench (7), the conductive region (D/13) being insulated from the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3) by the dielectric layer (8); [claim 26] wherein each dielectric layer (8) has a first surface (top surface) coplanar with the first side (top surface) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3) and each conductive region (D/13) has a second surface (top surface) coplanar with the first side (top surface) of the semiconductor substrate (comprising 10, 9, 6, 5, 4, and 3).
Given the teachings of Konishi, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nakanishi by employing the well-known or conventional features of inverter fabrication, such as displayed by Konishi, by employing a trench with an insulating layer and conductive regions on the insulating layer in the diode region in order to reduce the turn-on loss ([0010]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
3/6/2026