DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 16, 2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “lower gate electrode and the upper gate electrode are configured to receive different voltages” (claim 9) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 6, 10-14 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2019/0027480) in view of Huang et al. (2019/0131185).
As for claims 1, 2, 4, 14 and 12, Lee et al. show in Figs. 1, 2A and related text a semiconductor device, comprising:
a substrate 100 having a trench 120; and
a gate structure 200 in the trench, wherein the gate structure comprises:
a lower gate electrode G1;
an upper gate electrode 250 disposed over the lower gate electrode; and
a metal layer 22 disposed between the lower gate electrode and the upper gate electrode; and
a work function adjustment layer 235 disposed over the metal layer and contacting a bottom surface and sidewalls of the upper gate electrode (wherein the conductive layer is formed along an interface between the metal layer and the upper gate electrode);
a lower dielectric layer 210 disposed between the lower gate electrode and the substrate;
wherein the metal layer is disposed between the lower dielectric layer and the upper gate electrode(; wherein the upper gate electrode is separated from the lower dielectric layer by the metal layer and the silicide layer).
Lee et al. do not disclose the work function layer is a silicide layer.
Lu et al. teach in Fig. 5 and related text a silicide layer 425 (426, 428 or 429) ([0072]-[0073]).
Lee et al. and Lu et al. are analogous art because they are directed to a gate structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. with the specified feature(s) of Lu et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use silicide layer as a work function adjustment layer, as taught by Lu et al., in Lee et al.'s device, in order to reduce gate resistance, contact resistance and RC delay.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
As for claim 3, the upper gate electrode is separated from the lower gate electrode by the metal layer and the silicide layer (Lee: Fig. 2A).
As for claim 9, the combined device shows the lower gate electrode and the upper gate electrode are configured to receive different voltages.
Regarding the limitations (“configured to receive different voltages”) these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Furthermore, claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danley, 120 USPQ 528, 531 (CCPA 1959). "Apparatus claims cover what a device is, not what a device does." Hewlett -Packard Co. v. Bausch & Lomb Inc., 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
As for claim 10, the combined device shows the gate structure is disposed in an active region of the substrate (Lee: Fig. 2A).
As for claim 11, the combined device shows the gate structure is disposed in an isolation region 101 of the substrate (Lee: Fig. 2A).
As for claim 13, the combined device shows the upper gate electrode is surrounded by the metal layer (Lee: Fig. 2A).
Claim(s) 6 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2019/0027480) and Huang et al. (2019/0131185) in view of Jang (2011/0180868).
As for claims 6 and 16, Lee et al. and Huang et al. disclosed substantially the entire claimed invention, as applied to claim 4 and 12, respectively, above, except a barrier layer disposed between the lower gate electrode and the substrate.
Jang teaches in Fig. 2d and related text a barrier layer 355 disposed between the lower gate electrode 365 and the substrate 300.
Lee et a., Huang et al. and Jang are analogous art because they are directed to a gate structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. and Huang et al. with the specified feature(s) of Jang because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a barrier layer disposed between the lower gate electrode and the substrate, as taught by Jang, in Lee et al. and Huang et al.'s device, in order to prevent a metallic material in the contact hole from diffuse into a substrate.
Therefore, the combined device shows:
As for claim 6, the barrier layer contacts the lower dielectric layer.
As for claim 16, the metal layer contacts the barrier layer.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2019/0027480) and Huang et al. (2019/0131185) in view of Kim et al. (2012/0299090).
Lee et al. and Huang et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except the lower gate electrode and the upper gate electrode are configured to receive different voltages.
Kim et al. teach in Figs. 3A, 5, 6A and related text the lower gate electrode SG1 and the upper gate electrode SG2 are configured to receive different voltages (Table 2: standby; [0119]).
Lee et a., Huang et al. and Kim et al. are analogous art because they are directed to a gate structure and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. and Huang et al. with the specified feature(s) of Kim et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the lower gate electrode and the upper gate electrode being configured to receive different voltages, as taught by Kim et al., in Lee et al. and Huang et al.'s device, in order to decrease resistance and switching noise of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-4, 6, 9-14 and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MEIYA LI whose telephone number is (571)270-1572. The examiner can normally be reached Monday-Friday 7AM-3PM.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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