DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 5, 2026, has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-6, 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US Publication No. 2022/0020859) in view of Alptekin et al (US Publication No. 2024/0070365).
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Regarding claim 1, Cho discloses a semiconductor device, comprising: an isolation region Fig 15B, ST or Fig 20, ST; at least one transistor Fig 15B, PR1 or Fig 20, TR2 comprising a gate region Fig 15B, GE or Fig 20, GE, wherein the gate region is disposed on the first surface of the isolation region Fig 15B, ST or Fig 20, ST; a signal line Fig 20, SI disposed on a second side of the isolation region Fig 20 ST opposite the first side of the isolation region Fig 20, ST; a via Fig 15B or Fig 20, TV/LP/MC ¶0094 extending through the isolation region and in contact with the signal line Fig 15B, SI or Fig 20, SI on the second side of the isolation region ¶0094-0095; and a gate contact Fig 15B, GC or Fig 16, UP disposed on the gate region Fig 15B or Fig 16, wherein the via ¶0089 Fig 15B or Fig 16, LP is connected to the gate contact Fig 15B, GC or Fig 16, UP and the signal line Fig 15B, SI or Fig 20, SI is connected to the gate region through the via ¶0094-0095 Fig 15B or Fig 20, TV/LP/MC and the gate contact Fig 15B, GC or Fig 20, UP. Cho discloses all the limitations but silent on the arrangement of the via and the signal line. Whereas Alptekin discloses a signal line disposed on a second surface of the isolation region opposite the first surface of the isolation region Fig 4 ¶0036-0037; a via Fig 4, 228 and Fig 8, 228 extending through the isolation region from the first surface to the second surface of the isolation region and in contact with the signal line disposed on the second surface of the isolation region Fig 4 and Fig 8. Cho and Alptekin are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Cho because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cho and incorporate the teachings of Alptekin to improve device performance.
Regarding claim 2, Cho discloses wherein the signal line Fig 15B, SI or Fig 20, SI is disposed in a same metallization level as a power element Fig 15B, POR1/POR2 ¶0095.
Regarding claim 3, Cho discloses wherein the power element comprises a power rail ¶0041-0042.
Regarding claim 4, Cho discloses wherein the at least one transistor further comprises a source/drain region Fig 15A, SD1, and the semiconductor device further comprises an additional via disposed through another portion of the isolation region and on the power element Fig 15A.
Regarding claim 5, Cho discloses further comprising a source/drain contact disposed on the source/drain region, wherein the additional via Fig 15A, EP is connected to the source/drain contact Fig 15A.
Regarding claim 6, Cho discloses wherein the via contacts a side surface of the gate region Fig 14A.
Regarding claim 8, Cho discloses wherein the via is disposed adjacent the gate region Fig 15B and Fig 16.
Regarding claim 9, Cho discloses further comprising at least one additional transistor comprising an additional gate region, wherein the additional gate region is disposed on the first side of the isolation region, and wherein the via is disposed between the gate region and the additional gate region Fig 15B, Fig 16 and Fig 20.
Regarding claim 10, Cho discloses wherein the gate contact is further disposed on the additional gate region, and wherein the signal line is connected to the additional gate region through the via and the gate contact Fig 15B, Fig 16 and Fig 20.
Regarding claim 11, Cho discloses a semiconductor device, comprising: an isolation region Fig 15B, ST or Fig 20, ST; at least one transistor Fig 15B, PR1 or Fig 20, TR2 comprising a gate region Fig 15B, GE or Fig 20, GE and a source/drain region Fig 15A, SD1; wherein the gate region Fig 15B, GE or Fig 20, GE and the source/drain region Fig 15A, SD1 are disposed on a first surface of the isolation region Fig 15B, ST or Fig 20, ST; a signal line Fig 20, SI and a power element Fig 15B, POR1/POR2 disposed on a second surface of the isolation region Fig 20 ST opposite the first surface of the isolation region Fig 20, ST ¶0095; a first via Fig 15B or Fig 20, TV/LP/MC ¶0094 extending through the isolation region and in contact with the signal line Fig 15B, SI or Fig 20, SI; wherein the first via ¶0089,0094-0095 Fig 15B or Fig 20, TV/LP/MC connects the signal line Fig 15B, SI or Fig 20, SI to the gate region Fig 15B, GE or Fig 16, GE; and a second via Fig 15A, EP extending through the isolation region and in contact with the power element Fig 15A, POR1/POR2 ¶0095, wherein the second via connects the power element to the source/drain region Fig 15A. Cho discloses all the limitations but silent on the arrangement of the via and the signal line. Whereas Alptekin discloses a signal line disposed on a second surface of the isolation region opposite the first surface of the isolation region Fig 4 ¶0036-0037; a first and second via Fig 4, 228 and Fig 8, 228 extending through the isolation region from the first surface to the second surface of the isolation region and in contact with the signal line disposed on the second surface of the isolation region Fig 4 and Fig 8. Cho and Alptekin are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Cho because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cho and incorporate the teachings of Alptekin to improve device performance.
Regarding claim 12, Cho discloses wherein the signal line is disposed in a same metallization level as the power element Fig 15A-15B and Fig 16.
Regarding claim 13, Cho discloses wherein the power element comprises a power rail¶0041-0042.
Regarding claim 14, Cho discloses a gate contact Fig 15B, GC or Fig 20, UP on the gate region, wherein the first via Fig 15B, LP or Fig 20, LP/TV/MC is connected to the gate contact Fig 15B, GC or Fig 20, UP on and the signal line Fig 15B, SI or Fig 20, SI on is connected to the gate region through the first via and the gate contact Fig 15A-15B and Fig 16.
Regarding claim 15, Cho discloses wherein the first via contacts a side surface of the gate region Fig 14A.
Regarding claim 16, Cho discloses a source/drain contact on the source/drain region, wherein the second via Fig 15A, EP is connected to the source/drain contact and the power element Fig 15A, POR1/POR2 is connected to the source/drain region through the second via and the source/drain contact Fig 15A.
Regarding claim 17, Cho discloses an integrated circuit, comprising: at least one transistor Fig 15B, PR1 comprising a gate region Fig 15B, GE and source/drain region Fig 15A, SD1 which are disposed on a first surface of an isolation region Fig 15B, ST or Fig 20, ST;a signal line Fig 20, SI and a power element Fig 15B, POR1/POR2 disposed in a same metallization level on a second surface of the isolation region opposite the first side ¶0095 Fig 15A-15B;a first via Fig 15B or Fig 20, TV/LP/MC ¶0094 extending through the isolation region and connecting the gate region Fig 15B, GE or Fig 16, GE to the signal line Fig 15B, SI or Fig 20, SI; and a second via Fig 15A, EP extending through the isolation region and connecting the source/drain region Fig 15A, SD1 to the power element Fig 15A-15B ¶0094-0095. Cho discloses all the limitations but silent on the arrangement of the via and the signal line. Whereas Alptekin discloses a signal line disposed on a second surface of the isolation region opposite the first surface of the isolation region Fig 4 ¶0036-0037; a first and second via Fig 4, 228 and Fig 8, 228 extending through the isolation region from the first surface to the second surface of the isolation region and in contact with the signal line disposed on the second surface of the isolation region Fig 4 and Fig 8. Cho and Alptekin are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Cho because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cho and incorporate the teachings of Alptekin to improve device performance.
Regarding claim 18, Cho discloses a gate contact Fig 15B, GC on the gate region Fig 15B, GE1, wherein the first via ¶0089 Fig 15B or Fig 20, TV/LP/MC is connected to the gate contact Fig 15B, GC and the signal line Fig 15B, SI is connected to the gate region through the first via and the gate contact Fig 15A-15B.
Regarding claim 19, Cho discloses wherein the first via contacts a side surface of the gate region Fig 14A.
Regarding claim 20, Cho discloses a source/drain contact on the source/drain region, wherein the second via Fig 15A, EP is connected to the source/drain contact and the power element Fig 15A, POR1/POR2 is connected to the source/drain region through the second via and the source/drain contact Fig 15A.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US Publication No. 2022/0020859) and Alptekin et al (US Publication No. 2024/0070365) in further view of Chen et al (US Publication No. 2023/0036522).
Regarding claim 7, Cho discloses all the limitations but is silent on the clock signal line. Whereas Chen discloses wherein the signal line comprises a clock signal line ¶0097-0099. Cho and Chen are analogous art because they are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of Cho because they are from the same field of endeavor.
Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the device of Cho and incorporate the teachings of Chen to improve device synchronization and timing.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/CHRISTINE A ENAD/Primary Examiner, Art Unit 2811
