DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/9/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang, US Pub. No. 2021/0083083 A1.
Re claim 9, Huang discloses a high electron mobility transistor (HEMT), comprising: a buffer layer 15/14/13/12 on a substrate 11 (i.e., fig. 6A-1/2 or fig. 10A-1/2); a barrier layer 16 on the buffer layer (i.e., fig. 6A-1/2 or fig. 10A-1/2); a p-type semiconductor layer 26 (i.e, the bottom 1/3 portion of the 26, see fig. 6A-1/2 or fig. 10A-1/2) on the barrier layer; and a gate electrode 26 (i.e, the upper 1/3 portion of the 26, see fig. 6A-1/2 or fig. 10A-1/2) on the p-type semiconductor layer, wherein the gate electrode comprises an inclined sidewall (i.e, fig. 6A-1/2 or fig. 10A-1/2) and a width of a bottom surface of the gate electrode and a width of a top surface of the p-type semiconductor layer are different (i.e, fig. 6A-1/2 or fig. 10A-1/2), also see figs. 4A-4D, see figs. 1-42And pages 1-17 for more details.
Re claim 10. : The HTEMT of claim 9, wherein the gate electrode comprises a trapezoid (i.e., fig. 6A-1/2 or fig. 10A-1/2).
Re claim 11. : The HTEMT of claim 9, wherein a bottom surface of the gate electrode is less than a top surface of the gate electrode (i.e., fig. 6A-1/2 or fig. 10A-1/2).
Re claim 12.: The HTEMT of claim 9, wherein the buffer layer 15 comprises gallium nitride (GaN) (i.e., paragraph 121 etc.).
Re claim 13. : The HTEMT of claim 9, wherein the barrier layer 16 comprise AlxGa1.xN (i.e., paragraph 121 etc.).
Re claim 14. The HTEMT of claim 9, wherein the p-type semiconductor layer comprises p-type gallium nitride (pGaN) (i.e., paragraph 120 etc.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK CHEN whose telephone number is (571)272-1689. The examiner can normally be reached Monday to Friday, 8am to 4pm.
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/JACK S CHEN/ Primary Examiner, Art Unit 2893
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