DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/13/2025 has been entered.
Response to Arguments
6. Applicant’s arguments, see Claim Rejections – 35 U.S.C. 103, filed 11/13/2025, with respect to the rejection(s) of claim(s) 1 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka) in view of Jerome, Rick C. et al (Pub No. US 5561073 A) (hereinafter, Jerome).
7. Applicant's arguments filed 11/13/2025 have been fully considered but they are not persuasive.
Regarding amended claim 1, in response to applicant's argument (Page 3 of Remarks), “the trench groove 13A/13B of Yamaoka would not be configured to electrically insulate a specific region in the semiconductor device of Yamaoka,” a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Referring to Fig. 13 of Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka), the deep trench isolation structures may comprise of trench grooves (13A/13B) and insulation film (14), wherein the insulation film is configured to insulate specific regions in the semiconductor device and does define boundaries between device regions.
Regarding claim 1, In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., Gettering sites are configured to trap impurity atoms to prevent impurity atoms from negatively affecting electrical performance of the semiconductor device, Page 4 of Remarks… [and] current is prevented from flowing through the gettering site, Page 5 of Remarks) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
8. Applicant's arguments filed 11/13/2025 have been fully considered but they are not persuasive.
Regarding claim 15, in response to applicant’s argument that “etching inhibitor (141) is formed during the formation of a temporary trench (131) (Page 6 of Remarks)… whereas Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka) teaches the insulation film 14 is formed after the formation of grooves 13A/13B (Page 7 of Remarks),” the fact that the inventor has recognized another advantage which would flow naturally from following the suggestion of the prior art cannot be the basis for patentability when the differences would otherwise be obvious. See Ex parte Obiaya, 227 USPQ 58, 60 (Bd. Pat. App. & Inter. 1985).
The prior art anticipates the claimed process, i.e. “an etching inhibitor is concurrently formed during etching the semiconductor layer,” although there exists a change in sequence. (See MPEP § 2144.04 (IV) (C))
Unless the applicant can show a process in the specification of the etching inhibitor (141, Fig 6) being formed concurrently while etching the semiconductor layer (105, Fig 6), it is assumed the etching inhibitor must be formed at some time after the trench is formed. This is due to the fact that the etching inhibitor covers portions of the width of the trench (131, Fig 6), thus the etchant would have remove portions of the substrate 105 before the etching inhibitor is formed in the trench.
Regarding claim 15, in response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
In this case, the applicant argues “persons of ordinary skill in the art would have no motivation to form a gettering region surrounding the trench groove of Yamaoka, because Yamaoka does not teach anything about the negative effect from the impurity atoms (Page 10 of Remarks).”
The deep isolation structures (Drain lead electrodes/insulation film; Fig 13) of Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka) contain, in its broadest reasonable interpretation, a gettering site, and therefore have some motivation to be combined with the gettering regions (105, Fig 2) of Shoyama, Toshihiro (Pub No. US 20190237495 A1) (hereinafter, Shoyama). However, applicant may prove otherwise by claiming the intended purpose of the gettering region as preventing the negative effect from the impurity atoms.
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka), and further in view of Jerome, Rick C. et al (Pub No. US 5561073 A) (hereinafter, Jerome).
Yamaoka, Fig 13: Semiconductor Device with Deep Trench Isolation Structures
PNG
media_image1.png
425
680
media_image1.png
Greyscale
Re Claim 1, (Currently Amended) Yamaoka teaches a semiconductor device comprising a semiconductor device region (Center region comprising of semiconductor power elements connecting to metal wires 18C; Fig 13; ¶[0006]) and an isolation region (Regions comprising drain lead electrodes/Insulation film 15A/15B/14; Fig 13; ¶[0065]) surrounding the semiconductor device region, and the semiconductor device:
a semiconductor layer (P-type silicon substrate and N-type expitaxial silicon layer; 1/5; Fig 13; ¶[0048]) disposed on the insulating base layer;
a deep trench isolation structure (Drain lead electrodes/Insulation film; 15A/15B/14; Fig 13; ¶[0065]) disposed in the isolation region and surrounding the semiconductor device region,
wherein the deep trench isolation structure is configured to electrically insulate (Insulation film 14 insulates the central region comprising of metal wire 18C from outer regions and is used as a stopper to block electrical current flow; Fig 13; ¶[0120]) the semiconductor component region from an external region (Regions on outside of deep trench isolate structures comprising of metal wires 18A/18E; Fig 13), and the deep trench isolation structure comprises:
at least two insulating layers (Gate insulation films in trench grooves (7A/7B); 8; Fig 13; ¶0072]) disposed on the semiconductor layer, and each insulating layer comprising a bottom surface (Bottom surface of gate electrodes (9A/9B) and trench grooves (7A/7B); Fig 13; ¶[0060]);
at least two isolation trenches (Trench grooves; 30A/30B; Fig 13; ¶[0050]), each isolation trench being disposed on the semiconductor layer and passing through each insulating layer, wherein each isolation trench comprises a first cross-section (Above bottom surface of gate insulation film (8); Fig 13), a second cross-section (Below bottom surface of gate insulation film (8); Fig 13) and a third cross-section (Bottom surface of drain lead electrodes (15A/15B); Fig 13) from top to bottom, the first cross-section is higher than a bottom surface (Bottom surface of gate insulation film (8); Fig 13) of the insulating layer, and the second cross-section and the third cross-section are lower than the bottom surface of each insulating layer; and
at least two gettering sites (Sites in local area of each drain lead electrode (15A/15B) and buried diffusion layer (3), see Fig 10A below; ¶[0065]) disposed in the semiconductor layer and respectively contacting the isolation trenches, wherein a vertex (Upper surface of buried diffusion layer (3); Fig 10A) of each gettering site is lower than the second cross-section.
Yamaoka, Fig 10A: Gettering Site
PNG
media_image2.png
328
485
media_image2.png
Greyscale
However, Yamaoka does not teach an insulating base layer.
In the same field of endeavor, Jerome teaches an insulating base layer (Dielectric layer; 15; Fig 17; Col 4 ln 45-50). (See Fig 17 below)
Jerome, Fig 17: Semiconductor Device with Insulating Base Layer
PNG
media_image3.png
214
339
media_image3.png
Greyscale
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have added the insulating base layer as taught by Jerome. One would have been motivated to do this with a reasonable expectation of success in order to form a stacked silicon on insulator (SOI) substrate, which inherently comprise radiation hardened characteristics. Further, SOI substrates are substantially immune to noise. This is realized by the fact that SOI substrates provide greater isolation from the substrate instead of a PN junction, as well as reduced parasitic effects, as suggested by Jerome (Col 4 ln 35-45).
Re Claim 2, (Original) Yamaoka teaches the semiconductor device of claim 1, wherein each of the insulating layers (Gate insulation films in trench grooves (7A/7B); 8; Fig 13; ¶0072]) comprises a bottom corner (Bottom left corner of gate insulation film (8); Fig 13A) laterally separated from a top corner (Top corner where insulation film (14) intersects with gate insulation film (8); Fig 13A) of the semiconductor layer (P-type silicon substrate and N-type expitaxial silicon layer; 1/5; Fig 13; ¶[0048]). (See Fig 13A below)
Yamaoka, Fig 13A
PNG
media_image4.png
604
579
media_image4.png
Greyscale
Re Claim 3, (Original) Yamaoka does not teach the semiconductor device of claim 1, wherein each of the isolation trenches passes through the semiconductor layer to expose the insulating base layer.
In the same field of endeavor, Jerome teaches the semiconductor device of claim 1, wherein each of the isolation trenches (Isolation trench; 25; Fig 3; Col 5 ln 5-10) passes through the semiconductor layer (First conductive layer; 20; Fig 3; Col 4 ln 50-55; Note: Fig 2 originally has a [silicon] conductive layer 20 which is divided into 22 and 23) to expose the insulating base layer. (See Fig 3 below)
Jerome, Fig 3: Isolation Trench in Semiconductor Layer
PNG
media_image5.png
180
379
media_image5.png
Greyscale
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have etched an isolation trench to pass through the semiconductor layer and expose the insulating base layer beneath, as taught by Jerome. One would have been motivated to do this with a reasonable expectation of success in order to create stress and defects which can be drawn down to the interface between the isolation trench and dielectric layer to provide a means of intrinsic gettering of the divided semiconducting regions (22/23), as suggested by Jerome (Col 5 ln 25-30).
Re Claim 4, (Original) Yamaoka teaches the semiconductor device of claim 1, wherein each of the gettering sites (Sites in local area of each drain lead electrode (15A/15B) and buried diffusion layer (3), see Fig 10A above; ¶[0065]) is disposed along an inner sidewall (Sidewalls of drain lead electrodes (15A/15B) in contact with buried diffusion layer (3); Figs 10A/13) of a lower portion (Lower portion of drain lead electrodes (15A/15B); Figs 10A/13) of each of the isolation trenches (Trench grooves; 30A/30B; Fig 13; ¶[0050]).
Re Claim 5, (Original) Yamaoka teaches the semiconductor device of claim 1, wherein the gettering sites (Sites in local area of each drain lead electrode (15A/15B) and buried diffusion layer (3), see Fig 10A above; ¶[0065]) between the isolation trenches (Trench grooves; 30A/30B; Fig 13; ¶[0050]) are laterally separated from each other (Sites existing locally around drain lead electrodes (15A/15B)).
Re Claim 6, (Original) Yamaoka in view of Jerome does not teach the semiconductor device of claim 1, wherein a width relationship among the first cross-section, the second cross-section and the third cross-section satisfies following relations (1) and (2):
Wp1 < Wp2 (1)
Wp3 < Wp2 (2)
wherein Wp1 is a width of the first cross-section, Wp2 is a width of the second cross-section, and Wp3 is a width of the third cross-section.
However, the ordinary artisan would have recognized the width of the second cross section to be greater than the widths of the first and third cross-sections, to be a result effective variable affecting the electrical isolation between the semiconducting layers surrounding the isolation trench to be optimum, such that the first cross-section is electrically isolated due to insulating layers and the third cross-section comprises of the surrounding gettering sites. Thus, it would have been obvious to modify the thickness of the first metal seed layer within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
Re Claim 7, (Original) Yamaoka teaches the semiconductor device of claim 1, further comprising:
at least two upper through holes (Top of grooves (13A/13B); Fig 13; ¶[0063]) respectively disposed in the insulating layers (Gate insulation films in trench grooves (7A/7B); 8; Fig 13; ¶0072]); and
an etching inhibitor (Insulation film; 14; Fig 13; ¶[0064]) covering an inner sidewall (Sidewalls of sloped portion of trench groove (30A); Fig 13) of each of the upper through holes.
Re Claim 8, (Original) Yamaoka teaches the semiconductor device of claim 7, wherein a width relationship between each upper through hole (Top of grooves (13A/13B); Fig 13; ¶[0063]) and the third cross-section (Bottom surface of drain lead electrodes (15A/15B); Fig 13) of each isolation trench (Trench grooves; 30A/30B; Fig 13; ¶[0050]) satisfies following relation (3): Wt1 > wp3 (See second modification of Fig 13 below)
wherein Wtl is a width (Width of trench groove 30A where insulation film (14) is horizontal and parallel to the p-doped silicon substrate; Fig 13) of each of the through holes.
Yamaoka, Modification of Fig 13: Widths of Trench Isolation Structures
PNG
media_image6.png
425
543
media_image6.png
Greyscale
Re Claim 9, (Original) Yamaoka teaches the semiconductor device of claim 7, wherein a composition of the etching inhibitor (Insulation film; 14; Fig 13; ¶[0064]) comprises a polymer or a silicon-containing oxide (Per ¶[0049] insulation films burying gate electrodes (9A/9B) may be silicon dioxide).
Re Claim 10, (Original) Yamaoka teaches the semiconductor device of claim 7, wherein the inner sidewall (Sidewall on side of drain lead electrodes (15A/15B); Fig 13) of the etching inhibitor (Insulation film; 14; Fig 13; ¶[0064]) is coincident with an upper inner sidewall (Sidewall closest to insulation film (14); Fig 13) of each of the isolation trenches (Trench grooves; 30A/30B; Fig 13; ¶[0050]).
Re Claim 11, (Original) Yamaoka teaches the semiconductor device of claim 7, wherein the etching inhibitor (Insulation film; 14; Fig 13; ¶[0064]) comprises an inclined surface (Slopes within trench grooves 30A/30B; Fig 13).
Re Claim 12, (Original) Yamaoka teaches the semiconductor device of claim 7, further comprising at least two lower through holes (Bottom of grooves (13A/13B); Fig 13; ¶[0063]) disposed in the semiconductor layer (P-type silicon substrate and N-type expitaxial silicon layer; 1/5; Fig 13; ¶[0048]) , wherein the etching inhibitor further covers an inner sidewall (Parallel vertical sidewalls along grooves (13A/13B); Fig 13) of each of the lower through holes.
Re Claim 13, (Original) Yamaoka teaches the semiconductor device of claim 1, wherein a surface (Upper surface adjacent to body diffusion layer (11); Fig 13) of the semiconductor layer (P-type silicon substrate and N-type expitaxial silicon layer; 1/5; Fig 13; ¶[0048]) comprises at least two recessed regions (Trench grooves; 7A/7B; Fig 13; ¶[0049]), and the insulating layers (Gate insulation films in trench grooves (7A/7B); 8; Fig 13; ¶0072]) are respectively filled in the recessed regions.
Re Claim 14, (Original) Yamaoka teaches the semiconductor device of claim 1, further comprising an active device region (Between drain lead electrodes; Fig 13) disposed between the isolation trenches (Trench grooves; 30A/30B; Fig 13; ¶[0050]), and the active device region comprises a doped region (N-type source diffusionlayer/P-type body diffusion layer; 10/11; Fig 13; ¶[0049]) vertically separated from the gettering sites (Sites in local area of each drain lead electrode (15A/15B) and buried diffusion layer (3), see Fig 10A above; ¶[0065]).
11. Claims 15-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka) in view of Jerome, Rick C. et al (Pub No. US 5561073 A) (hereinafter, Jerome), and further in view of Shoyama, Toshihiro (Pub No. US 20190237495 A1) (hereinafter, Shoyama).
Re Claim 15, (Original) Yamaoka teaches a method of manufacturing a semiconductor device, comprising:
forming an insulating layer (Gate insulation films in trench grooves (7A/7B); 8; Fig 6; ¶0072]) on the semiconductor layer (P-type silicon substrate and N-type epitaxial silicon layer; 1/5; Fig 6; ¶[0048]), wherein the insulating layer comprises a bottom surface (Bottom surface of trench grooves (7A/7B); Fig 6; ¶[0060]); (See Fig 6 below)
Yamaoka, Fig 6: Forming insulating layer
PNG
media_image7.png
218
473
media_image7.png
Greyscale
forming at least one isolation trench (Trench grooves; 30A/30B; Fig 9; ¶[0050]) in the semiconductor layer and the insulating layer, wherein forming the at least one isolation trench comprises:
etching (Etching is performed to form grooves (13A/13B); Figs 8-9; ¶[0063]) the insulating layer to form an upper through hole (Top of grooves (13A/13B); Figs 8-9; ¶[0063]) in the insulating layer; and
after etching the insulating layer, etching (Etching through N-type epitaxial silicon layer (5) towards buried diffusion layer (3); Figs 8-9; ¶[0063]) the semiconductor layer to form a lower through hole (Bottom of grooves (13A/13B); Figs 8-9; ¶[0063]) in the semiconductor layer, (See Figs 8-9 below)
Yamaoka, Figs 8-9: Etching Isolation Trench
PNG
media_image8.png
265
359
media_image8.png
Greyscale
PNG
media_image9.png
272
388
media_image9.png
Greyscale
wherein a lower portion (Base of isolation region; Figs 10/10A) of the lower through hole comprises a tapered portion (Narrowed portion at the base of trench groove (30A); Fig 10A), and an etching inhibitor (Insulation film; 14; Fig 10; ¶[0064]) is concurrently formed during etching the semiconductor layer, and the etching inhibitor covers an inner sidewall (Sidewalls along upper portion of grooves (13A/13B); Fig 10) of the upper through hole; (See Fig 10 below)
Yamaoka, Fig 10: Etching Inhibitor Liner on Tapered Portion of Trenches
PNG
media_image10.png
258
448
media_image10.png
Greyscale
after forming the at least one isolation trench, forming a gettering site (Sites in local area of each drain lead electrode (15A/15B) and buried diffusion layer (3), see Fig 10A above; ¶[0065]) by using the insulating layer as an ion implantation mask (Per ¶[0062] the central portion gate insulation film (8) is removed, such that the remaining portion of gate insulation film (8) is a mask for ion-implanting Arsenic (As) into epitaxial silicon layer (5)), wherein the gettering site contacts the at least one isolation trench, and a vertex (Upper surface of buried diffusion layer (3); Fig 10A) of the gettering site is lower than a bottom surface (Below bottom surface of gate insulation film (8); Fig 10) of the insulating layer.
However, Yamaoka does not teach providing a substrate, wherein an insulating base layer and a semiconductor layer are sequentially disposed thereon;
forming at least one isolation trench in the semiconductor layer and the insulating layer to expose the insulating base layer
after forming the at least one isolation trench, forming a gettering site by using the insulating layer as an ion implantation mask,
wherein the gettering site contacts the at least one isolation trench, and a vertex of the gettering site is lower than a bottom surface of the insulating layer; and
forming an insulating material in the at least one isolation trench.
In the same field of endeavor, Jerome teaches providing a substrate (Semiconductor substrate; 12; Fig 2; Col 4 ln 45-50), wherein an insulating base layer (Dielectric layer; 15; Fig 2; Col 4 ln 45-50) and a semiconductor layer (First conductive layer; 20; Fig 2; Col 4 ln 50-55) are sequentially disposed thereon; (See Fig 2 below)
Jerome, Fig 2: Semiconductor Device Layers
PNG
media_image11.png
136
302
media_image11.png
Greyscale
forming at least one isolation trench (Isolation trench; 25; Fig 3; Col 5 ln 5-10) in the semiconductor layer and the insulating layer to expose the insulating base layer
forming an insulating material (Undoped polysilicon refill; 55; Fig 12; Col ln 24-30) in the at least one isolation trench. (See Fig 12 below)
Jerome, Fig 12: Forming Insulating Material
PNG
media_image12.png
190
323
media_image12.png
Greyscale
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the methods of Yamaoka and Jerome to form stacked a semiconducting layer on an insulating base layer on a substrate, forming an isolation trench to expose the insulating base layer and forming an insulating material in at least one isolation trench.
One would have been motivated to do this with a reasonable expectation of success in order to create stress and defects which can be drawn down to the interface between the isolation trench and dielectric layer to provide a means of intrinsic gettering of the divided semiconducting regions (22/23), as suggested by Jerome (Col 5 ln 25-30).
Further, silicon on insulator (SOI) substrate, which inherently comprise radiation hardened characteristics. Further, SOI substrates are substantially immune to noise. This is realized by the fact that SOI substrates provide greater isolation from the substrate instead of a PN junction, as well as reduced parasitic effects, as suggested by Jerome (Col 4 ln 35-45).
Finally, undoped polysilicon refill reduces stress related problems particularly at mask edges and corners because of the similar rates of thermal expansion between polysilicon and the active silicon regions. Further, undoped polysilicon is more conductive than silicon dioxide, and as such, it has a substantially lower resistive characteristic for parasitic purposes. Moreover, undoped polysilicon is more substantially conformal than silicon dioxide, as suggested by Jerome (Col 6 ln 55-65).
However, Yamaoka in view of Jerome does not teach after forming the at least one isolation trench, forming a gettering site by using the insulating layer as an ion implantation mask,
wherein the gettering site contacts the at least one isolation trench, and a vertex of the gettering site is lower than a bottom surface of the insulating layer; and
In the same field of endeavor, Shoyama teaches after forming the at least one isolation trench (Trench; 104; Fig 2; ¶[0025]), forming a gettering site (Gettering region; 105; Fig 2; ¶[0025]) by using the insulating layer (Insulating film; 102; Fig 2; ¶[0025]) as an ion implantation mask (Hard mask, i.e. ion implantation mask; ¶[0025]),
wherein the gettering site contacts (Below the bottom of trench and on lateral side of trench 104; ¶[0025]) the at least one isolation trench, and a vertex (Top portion of gettering region 105; Fig 2) of the gettering site is lower than a bottom surface (Bottom surface of insulating film 102; Fig 2) of the insulating layer. (See fig 2 below)
Shoyama, Fig 2: Forming gettering site via ion implantation mask
PNG
media_image13.png
633
438
media_image13.png
Greyscale
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the methods of forming two gettering sites through an ion implantation mask as taught by Shoyama, for the method of manufacturing the semiconductor device of Yamaoka in view of Jerome.
One would have been motivated to do this with a reasonable expectation of success because the ion implantation method through a trench within the semiconductor substrate requires a relatively low acceleration energy while forming the gettering site at a deeper position within a semiconductor substrate, as taught by Shoyama (¶¶[0025-0026]).
Re Claim 16, (Original) Yamaoka teaches the method of claim 15, wherein the at least one isolation trench (Trench grooves; 30A/30B; Fig 13; ¶[0050]) comprises a first cross-section (Above bottom surface of gate insulation film (8); Fig 13), a second cross-section (Below bottom surface of gate insulation film (8); Fig 13) and a third cross-section (Bottom surface of drain lead electrodes (15A/15B); Fig 13) from top to bottom, the first cross-section is higher than a bottom surface (Bottom surface of gate insulation film (8); Fig 13) of each of the insulating layers (Gate insulation films in trench grooves (7A/7B); 8; Fig 13; ¶0072]) , the second cross-section and the third cross-section are lower than the bottom surface of each of the insulating layers,
However, Yamaoka does not teach and a width relationship among the first cross-section, the second cross-section and the third cross-section satisfies following relations (1) and (2):
Wp1 < Wp2 (1)
Wp3 < Wp2 (2)
wherein Wp1 is a width of the first cross-section, Wp2 is a width of the second cross-section, and Wp3 is a width of the third cross-section.
However, the ordinary artisan would have recognized the width of the second cross section to be greater than the widths of the first and third cross-sections, to be a result effective variable affecting the electrical isolation between the semiconducting layers surrounding the isolation trench to be optimum, such that the first cross-section is electrically isolated due to insulating layers and the third cross-section comprises of the surrounding gettering sites. Thus, it would have been obvious to modify the thickness of the first metal seed layer within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
Re Claim 17, (Original) Yamaoka teaches the method of claim 15, wherein a composition of the etching inhibitor (Insulation film; 14; Fig 13; ¶[0064]) comprises a polymer or a silicon-containing oxide (Per ¶[0049] insulation films burying gate electrodes (9A/9B) may be silicon dioxide).
Re Claim 19, (Original) Yamaoka teaches the method of claim 15, further comprising using the etching inhibitor (Insulation film; 14; Fig 13; ¶[0064]) as an ion implantation mask (Per ¶[0062] the central portion gate insulation film (8) is removed, such that the remaining portion of gate insulation film (8) is a mask for ion-implanting Arsenic (As) into epitaxial silicon layer (5)) during forming the gettering site (Sites in local area of each drain lead electrode (15A/15B) and buried diffusion layer (3), see Fig 10A above; ¶[0065]).
Re Claim 20, (Original) Yamaoka does not teach the method of claim 15, wherein the gettering site directly contacts the insulating base layer.
In the same field of endeavor, Jerome teaches the method of claim 15, wherein the gettering site (Interface between trench (25) and dielectric layer (15); Fig 3; Col 5 ln 25-30) directly contacts the insulating base layer (Dielectric layer; 15; Fig 3; Col 5 ln 25-30).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the methods of Yamaoka and Jerome to make a gettering site which directly contacts the insulating base layer. One would have been motivated to do this with a reasonable expectation of success because the insulating layer acts as a barrier diffusion layer which deflects impurities away to be trapped within the gettering site.
12. Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaoka, Yoshikazu et al. (Pub No. US 20080001214 A1) (hereinafter, Yamaoka) in view of Jerome, Rick C. et al (Pub No. US 5561073 A) (hereinafter, Jerome) and Shoyama, Toshihiro (Pub No. US 20190237495 A1) (hereinafter, Shoyama) as applied to Claim 15 above, and further in view of Morii, Katsumi et al. (Pub No. CN 102157431 A) (hereinafter, Morii).
Re Claim 18, (Original) Yamaoka in view of Jerome and Shoyama does not teach the method of claim 15, wherein the etching inhibitor is gradually thickened during etching the semiconductor layer.
In the same field of endeavor, Morii teaches the method of claim 15, wherein the etching inhibitor (Sidewall insulating film; SW; Fig 78; ¶[0239]) is gradually thickened (Gradually thickens from top to bottom; Fig 78) during etching the semiconductor layer (Semiconductor layer; SL; Fig 78; ¶[0244]). (See Fig 78 below)
Morii, Fig 78: Etching Inhibitor
PNG
media_image14.png
396
452
media_image14.png
Greyscale
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined the methods of Yamaoka, Jerome, Shoyama and Morii to gradually thicken the etching inhibitor during etching the semiconductor layer. One would have been motivated to do this with a reasonable expectation of success because forming the side wall insulating film (SW) for protects the side surface of the semiconductor layer (SL), protecting the surface of the semiconductor layer directly exposed to phosphoric acid, thereby preventing the surface of the semiconductor layer from roughening and thereby inhibiting the increase of leakage current, as suggested by Morii (¶[0244]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817