DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In view of the appeal brief filed on October 2 2025, PROSECUTION IS HEREBY REOPENED. A new
ground of rejection is set forth below.
To avoid abandonment of the application, appellant must exercise one of the following two
options:
(1) file a reply under 37 CFR 1.111 (if this Office action is non-final) or a reply under 37 CFR 1.113
(if this Office action is final); or,
(2) initiate a new appeal by filing a notice of appeal under 37 CFR 41.31 followed by an appeal
brief under 37 CFR 41.37. The previously paid notice of appeal fee and appeal brief fee can be applied to the new appeal. If, however, the appeal fees set forth in 37 CFR 41.20 have been increased since they were previously paid, then appellant must pay the difference between the increased fees and the amount previously paid.
A Supervisory Patent Examiner (SPE) has approved of reopening prosecution by signing below:
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Claim Objections
Claim 39 is objected to because of the following informalities: “printed circuit board” in claim 39 should be “circuit board”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8-9, 76, and 79-80 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2019/0348340), Negoro (US Patent 8,558,372), and Wang (US 2008/0122067).
Regarding claim 1, Kwon discloses:
A transistor package (Figure 2B), comprising:
a circuit board (500);
a transistor die (100, 100 is disclosed as a logic die, see para. [0033], which contains transistors) that has a gate terminal, a drain terminal and a source terminal (all transistors have source, gate, and drain terminals), the transistor die flip-chip mounted (see Figure 2B) so that the gate terminal and the drain terminal face the upper surface of the circuit board (500, contacts 350 face the circuit board 500, and the die 100 only has one active surface, see Figure 2B, thus at least one face of the gate and drain terminals of a transistor within die 100 would face the circuit board 500);
a heatsink (600) having a plate-like portion (601) that extends in parallel to the circuit board (500, see Figure 2B) and a plurality of legs (602) that extend downwardly from the plate-like portion (601), the heatsink (600) mounted on an upper surface of the transistor die (100, see Figure 2B) and comprising an opening (691).
a plurality of surface mount circuit elements (300, 400) mounted on the upper surface of the circuit board (500, see Figure 2B) so that the footprint of the heatsink (600) vertically overlaps at least one of the plurality of surface mount circuit elements (300, 400, see Figure 2B),
a molding material (360) that at least partially fills a space between the circuit board (500) and the heatsink (600, see Figure 3D),
wherein a first of the plurality of surface mount circuit elements (400) does not vertically overlap the transistor die (100, see Figure 2B) and extends into the opening (trench 691, see Figure 2B).
Kwon does not disclose that the opening extends completely through the heatsink.
Negoro discloses an opening (30X, Figure 2) extending completely through the heatsink (30, see Figure 2).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Negoro into the teachings of Kwon to have the opening in the heatsink extend completely through the heatsink for the purpose of allowing heat generated by components to be dissipated to the external environment (Negoro, col. 4, lines 52-55).
Note that the claim language “facing” is unclear as to specifically what surface of the drain and gate terminals must face the upper surface of the circuit board. For examination purposes, the Examiner will require that any surface of the drain and gate terminals of the transistor die must face the upper surface of the circuit board.
Kwon does not disclose that the heatsink has a first footprint that is smaller than a second footprint of the circuit board, and a molding material that is on side surfaces of at least some of the surface mount circuit elements, the molding material also covering portions of the circuit board that are exposed outside of the heatsink.
However, Wang discloses in Figure 4 a heatsink (10) has a first footprint that is smaller than a second footprint of the circuit board (30, see Figure 4), and a molding material (40) that is on side surfaces of at least some of the surface mount circuit elements (20), the molding material (40) also covering portions of the circuit board (30) that are exposed outside of the heatsink (10, see Figure 4).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Wang into the teachings of Kwon and Negoro above to include the claimed elements above for the purpose of enabling the heatsink to be held more securely by the encapsulant (Wang, para. [0029]).
Regarding claim 8, Kwon discloses wherein the heatsink (600) is directly connected to the transistor die (100) through a thermally conductive bonding material (710, para. [0039]).
Regarding claim 9, Kwon discloses wherein the heatsink (600) contacts at least one of the plurality of surface mount circuit elements (300, 400) either directly or through a thermally conductive bonding material (730, heatsink 600 contacts one of the surface mount circuit elements 300 through thermally conductive bonding materials 730).
Regarding claim 76, Kwon discloses wherein an upper surface of the first surface mount circuit element (400) does not directly contact the heatsink (600) or contact the heatsink through a conductive bonding material (Figure 2B shows no direct contact or indirect contact between the first surface mount circuit element 400 and the heatsink 600).
Regarding claim 79, Wang discloses wherein the molding material (40) further covers side surfaces of the heatsink (10, see Figure 4 which shows the molding material covering outer side surfaces of the heatsink 10, in order to securely fix the heatsink 10, para. [0029]).
Regarding claim 80, Wang discloses wherein all of the legs (of heatsink 10, here the legs are the portions of the heatsink 10 that extend vertically) are inset from outer edges of the plate-like portion of the heatsink (10, here the plate-like portions of the heatsink are the portions of the heatsink 10 that extend parallel to the circuit board 30, as claimed in claim 1, thus Wang’s lower, horizontally extending portion of the heatsink 10 that is directly connected to the circuit board is considered a plate-like portion, where the legs are inset therefrom).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon, Negoro, and Wang as applied to claim 1 above, and further in view of Kuo et al. (“Kuo” US 2022/0278058).
Regarding claim 2, Kwon does not disclose a specific height of the transistor die.
Kuo discloses wherein a height of the transistor die (100, see para. [0022], Kuo discloses that die 100 may be any of a multitude of dies that include transistors) is at least 300 microns (para. [0036], the height of die 100 may be in a range from 20 microns to 775 microns).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kuo into the teachings of Kwon, Negoro, and Wang to include the height of the transistor die being at least 300 microns because it is advantageous for device minimization to decrease the height of individual dies.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon, Negoro, and Wang as applied to claim 1 above, and further in view of Falola et al. (“Falola” US 2020/0388554) and Cheng (US 2023/0065446).
Regarding claim 25, Kwon does not disclose an integrated passive device that is mounted on the circuit board, wherein the transistor die is flip-chip mounted on the integrated passive device.
However, Falola discloses an integrated passive device (108, para. [0028] discloses interposer 108 as containing passive devices) that is mounted on the circuit board (102, shown in Figure 3A), wherein the transistor die (106-1) is flip-chip mounted on the integrated passive device (108, flip-chip mounting shown in Figure 3A).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Falola into the teachings of Kwon to include an integrated passive device that is mounted on the circuit board, wherein the transistor die is flip-chip mounted on the integrated passive device for the purpose of increasing device density (see Cheng, para. [0025] “arranging the passive devices and logic device in a stacked relationship reduces the footprint of the IC”).
Claims 26, 31, 77, and 81-82 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2019/0348340) and Wang (US 2008/0122067).
Regarding claim 26, Kwon discloses:
A transistor package (Figure 2B), comprising:
a circuit board (500);
a transistor die (100,100 is disclosed as a logic die, see para. [0033], which contains transistors) that has a gate terminal, a drain terminal and a source terminal (all transistors have source, gate, and drain terminals), the transistor die flip-chip mounted (see Figure 2B) so that the gate terminal and the drain terminal face an upper surface of the circuit board (500, contacts 350 face the circuit board 500, and the die 100 only has one active surface, see Figure 2B, thus at least one face of the gate and drain terminals of a transistor within die 100 would face the circuit board 500);
a heatsink (600) mounted above the transistor die (100), the heatsink (600) including a plate-like portion (601) that has first recess (691, see Figure 2B) formed therein, and a plurality of legs (602) that directly contact and extend downwardly from the plate-like portion (601) of the heatsink (600);
a first surface mount circuit element (400) mounted on the upper surface of the circuit board (500), the first surface mount circuit element extending into the first recess (691) in the heatsink (600) and not contacting the heatsink (600, see Figure 2B) while the transistor die (100) directly contacts the heatsink (600) or contacts the heatsink through a conductive bonding material (the transistor die 100 contacts the heatsink 600 through material 710); and
a molding material (360) that at least partially fills a space between the circuit board (500) and the heatsink (600, see Figure 3D),
Kwon does not disclose a molding material that is on side surfaces of the first surface mount circuit elements, the molding material also covering portions of the circuit board that are exposed outside of the heatsink, and wherein a first footprint of the heatsink is smaller than a second footprint of the circuit board.
However, Wang discloses in Figure 4 a molding material (40) that is on side surfaces of the first surface mount circuit element[s] (20, Figure 4), the molding material (40) also covering portions of the circuit board (30) that are exposed outside of the heatsink (10, see Figure 4), and wherein a first footprint of the heatsink (10) is smaller than a second footprint of the circuit board (30, see Figure 4). While Figure 4 of Wang shows one chip, many chips may be included such as in Figure 8 in order to increase the power of the device, para. [0035], and increase device density.
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Wang into the teachings of Kwon above to include the claimed elements above for the purpose of enabling the heatsink to be held more securely by the encapsulant (Wang, para. [0029]).
Regarding claim 31, Kwon discloses wherein a first height of the first surface mount circuit element (400, H4 in Figure 2B) is greater than or equal to a second height of the transistor die (100, H1 in Figure 2B).
Regarding claim 77, Kwon discloses wherein an upper surface of the first surface mount circuit element (400) does not directly contact the heatsink (600) or contact the heatsink (600) through a conductive bonding material (Figure 2B shows no contact, direct or indirect, between the first surface mount circuit element 400 and the heatsink 600).
Regarding claim 81, Wang discloses wherein the molding material (40) further covers side surfaces of the heatsink (10, see Figure 4, the molding material covers outer side surfaces of the heatsink 10, in order to securely fix the heatsink 10, para. [0029]).
Regarding claim 82, Wang discloses wherein all of the legs (of heatsink 10, here the legs are the portions of the heatsink 10 that extend vertically) are inset from outer edges of the plate-like portion of the heatsink (10, here the plate-like portions of the heatsink are the portions of the heatsink 10 that extend parallel to the circuit board 30, as claimed in claim 1, thus Wang’s lower, horizontally extending portion of the heatsink 10 that is directly connected to the circuit board is considered a plate-like portion, where the legs are inset therefrom).
Claims 39, 42-43, 71, 75, 78, and 83-84 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2019/0348340), Hsu et al. (“Hsu” US 2016/0172292), and Wang (US 2008/0122067).
Regarding claim 39, Kwon discloses:
A transistor package (Figure 3D), comprising:
a circuit board (500) [comprising a recessed portion];
a [transistor] die (300, 730) [mounted within the recessed portion of the circuit board];
a heatsink (600) mounted on the transistor die (300, 730) opposite the circuit board (500, see Figure 3D), the heatsink (600) including a monolithic plate-like portion (601) that extends parallel to the circuit board (500, see Figure 2B) and a plurality of legs (602) that extend downwardly from the plate-like portion (601), where a lower surface of the plate-like portion (601) includes a recess (691, 693); and
a surface mount circuit element (400) mounted on an upper surface of the circuit board (500) and extending into the recess (693, 691, see Figure 3D),
a molding material (360) that at least partially fills a space between the circuit board (500) and the heatsink (600, see Figure 3D),
wherein the transistor die (300, 730) vertically overlaps the recess (693, 691) in the plate-like portion of the heatsink (601, see Figure 3D).
Kwon does not explicitly disclose a transistor die. However, it would have been obvious to one having ordinary skill in the art to incorporate a transistor into the die 300/730 as disclosed by Kwon because they are known in the art and result in the predictable result of increasing device density.
Kwon does not disclose that the circuit board comprises a recessed portion.
However, Hsu discloses a circuit board (306) including a recessed portion (cavity 360).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Hsu into the teachings of Kwon to include a recessed portion of the circuit board and the transistor die mounted within the recessed portion of the circuit board for the purpose of reducing height (Hsu, para. [0033]). One of ordinary skill would recognize that incorporating a recessed portion of the circuit board as disclosed by Hsu into the teachings of Kwon would reduce the total height of the package and thus achieve miniaturization requirements.
Kwon does not disclose a molding material also covering portions of the printed circuit board that are exposed outside of the heatsink, and wherein a first footprint of the heatsink is smaller than a second footprint of the circuit board.
However, Wang discloses a molding material (40) also covering portions of the printed circuit board (30) that are exposed outside of the heatsink (10, see Figure 4), and wherein a first footprint of the heatsink (10) is smaller than a second footprint of the circuit board (30, see Figure 4).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Wang into the teachings of Kwon and Hsu above to include the claimed elements above for the purpose of enabling the heatsink to be held more securely by the encapsulant (Wang, para. [0029]).
Regarding claim 42, Kwon discloses wherein the heatsink (600) is directly connected to the transistor die (300, 730) through a thermally conductive bonding material (direct contact, see Figure 3D).
Regarding claim 43, Kwon further discloses a plurality of additional surface mount circuit elements (100, 200) mounted on the upper surface of the circuit board (500, see Figure 3D), wherein the heatsink (600) contacts at least one of the plurality of additional surface mount circuit elements (100, 200) either directly or through a thermally conductive bonding material (heatsink contacts 100, 200 through thermally conductive material 710, 720, respectively).
Regarding claim 71, Kwon does not explicitly show that the recess in the heat sink has curved corner regions.
However, it would have been obvious to one of ordinary skill in the art to include curved corner regions of the recess in the heat sink for improved airflow for heat dissipation as opposed to sharp corner regions, however it has been ruled that changes of shape are prima facia obvious absent persuasive evidence that the particular configuration is significant (MPEP 2144.04(IV)(B)). Applicant has not disclosed in the specification persuasive evidence that curved corner regions of the recess of the heatsink is significant to the device.
Regarding claim 75, Kwon discloses wherein the transistor die (300, 730) extends into the recess (691, 693, see Figure 3D).
Regarding claim 78, Kwon discloses wherein an upper surface of the surface mount circuit element (400) does not directly contact the heatsink (600) or contact the heatsink (600) through a conductive bonding material (see Figure 3D, there is not contact, direct or indirect, between the surface mount circuit element 400 and the heatsink 600).
Regarding claim 83, Wang discloses wherein the molding material (40) further covers side surfaces of the heatsink (10, see Figure 4 which shows the molding material covering outer side surfaces of the heatsink 10, in order to securely fix the heatsink 10, para. [0029]).
Regarding claim 84, Wang discloses wherein all of the legs (of heatsink 10, here the legs are the portions of the heatsink 10 that extend vertically) are inset from outer edges of the plate-like portion of the heatsink (10, here the plate-like portions of the heatsink are the portions of the heatsink 10 that extend parallel to the circuit board 30, as claimed in claim 1, thus Wang’s lower, horizontally extending portion of the heatsink 10 that is directly connected to the circuit board is considered a plate-like portion, where the legs are inset therefrom).
Claim 44 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon, Hsu, and Wang as applied to claim 39 above, and further in view of Kim et al. (“Kim” US 2024/0072739).
Regarding claim 44, Kwon does not explicitly disclose that the transistor die is a radio frequency transistor amplifier die.
However, Kim discloses wherein the transistor die is a radio frequency ("RF") transistor amplifier die (340, para. [0130], [0133]) that includes a gate terminal, a drain terminal and a source terminal (discussed in para. [0057] and labeled in Figure 19, present but not labeled in Figure 21), and the RF transistor amplifier die is flip-chip mounted on an upper surface of the circuit board (2110, shown in Figure 21) so that at least the gate terminal (330) and the drain terminal face (331) the upper surface of the circuit board (2110, shown in Figure 21).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Kwon, Hsu, and Wang in the manner above because incorporating an RF transistor amplifier die in accordance with the specifications and functions of a device is within the skill set of a person having ordinary skill in the art. RF amplifiers are widely used and the incorporation of one results in the predictable result of amplifying external signals.
Claim 85 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon (US 2019/0348340) and Wang (US 2008/0122067).
Regarding claim 85, Kwon discloses a transistor package (Figure 2B), comprising:
a circuit board (500);
a transistor die (100, 100 is disclosed as a logic die, see para. [0033], which contains transistors) that has a gate terminal, a drain terminal and a source terminal (all transistors have source, gate, and drain terminals), the transistor die (100) flip-chip mounted (see flip-chip mounting in Figure 2B) so that the gate terminal and the drain terminal face an upper surface of the circuit board (500, contacts 350 face the circuit board 500, and the die 100 only has one active surface, see Figure 2B, thus at least one face of the gate and drain terminals of a transistor within die 100 would face the circuit board 500);
a heatsink (600) comprising a plate-like portion (601) that extends in parallel to the circuit board (500) and a plurality of legs (602) that extend downwardly from the plate-like portion (601, see Figure 2B);
a plurality of surface mount circuit elements (300, 400) mounted on the upper surface of the circuit board (500) so that a footprint of the heatsink (600) vertically overlaps at least one of the plurality of surface mount circuit elements (300, 400, see Figure 2B);
a molding material (360) in a space between the circuit board (500) and the heatsink (600), the molding material also covering portions of the circuit board (500) and side surfaces of the heatsink (600, see molding material laterally covering side surfaces of the legs 602 of the heat sink, note that “covering” does not require direct physical contact, only that one element overlay another element in some direction).
Kwon does not disclose wherein all of the legs are inset from outer edges of the plate-like portion of the heatsink, and wherein a first footprint of the heatsink is smaller than a second footprint of the circuit board.
However, Wang discloses wherein all of the legs (of heatsink 10, here the legs are the portions of the heatsink 10 that extend vertically) are inset from outer edges of the plate-like portion of the heatsink (10, here the plate-like portions of the heatsink are the portions of the heatsink 10 that extend parallel to the circuit board 30, as claimed in claim 1, thus Wang’s lower, horizontally extending portion of the heatsink 10 that is directly connected to the circuit board is considered a plate-like portion, where the legs are inset therefrom), and wherein a first footprint of the heatsink (10) is smaller than a second footprint of the circuit board (30, see Figure 4).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Wang into the teachings of Kwon above to include the claimed elements above for the purpose of enabling the heatsink to be held more securely by the encapsulant Wang, para. [0029]) due to the shape of the heatsink and the encapsulant’s incorporation onto the shape of the heatsink as claimed and the circuit board.
Claims 86-87 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon and Wang as applied to claim 85 above, and further in view of Nomura (US 2022/0095496) as evidenced by Wang and Soller (US Patent No. 9,147,600).
Regarding claim 86, Nomura discloses in Figure 14-16 an additional surface mount circuit element (3c, Figure 16) that is mounted on the upper surface of the circuit board (1) outside of footprint of the heatsink (shielding structure 20, which would have heat dissipation capabilities due to the thermal conductivity of the materials used).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Nomura into the teachings of Kwon and Wang above to include the additional surface mount circuit element as claimed for the purpose of increasing device density by incorporating more circuit elements onto the same circuit board. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007). Further, it is the Examiner’s position that the EMI shield of Nomura can also function as a heatsink, which is evidenced by Wang. Wang discloses that the heatsink (10) can also function as an EMI shield when connected to electrical terminals of the circuit board (see para. [0034]). Thus, the shield of Nomura must also be capable of functioning as a heatsink as well, even with molding material covering the surfaces of the heatsink which does not have as much heat dissipation capabilities as the metallic material of a shield/heatsink.
Regarding claim 87, Nomura discloses wherein the molding (6a) is on the additional surface mount circuit element (3c, see Figure 16).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Nomura into the teachings of Kwon and Wang above to include the molding over the additional surface mount circuit element for the purpose of protecting the chip, as evidenced by Soller (see Soller, col. 5 lines 45-48).
Response to Arguments
The Examiner notes that the assertion that the EMI shield of Nomura should be considered as a heat sink is being maintained. See above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899
/DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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