DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/28/2025 have been fully considered but they are not persuasive or moot in view of the new grounds of rejection as detailed below as necessitated by Applicant’s claim amendments or indication of allowable subject matter.
Applicant argues on page 9 that the independent claims 1, 20, and 27 are amended to incorporate the features of indicated-allowable claims 10, 26, and 31 respectively, but this is not persuasive. Claim 10, for example, depended on claim 9 which depended on claim 8 which depended on claim 1. Claim 10 was objected to as being allowable including all of the limitations of the base claim and any intervening claims (see non-final office action mailed 05/28/2025 page 21 lines 1-4). Therefore, Applicant’s incorporating of the language from only claim 10 into claim 1 fails to incorporate the entirely of the limitations which together established the allowable subject matter.
Applicant’s arguments on page 10 with respect to the indefiniteness rejection of claims 5,28,32-35 over the scope of the term “transconductance” are persuasive and the rejection withdrawn.
Claim Objections
Claim 24 objected to because of the following informalities:
Claim 24 lines 1-2 recites “[…] wherein second Group […]” which should be “[…] wherein the second Group […]”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 7 recites wherein the multilayer barrier structure comprises a Group III-nitride based barrier structure, but claim 7 depends on claim 1 and claim 1 has been amended to recite “the multilayer barrier structure comprising a first group III-nitride layer […] and a second Group III-nitride layer” so claim 7 fails to further limit amended claim 1.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,2,6-8,17-19,21 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”.
Regarding claim 1, Bayram discloses a transistor device (e.g. FIG. 1B) comprising:
a channel layer (102, ¶ [0058]);
a multilayer barrier structure (106) on the channel layer, the multilayer barrier structure comprising a first group III-nitride layer (106B) having a thickness (t2) in a range of about 5 Angstroms to about 15 Angstroms (FIG. 3A,3b, t2 may be 1 nm = 10 Angstroms, ¶ [0072]) and a second Group III-nitride layer (106C), different from the first Group III-nitride layer, having a thickness (t3) in a range of about 70 Angstroms to about 100 Angstroms (FIG. 4A,4B t3 may be 10 nm = 100 Angstroms, ¶ [0073]).
Bayram fails to clearly teach wherein the gate contact has a gate length of about 100 nm or less and wherein a ratio of the gate length to a thickness of the multilayer barrier structure is in a range of about 8:1 to about 16:1.
Hoshi teaches optimizing Lg/a (¶ [0008],[0009]) including wherein a ratio of a gate length to a thickness of the multilayer barrier layer is in a range of about 8:1 to about 16:1 (e.g. teaches optimizing Lg/a ¶ [0008],[0009], specifically 100 nm gate ¶ [0076],[0077] and ¶ [0078],[0079] 100nm/(2.4nm+3.3nm) = 17.5 which is “about 16:1 and also teaches values of the electron-supply layer 50 to be thinner than or equal to 5 nm ¶ [0064] and 100nm/(2.4nm+5nm) = 13.5 which falls within claimed range of 8:1 to 16:1 since 13.5 < 16).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram with the thicknesses and gate length ratios as claimed as suggested by the overlapping ranges of Bayram and optimization of Lg/a taught by Hoshi and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the gate length to barrier thickness determines electrical characteristics such as resistance to short channel effects (¶ [0058],[0007]-[0009]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 2, although Bayram in view of Hoshi yields the transistor device of claim 1, Bayram and Hoshi fail to clearly teach with sufficient specificity for anticipation (MPEP 2131.03) wherein the ratio of the gate length to the thickness of the multilayer barrier structure is in a range of about 8:1 to 12:1.
However Hoshi teaches optimizing Lg/a ¶ [0008],[0009], specifically 100 nm gate ¶ [0076],[0077] and ¶ [0078],[0079] 100nm/(2.4nm+3.3nm) = 17.5 which is about 16:1, but also teaches values of the electron-supply layer 50 to be thinner than or equal to 5 nm ¶ [0064] and 100nm/(2.4nm+5nm) = 13.5 which is about within the claimed range of 8:1 to 12:1).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with the ratio of gate length to thickness of the multilayer barrier structure as generally taught by Hoshi since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the gate length to barrier thickness determines electrical characteristics such as resistance to short channel effects (¶ [0058],[0007]-[0009]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 6, although Bayram in view of Hoshi yields the transistor device of claim 1, Bayram fails to teach in sufficient specificity for anticipation (MPEP 2131.03) wherein the multilayer barrier structure has a peak thickness in a range of about 50 Angstroms to about 120 Angstroms.
However, Bayram generally teaches wherein the multilayer barrier layer has a thickness (t1 + t2 + t3) with a lower bound for t1 = 1 nm (FIG. 2A,2B), a lower bound for t2 = 1nm (FIG. 3A,3C) and a lower bound for t3 = 5 nm (FIG. 4A,4B) which yields 1nm+1m+5m=7nm = 70 Angstroms which falls within the claimed range, and that the multilayer barrier structure should have a peak thickness (hc) sufficiently low in order to maximize turn-on voltage (¶ [0063]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with the peak thickness within the claimed range as suggested by Bayram in order to maximize turn-on voltage (Bayram ¶ [0063]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the peak thickness determines electrical characteristics of the transistor such as the turn-on voltage (Bayram ¶ [0063], FIG. 7, ¶ [0077]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 7, Bayram in view of Hoshi yields the transistor device of claim 1, and Bayram further teaches wherein the multilayer barrier structure comprises a Group III-nitride based barrier structure (AlGaN layers, Abstract).
Regarding claim 8, Bayram in view of Hoshi yields the transistor device of claim 1, and Bayram further teaches (FIG. 1B) wherein the second Group III-nitride layer (106C) is over the first Group III-nitride layer (106B).
Regarding claim 17, Bayram in view of Hoshi yields the transistor device of claim 1, and Hoshi further discloses wherein a ratio of the gate length to a distance between the gate contact and the channel layer is in a range of about 8:1 to about 16:1 (same as claim 1, since Hoshi teaches optimizing Lg/a ¶ [0008],[0009], specifically 100 nm gate ¶ [0076],[0077] and ¶ [0078],[0079] 100nm/(2.4nm+3.3nm) = 17.5 which is “about” 16:1 since it is close, but also teaches values of the electron-supply layer 50 to be thinner than or equal to 5 nm ¶ [0064] and 100nm/(2.4nm+5nm) = 13.5 which is within the claimed range and/or overlaps with sufficient specificity for anticipation, MPEP 2131.03).
Bayram fails to clearly teach a cap layer adjacent the gate contact.
Hoshi further discloses wherein the transistor device further comprises a cap layer (90, ¶ [0048]) adjacent the gate contact (80).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with a cap layer as taught by Hoshi in order to prevent the oxidation of the underlying barrier layer (Hoshi ¶ [0053]).
Regarding claim 18, Bayram in view of Hoshi yields the transistor device of claim 1, and Bayram further teaches wherein the transistor device is a high electron mobility transistor device (¶ [0004]) and Hoshi further discloses wherein the transistor device is a high electron mobility transistor device (Title).
Regarding claim 19, although Bayram in view of Hoshi yields the transistor device of claim 1, Bayram fails to clearly teach wherein the channel layer is on a silicon carbide substrate.
Hoshi further discloses wherein the channel layer is on a silicon carbide substrate (20, ¶ [0050]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram on a silicon carbide substrate as exemplified by Hoshi since it has been held in KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) that exemplary rationales that may support a conclusion of obviousness include:
(A) Combining prior art elements according to known methods to yield predictable results;
(B) Simple substitution of one known element for another to obtain predictable results;
(C) Use of known technique to improve similar devices (methods, or products) in the same way;
(D) Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results;
(E) “Obvious to try” – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success;
(F) Known work in one field of endeavor may prompt variations of it for use in either the same field or a different one based on design incentives or other market forces if the variations are predictable to one of ordinary skill in the art;
(G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention,
Wherein in the instant case one having ordinary skill in the art would have been able to and would have found it obvious to (b) substitute a silicon carbide as used in a conventional heterojunction field effect transistor (Hoshi ¶ [0050]) under the gallium nitride layer and forming the bulk substrate of Bayram with the predictable and desired result of forming a suitable semiconductor substrate material.
Regarding claim 21, although Bayram generally yields the transistor device of claim 20, Bayram fails to clearly teach wherein a gate length of the gate contact is about 100 nm or less.
Hoshi teaches wherein a gate length of the gate contact is 100 nm (100 nm gate ¶ [0076],[0077] and ¶ [0078],[0079]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram with the gate length as taught by Hoshi in the process of optimizing Lg/a (Hoshi ¶ [0008],[0009]) since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case
the gate length determines in part the electrical characteristics such as resistance to short channel effects (Hoshi ¶ [0058],[0007]-[0009]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”, further in view of U.S. Patent Application Publication Number 2009/0212324 A1 to Tamai et al., “Tamai”.
Regarding claim 3, although Bayram in view of Hoshi yields the transistor device of claim 1 and Hoshi teaches wherein a 25 nm electron supply layer produces an electron mobility electron mobility of 1500 cm2/Vs (¶ [0005]), Bayram and Hoshi fails to clearly teach with sufficient specificity for anticipation (MPEP 2131.03) wherein a two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has an electron mobility in a range of about 800 cm2/Vs to about 2500 cm2/Vs together with all of the limitations of claim 1 as claimed.
Tamai teaches wherein the AlGaN/GaN heterostructure achieves approximate mobility vales of 1500 cm2/Vs and that very thin Group III-nitride barrier layers (e.g. AlN) can produce a mobility of 1226.8 cm2/Vs (¶ [0065]) and that the mobility is determined in part by barrier layer thickness (FIG. 7, ¶ [0068]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram and Hoshi with the mobility within the claimed range as suggested by Hoshi and as taught by Tamai in order to desirably achieve high mobility for high frequency applications without short channel effects (Tamai ¶ [0068],[0069],[0008],[0009],[0072],[0073]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the carrier mobility determines the capable operating frequencies making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”, further in view of U.S. Patent Application Publication Number 2024/0363745 A1 to Gupta et al., “Gupta”.
Regarding claim 4, although Bayram in view of Hoshi yields the transistor device of claim 1, Bayram and Hoshi fail to clearly state wherein a two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has a carrier concentration in a range of about 1.2 x 10^13 cm-2 to about 2.0 x 10^13 cm-2.
Gupta teaches a multilayer barrier structure which has a 2DEG carrier (electron) concentrations (FIG. 14A, ¶ [0122]) within the range of 1.2 x 10^13 cm-2 to 1.5 x 10^13 cm-2 which falls within the claimed range.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with the sheet carrier concentration within the claimed range as suggested by the overlapping range of Gupta in the process of optimizing growth conditions to achieve high mobility (Gupta ¶ [0122]-[0129]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the carrier concentration determines the operating characteristics of the transistor making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”, further in view of U.S. Patent Application Publication Number 2011/0241020 A1 to Saunier, “Saunier”.
Regarding claim 5, although Bayram in view of Hoshi yields the transistor device of claim 1, it is unclear whether the structure Bayram or Hoshi achieves the function of wherein the two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has a transconductance in a range of about 500 mS/mm to about 800 mS/mm.
Saunier teaches optimizing the specific dimensions of various layers to achieve a relatively high or maximum transconductance of about 800 mS/mm (¶ [0024]) or exhibit relatively superior (e.g. desirable) operating characteristics including a transconductance of about 600 mS/mm (¶ [0032]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi by optimizing the transconductance to within the claimed range as taught by the values of Saunier in order to allow relatively high current and relatively low access resistance (Saunier ¶ [0023]) in order to achieve various voltages for pinch-off voltage, transconductance, and/or current density (Saunier ¶ [0024]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”, further in view of U.S. Patent Application Publication Number 2022/0320326 A1 to Cheng, “Cheng”.
Regarding claim 13, although Bayram in view of Hoshi yields the transistor device of claim 7, Bayram and Hoshi fail to clearly teach wherein the multilayer barrier structure comprises a plurality Group III-nitride layers arranged in an alternating manner.
Cheng teaches a plurality of Group III-nitride barrier layers (e.g. FIG. 6 layers 141,142,143,144, ¶ [0055], or FIG. 10 layers 141, 142, 143, 144, 145, 146, ¶ [0060]) arranged in an alternating matter.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with alternating barrier layers as taught by Cheng in order to from quantum wells which avoid forward leakage (Cheng ¶ [0055],[0056],[0060]).
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”, as applied to claim 1 above, and further in view of U.S. Patent Application Publication Number 2021/0257486 A1 to Wong, “Wong”.
Regarding claims 14 and 15, although Bayram in view of Hoshi yields the transistor device of claim 1, Hoshi fails to clearly teach (claim 14) wherein the gate length of the gate contact is in a range of about 40 nm to about 90 nm, or (claim 15) wherein the gate length of the gate contact is in a range of about 60 nm to about 90 nm.
Wong teaches an improved gate contact, wherein a length of a gate contact (L2) is shortened to from 40 nm to 60 nm or from 60 nm to 80 nm (¶ [0047]), which overlaps the claimed ranges with sufficient specificity for anticipation (MPEP 2131.03).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with the improved gate contact having the gate length within the claimed ranges as taught by Wong in order to allow for the transistor to operate at higher frequencies (Wong ¶ [0128],[0129],[0157],[0002]-[0004]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2009/0045439 A1 to Hoshi et al., “Hoshi”, as applied to claim 1 above, and further in view of U.S. Patent Number 6,849,882 B2 to Chavarkar et al., “Chavarkar”.
Regarding claim 16, Bayram in view of Hoshi yields the transistor device of claim 1, and Hoshi further discloses wherein a ratio of the gate length to a distance between the gate contact and the channel layer is in a range of about 8:1 to about 16:1 (teaches optimizing Lg/a ¶ [0008],[0009], specifically 100 nm gate ¶ [0076],[0077] and ¶ [0078],[0079] 100nm/(2.4nm+3.3nm) = 17.5 which is “about” 16:1 since it is close, but also teaches values of the electron-supply layer 50 to be thinner than or equal to 5 nm ¶ [0064] and 100nm/(2.4nm+5nm) = 13.5 which is within the claimed range and/or overlaps with sufficient specificity for anticipation, MPEP 2131.03).
Bayram and Hoshi fail to clearly teach wherein the gate contact is recessed into the multilayer barrier structure.
Chavarkar teaches (FIG. 6) wherein a gate contact (“G” 94) is recessed (column 6 lines 20-40) into a multilayer barrier structure (86, 96).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with a recessed gate as taught by Chavarkar in order to desirably form an increased resistance under the gate as compared to the source/drain regions (Chavarkar column 6 lines 20-40).
Claims 20,23,24 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”.
Regarding claim 20, Bayram discloses a transistor device (e.g. FIG. 1B) comprising:
a channel layer (102, ¶ [0058]);
a group III-nitride based barrier structure (106) on the channel layer, the Group III-nitride based barrier structure comprising a first Group III-nitride layer (106B) having a thickness (t2) in a range of about 5 Angstroms to about 15 Angstroms (FIG. 3A,3b, t2 may be 1 nm = 10 Angstroms, ¶ [0072]) and a second Group III-nitride layer (106C), different than the first Group III-nitride layer, having a thickness (t3) in a range of about 70 Angstroms to about 100 Angstroms (FIG. 4A,4B t3 may be 10 nm = 100 Angstroms, ¶ [0073]); and
a gate contact (112, ¶ [0056]).
Bayram fails to teach in sufficient specificity for anticipation (MPEP 2131.03) wherein the multilayer barrier structure has a peak thickness of less than 120 Angstroms.
However, Bayram generally teaches wherein the multilayer barrier layer has a thickness (t1 + t2 + t3) with a lower bound for t1 = 1 nm (FIG. 2A,2B), a lower bound for t2 = 1nm (FIG. 3A,3C) and a lower bound for t3 = 5 nm (FIG. 4A,4B) which yields 1nm+1m+5m=7nm = 70 Angstroms which falls within the claimed range. Furthermore, Bayram teaches that the multilayer barrier structure should have a peak thickness (hc) sufficiently low in order to maximize turn-on voltage (¶ [0063]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram with the peak thickness within the claimed range as suggested by Bayram in order to maximize turn-on voltage (Bayram ¶ [0063]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the peak thickness determines electrical characteristics of the transistor such as the turn-on voltage (Bayram ¶ [0063], FIG. 7, ¶ [0077]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 23, although Bayram generally yields the transistor device of claim 20, Bayram fails to clearly teach in sufficient specificity for anticipation (MPEP 2131.03) wherein the peak thickness of the Group III-nitride based barrier structure is in a range of about 50 Angstroms to about 120 Angstroms.
However, Bayram generally teaches wherein the multilayer barrier layer has a thickness (t1 + t2 + t3) with a lower bound for t1 = 1 nm (FIG. 2A,2B), a lower bound for t2 = 1nm (FIG. 3A,3C) and a lower bound for t3 = 5 nm (FIG. 4A,4B) which yields 1nm+1m+5m=7nm = 70 Angstroms which falls within the claimed range, and that the multilayer barrier structure should have a peak thickness (hc) sufficiently low in order to maximize turn-on voltage (¶ [0063]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram in view of Hoshi with the peak thickness within the claimed range as suggested by Bayram in order to maximize turn-on voltage (Bayram ¶ [0063]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the peak thickness determines electrical characteristics of the transistor such as the turn-on voltage (Bayram ¶ [0063], FIG. 7, ¶ [0077]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 24, Bayram generally yields the transistor device of claim 20, and Bayram further teaches wherein the second Group III-nitride layer (106C) is over the first Group III-nitride layer (106B).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, in view of U.S. Patent Application Publication Number 2021/0257486 A1 to Wong, “Wong”.
Regarding claim 22, although Bayram generally yields the transistor device of claim 20, Bayram fails to clearly teach wherein a gate length of the gate contact is in a range of about 60 nm to about 90 nm.
Wong teaches an improved gate contact, wherein a length of a gate contact (L2) is shortened to from 40 nm to 60 nm or from 60 nm to 80 nm (¶ [0047]), which overlaps the claimed ranges with sufficient specificity for anticipation (MPEP 2131.03).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Bayram with the improved gate contact having the gate length within the claimed ranges as taught by Wong in order to allow for the transistor to operate at higher frequencies (Wong ¶ [0128],[0129],[0157],[0002]-[0004]).
Claims 27,29-30 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Number 6,849,882 B2 to Chavarkar et al., “Charvarkar”, in view of U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, further in view of U.S. Patent Application Publication Number 2021/0257486 A1 to Wong, “Wong”.
Regarding claim 27, Charvarkar discloses a transistor device (e.g. FIG. 2), comprising:
a channel layer (“GaN” 26, column 4 lines 18-23);
a barrier structure (AlGaN layers 28 and 30, column 4 lines 24-46) on the channel layer, the barrier structure comprising an AlN layer (layer 28 when y=1) and an AlGaN layer (30); and
a two-dimensional electron gas (2DEG) at an interface between the channel layer and the barrier structure, the 2DEG having an electron mobility in a range of about 800 cm2/Vs to about 2500 cm2/Vs (“2195 cm2/Vs.” column 5 line 4).
Charvarkar fails to clearly anticipate wherein the AlN layer (28) having a thickness in a range of 5 Angstroms to 15 Angstroms, and the AlGaN layer has a thickness in a range of about 70 Angstroms to about 100 Angstroms.
Bayram teaches a first group III-nitride layer (106B) having a thickness (t2) in a range of about 5 Angstroms to about 15 Angstroms (FIG. 3A,3b, t2 may be 1 nm = 10 Angstroms, ¶ [0072]) and a second Group III-nitride layer (106C), different from the first Group III-nitride layer, having a thickness (t3) in a range of about 70 Angstroms to about 100 Angstroms (FIG. 4A,4B t3 may be 10 nm = 100 Angstroms, ¶ [0073]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar with the thicknesses within the claimed ranges as suggested by Bayram in order to control and tune the conduction band energy (FIG. 3A,4A) and resulting electron concentration (FIG. 3B,4B) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thicknesses determine the resulting electrical characteristics such as the electron concentration making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Charvarkar fails to clearly teach the gate contact having a gate length in a range of about 60 nm to about 100 nm.
Wong teaches an improved gate contact, wherein a length of a gate contact (L2) is shortened to from 60 nm to 80 nm (¶ [0047]), which overlaps the claimed ranges with sufficient specificity for anticipation (MPEP 2131.03).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar with the improved gate contact having the gate length within the claimed ranges as taught by Wong in order to allow for the transistor to operate at higher frequencies (Wong ¶ [0128],[0129],[0157],[0002]-[0004]).
Regarding claim 29, although Charvarkar in view of Bayram and Wong yields the transistor device of claim 27, Charvarkar fails to clearly teach wherein a peak thickness of the barrier structure is in a range of about 50 Angstroms to 120 Angstroms.
Bayram fails to teach in sufficient specificity for anticipation (MPEP 2131.03) wherein the multilayer barrier structure has a peak thickness of less than 120 Angstroms.
However, Bayram generally teaches wherein the multilayer barrier layer has a thickness (t1 + t2 + t3) with a lower bound for t1 = 1 nm (FIG. 2A,2B), a lower bound for t2 = 1nm (FIG. 3A,3C) and a lower bound for t3 = 5 nm (FIG. 4A,4B) which yields 1nm+1m+5m=7nm = 70 Angstroms which falls within the claimed range. Furthermore, Bayram teaches that the multilayer barrier structure should have a peak thickness (hc) sufficiently low in order to maximize turn-on voltage (¶ [0063]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar in view of Bayram and Wong with the peak thickness within the claimed range as suggested by Bayram in order to maximize turn-on voltage (Bayram ¶ [0063]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the peak thickness determines electrical characteristics of the transistor such as the turn-on voltage (Bayram ¶ [0063], FIG. 7, ¶ [0077]) making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 30, Charvarkar in view of Bayram and Wong yields the transistor device of claim 27, Charvarkar further teaches wherein the AlGaN layer (30) is over the AlN layer (28 when y=1), the AlGaN layer having an aluminum mole fraction of about 30% or greater (e.g. x=.33 column 4 line 44).
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Number 6,849,882 B2 to Chavarkar et al., “Charvarkar”, in view of U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, further in view of U.S. Patent Application Publication Number 2021/0257486 A1 to Wong, “Wong”, further in view of U.S. Patent Application Publication Number 2011/0241020 A1 to Saunier, “Saunier”.
Regarding claim 28, although Charvarkar in view of Bayram and Wong yields the transistor of claim 27, it is unclear whether the structure Charvarkar achieves the function of wherein the two-dimensional electron gas (2DEG) at an interface between the channel layer and the multilayer barrier structure has a transconductance in a range of about 500 mS/mm to about 800 mS/mm.
Saunier teaches optimizing the specific dimensions of various layers to achieve a relatively high or maximum transconductance of about 800 mS/mm (¶ [0024]) or exhibit relatively superior (e.g. desirable) operating characteristics including a transconductance of about 600 mS/mm (¶ [0032]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar in view of Bayram and Wong by optimizing the transconductance to within the claimed range as taught by the values of Saunier in order to allow relatively high current and relatively low access resistance (Saunier ¶ [0023]) in order to achieve various voltages for pinch-off voltage, transconductance, and/or current density (Saunier ¶ [0024]).
Claims 32 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Number 6,849,882 B2 to Chavarkar et al., “Charvarkar”, in view of U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, further in view of U.S. Patent Application Publication Number 2011/0241020 A1 to Saunier, “Saunier”.
Regarding claim 32, Charvarkar disloses a transistor device (e.g. FIG. 2), comprising:
a channel layer (“GaN” 26, column 4 lines 18-23);
a barrier structure on the channel layer, the barrier structure comprising an AlN layer (28 when y=1 column 4 lines 24-46) and an AlGaN layer (30) having a thickness in a range of about 70 Angstroms to about 100 Angstroms; and
a two-dimensional electron gas (2DEG) at an interface between the channel layer and the barrier structure (dashed 2DEG line).
Charvarkar fails to clearly teach wherein the AlN layer (28 when y=1) has a thickness in a range of 5 Angstroms to 15 Angstroms, and the AlGaN layer (30) has a thickness in a range of about 70 Angstroms to about 100 Angstroms, wherein a peak thickness of the barrier structure is in a range of about 50 Angstroms to about 120 Angstroms.
Bayram teaches a first group III-nitride layer (106B) having a thickness (t2) in a range of about 5 Angstroms to about 15 Angstroms (FIG. 3A,3b, t2 may be 1 nm = 10 Angstroms, ¶ [0072]) and a second Group III-nitride layer (106C), different from the first Group III-nitride layer, having a thickness (t3) in a range of about 70 Angstroms to about 100 Angstroms (FIG. 4A,4B t3 may be 10 nm = 100 Angstroms, ¶ [0073]), wherein the multilayer barrier layer has a thickness (t1 + t2 + t3) with a lower bound for t1 = 1 nm (FIG. 2A,2B), a lower bound for t2 = 1nm (FIG. 3A,3C) and a lower bound for t3 = 5 nm (FIG. 4A,4B) which yields 1nm+1m+5m=7nm = 70 Angstroms which falls within the claimed range. Furthermore, Bayram teaches that the multilayer barrier structure should have a peak thickness (hc) sufficiently low in order to maximize turn-on voltage (¶ [0063]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar with the thicknesses within the claimed ranges as suggested by Bayram in order to control and tune the conduction band energy (FIG. 3A,4A) and resulting electron concentration (FIG. 3B,4B) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thicknesses determine the resulting electrical characteristics such as the electron concentration making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
It is unclear whether the structure of Charvarkar achieves the function of wherein the 2DEG having a transconductance in a range of about 500 mS/mm to about 800 mS/mm.
Saunier teaches optimizing the specific dimensions of various layers to achieve a relatively high or maximum transconductance of about 800 mS/mm (¶ [0024]) or exhibit relatively superior (e.g. desirable) operating characteristics including a transconductance of about 600 mS/mm (¶ [0032]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar and Bayram by optimizing the transconductance to within the claimed range as taught by the values of Saunier in order to allow relatively high current and relatively low access resistance (Saunier ¶ [0023]) in order to achieve various voltages for pinch-off voltage, transconductance, and/or current density (Saunier ¶ [0024]).
Regarding claim 34, Charvarkar in view of Bayram and Saunier yields transistor device of claim 32, and Charvarkar further teaches wherein the AlGaN layer (30) is over the AlN layer (28 when y=1), the AlGaN layer having an aluminum mole fraction of about 30% or greater (e.g. x=.33 column 4 line 44).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Number 6,849,882 B2 to Chavarkar et al., “Charvarkar”, in view of U.S. Patent Application Publication Number 2018/0083133 A1 to Bayram et al., “Bayram”, and U.S. Patent Application Publication Number 2011/0241020 A1 to Saunier, “Saunier”., further in view of U.S. Patent Application Publication Number 2021/0257486 A1 to Wong, “Wong”.
Regarding claim 33, although Charvarkar in view of Bayram and Saunier yields the transistor device of claim 32, Charvarkar fails to clearly teach the gate contact having a gate length in a range of about 60 nm to about 90 nm.
Wong teaches an improved gate contact, wherein a length of a gate contact (L2) is shortened to from 60 nm to 80 nm (¶ [0047]), which overlaps the claimed ranges with sufficient specificity for anticipation (MPEP 2131.03).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Charvarkar in view of Bayram and Saunier with the improved gate contact having the gate length within the claimed ranges as taught by Wong in order to allow for the transistor to operate at higher frequencies (Wong ¶ [0128],[0129],[0157],[0002]-[0004]).
Allowable Subject Matter
Claims 9,11,12,25 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891