DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/3/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. No. 2014/0252368) in view of Suvorov (US Pub. No. 2011/0092057) and Johnson (US Pub. No. 2006/0270140).
As to the interpretation of claim 1, the claim recites “a hole injection buffer layer (HIBL) comprises a silicon layer.” The present application discloses forming the HIBL by “conduct[ing] an ion implantation process to inject silicon atoms into part of the p-type semiconductor layer for transforming part of the p-type semiconductor layer into a HIBL made of silicon,” (paragraph [0017]). The claimed silicon layer is therefore being interpreted as a layer that has been implanted with silicon.
As to the rejection of claim 1 over the prior art, in FIGs. 3 and 7A-7F, Lee discloses a method for fabricating a high electron mobility transistor (HEMT), comprising: forming a buffer layer (115, paragraph [0036]) on a substrate (110, paragraph [0034]); forming a barrier layer (140, paragraph [0041]) on the buffer layer; forming a p-type semiconductor layer (160, GaN or AlGaN, paragraphs [0034] and [0052]) on the barrier layer; forming a passivation layer (174, paragraph [0080]) on and directly contacting the p-type semiconductor layer and the barrier layer (etch stop 150 is optional and may not be formed, paragraph [0044]); forming a hole injection buffer layer (HIBL) (162, paragraph [0058]) on the p-type semiconductor layer; and forming a gate electrode (186,paragraph [0034]) on the HIBL. Lee discloses that the HIBL is a nitride-based semiconductor layer doped with an n-type dopant such as silicon (paragraph [0058]).
Lee appears not to explicitly disclose that the HIBL is formed by performing an ion implantation process to implant silicon atoms into the p-type semiconductor layer to form a hole injection buffer layer (HIBL) comprising a silicon layer for neutralizing magnesium acceptors on a surface of the p-type semiconductor layer, wherein the silicon atoms of the ion implantation process are not implanted into the barrier layer and the buffer layer.
The art however well recognized ion implanting silicon into a nitride-based layer to be suitable for forming n-type doped regions in a nitride-based semiconductor layer. See, for example, Suvorov, paragraph [0045], last line.
According to well-established patent law precedents (see, for example, M.P.E.P. § 2144.07), therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have implanted silicon into the Lee disclosed GaN or AlGaN layer (or “p-type semiconductor layer”) for its recognized suitability for forming n-type doped regions in a nitride-based layer. In doing so, the silicon atoms of the ion implantation process are not implanted into the barrier layer and the buffer layer (Lee does not disclose silicon atoms are present in the barrier layer and the buffer layer; Suvorov broadly discloses implanting silicon dopant atoms into only a desired region of a nitride-based semiconductor to form an n-doped region by masking areas where silicon atoms are not desired).
However, if the combination of references is interpreted so narrowly as to not disclose implantation of a dopant species into only a top surface of a gate electrode (or “p-type semiconductor layer”), this feature would nonetheless be obvious.
In FIG. 11, Johnson discloses a process for implanting a desired dopant species (216) into only the top surface of a gate electrode (206) by masking the areas where the dopant species is not desired.
To implant silicon atoms into only the p-type semiconductor layer it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have implanted silicon into only the top surface of the p-type semiconductor layer by masking the surrounding area where the silicon dopant atoms are not desired. In doing so, the silicon atoms of the ion implantation process are not implanted into the barrier layer and the buffer layer.
Regarding claim 2, the combination of Lee, Suvorov, and Johnson discloses (see Lee FIGs. 3 and 7A-7F), patterning the p-type semiconductor layer (FIGs. 7C-7D); forming the passivation layer (174, paragraph [0080]) on the p-type semiconductor layer; performing the ion implantation process to form the HIBL on the p-type semiconductor layer; patterning the passivation layer to expose the HIBL (FIG. 7E); forming the gate electrode on the HIBL (FIG. 7F); and forming a source electrode (182) and a drain electrode (184) adjacent to two sides of the gate electrode (FIG. 7F).
Regarding claim 4, the combination of Lee, Suvorov, and Johnson discloses (see Lee FIG. 3) that a thickness of the silicon layer is less than a thickness of the p-type semiconductor layer.
Regarding claim 5, in FIGs. 3 and 7A-7F, Lee discloses that the buffer layer comprises gallium nitride (GaN) (paragraph [0036]).
Regarding claim 6, in FIGs. 3 and 7A-7F, Lee discloses that the barrier layer comprise AlxGa1-xN (paragraph [0041]).
Regarding claim 7, in FIGs. 3 and 7A-7F, Lee discloses that the p-type semiconductor layer comprises p-type gallium nitride (pGaN) (paragraphs [0034] and [0052]).
Response to Arguments
Applicant's arguments filed 11/3/2025 (“Reply”) have been fully considered but they are not persuasive.
Regarding the 10/3/2025 interview, Applicant contends that:
During the discussion, the Examiner referred to the condition “wherein the ion implantation process is performed exclusively in the p-type semiconductor layer” and indicated that such limitation corresponded to a portion not elected during a prior restriction requirement.
The Applicant respectfully clarifies that this interpretation does not reflect the actual prosecution history. According to the original filing dated September 23, 2022, the present application did not undergo any restriction requirement, and no claims were withdrawn. (see page 4 of the Reply)
This argument is not persuasive. During the interview, Examiner noted that the originally examined claims appear to be directed to the embodiment shown in FIGs. 4-5 wherein the ion implantation is performed on the p-type layer (claim 1) and then the p-type layer is pattered (claim 2). However, the amendment proposed during the interview appeared to limit the claims to the embodiment shown in FIGs. 1- 3 wherein the p-type layer is patterned and then the ion implantation is performed exclusively in the p-type layer. Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Examiner noted that claims of the proposed amendment would be withdrawn from consideration as being directed to a non-elected invention. See MPEP § 821.03.
Regarding the rejection of claim 1, Applicant contends that the Suvorov reference does not anticipate or render obvious the amended feature of selectively implanting only the p-type layer while excluding the barrier and buffer layers at least because Suvorov expressly teaches implantation into the barrier and buffer regions rather than avoiding them.
This argument is not persuasive. Suvorov is cited for the broad disclosure of implanting silicon dopant atoms into only a desired region of a nitride-based semiconductor to form an n-doped region by masking areas where silicon atoms are not desired. When applied to the structure of Lee, one of ordinary skill in the art would only be motivated to dope the p-type semiconductor layer with silicon dopant atoms (Lee discloses forming the n-type semiconductor layer 162 in only the upper portion of the p-type semiconductor layer 160).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/Primary Examiner, Art Unit 2891