Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 10/16/2025 has been entered.
Specification Objection Withdrawal
Applicant’ amendment of the title of the invention is acknowledged. Thus, the objection to specification is withdrawn.
Claim Rejections – 35 U.S.C. 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AlA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1, 16, 21 and 22 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Patent Pub. No. 2022/0262425).
Regarding Claim 1
FIG. 5 of Kim discloses a semiconductor memory device, comprising: a substrate (110); a plurality of layers vertically stacked over the substrate, wherein the plurality of layers includes a first layer (L) and a second layer (U) vertically stacked over the first layer, each of the first layer and the second layer comprises an active region (ACT) extending in a first direction parallel to a top surface of the substrate, wherein the active region includes a first source/drain region, a channel region and a second source/drain region; a first conductive line (BL) vertically extending in a second direction perpendicular to the top surface of the substrate and penetrating through the second source/drain region of the active region of the first layer and the second source/drain region of the active region of the second layer, wherein each of the first layer and the second layer further comprises a second conductive line (WL, FIG. 4) extending in a third direction that is parallel to the top surface of the substrate; a third conductive line (PL) vertically extending in the second direction and penetrating through the first source/drain region of the active region of the first layer and the first source/drain region of the active region of the second layer; and a capacitor (C) comprising a first electrode (N1) that is disposed in the active region of the first layer.
Regarding Claim 16
FIG. 5 of Kim discloses a semiconductor memory device, comprising: a first active region (lower ACT) and a second active region (upper ACT) vertically stacked over the first active region, each of the first active region and the second active region including a first source/drain region, a first channel region, a second source/drain region, a second channel region, and a third source/drain region sequentially arranged in a first direction; a bit line (BL) vertically penetrating through and electrically connected to the second source/drain region of the first active region; a dielectric tube (N3) continuously extending through the first source/drain region of the first active region and the first source/drain region of the second active region; a first capacitor (lower C) disposed in the first source/drain region of the first active region, wherein the first capacitor comprises a capacitor dielectric layer that includes a portion of the dielectric tube; and a second capacitor (upper C) disposed in the third source/drain region of the first active region.
Regarding Claim 21
FIG. 5 of Kim discloses the channel region of the active region of the first layer (lower) is connected to the channel region of the active region of the second layer (upper) through (BL) a semiconductor feature [0108].
Regarding Claim 22
FIG. 5 of Kim discloses the active region of the first layer, the active region of the second layer and the semiconductor feature are made of a continuous semiconductor material [0093, 0108].
Claim Rejections – 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4, 5, 9 and 10 rejected under 35 U.S.C. 103 as being unpatentable over Lee (U.S. Patent Pub. No. 2023/0328964) of record, in view of Jang (KR 20090120688, machine-translation provided), in view of Onuki (U.S. Patent Pub. No. 2016/0336057).
Regarding Claim 1
FIG. 8 of Lee discloses a semiconductor memory device, comprising: a substrate (1); a plurality of layers vertically stacked over the substrate, wherein the plurality of layers includes a first layer and second layer vertical stacked over the first layer, each of the first layer and the second layer comprises an active region (20) extending in a first direction parallel to a top surface of the substrate, wherein the active region includes a first source/drain region, a channel region and a second source/drain region (FIG. 15) [0110]; a first conductive line (40a, FIG. 4A) vertically extending in a second direction perpendicular to the top surface of the substrate and penetrating through the second source/drain region of the active region of the first layer and the second source/drain region of the active region of the first layer; a third conductive line (40b) vertically extending in the second direction and penetrating through the active region of the second layer [0052]; and a capacitor (70) comprising a first electrode (50a) that is disposed in the active region of the first layer.
Lee is silent with respect to a first conductive line “penetrating through the active region of the first layer and the active region of the second layer”; “each of the first layer and the second layer further comprises a second conductive line extending in a third direction that is parallel to the top surface of the substrate”; and a third conductive line “penetrating through the active region of the first layer and the active region of the second layer”.
FIG. 4 of Jang discloses a similar semiconductor memory device, comprising a second layer (_1) vertical stacked over the first layer (_2); a first conductive line (right 112) penetrating through the active region (110) of the first layer and the active region of the second layer; and a third conductive line (left 112) penetrating through the active region of the first layer and the active region of the second layer [0058].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Jang. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of improving device reliability (Abstract of Jang).
Lee as modified by Jang is silent with respect to “each of the first layer and the second layer further comprises a second conductive line extending in a third direction that is parallel to the top surface of the substrate”.
FIG. 8 of Onuki discloses a similar semiconductor memory device, wherein each of the first layer and the second layer further comprises a second conductive line (CL) extending in a third direction that is parallel to the top surface of the substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Onuki. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of storing multi-level data with low power consumption and reduced area ([0007] of Onuki).
Regarding Claim 4
FIG. 11 of Lee discloses each of the first layer and the second layer further comprises: a first gate electrode layer (38) connected to the second conductive line and electrically coupled to a first side of the channel region of the active region.
Regarding Claim 5
FIG. 11 of Lee discloses the first layer further comprises: a second gate electrode layer (38) connected to the second conductive line and electrically coupled to a first side of the channel region of the active region.
Regarding Claim 9
FIG. 4 of Lee discloses a semiconductor memory device, comprising: a plurality of memory cell transistors (MCT) vertically stacked over a substrate (1), each of the memory cell transistors comprising an active region (20) and a gate electrode layer (38); a first conductive line (40) vertically extending in a first direction perpendicular to a top surface of the substrate and penetrating through first source/drain regions of the plurality of active regions; and a plurality of second conductive lines extending in a second direction parallel to the top surface of the substrate, wherein in a plan view (FIG. 4B), each of the active region has a first sidewall, a second sidewall and a third sidewall connected to the first sidewall and the second sidewall, the third sidewall extends along the second direction, and the first sidewall and the second sidewall extend along a third direction perpendicular to the first direction and the second direction, wherein each of the second conductive lines (WL) is electrically connected to a respective gate electrode layer; a dielectric layer (35) surrounding the second source/drain regions (21/22) of the plurality of active regions; and wherein each of the gate electrode layers includes a first portion extending in the second direction and connected to the corresponding active region, and each of the gate electrode layers includes a second portion extending in a third direction perpendicular to the second direction and connected to the corresponding second conductive line (FIG. 11).
Lee is silent with respect to “a dielectric layer encapsulating the plurality of memory cell transistors, the first conductive line and the plurality of second conductive lines” and “each of the second conductive lines faces the third sidewall of the corresponding active region and is spaced apart from third sidewall of the corresponding active region by a first portion of the dielectric layer”.
FIG. 22 of Onuki discloses a similar semiconductor memory device, comprising a dielectric layer (1408) encapsulating the plurality of memory cell transistors (TrC/TrB), the first conductive line and the plurality of second conductive lines; and (FIG. 8) each of the second conductive lines (WL) faces the third sidewall of the corresponding active region and is spaced apart from third sidewall of the corresponding active region by a first portion of the dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Onuki. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of storing multi-level data with low power consumption and reduced area ([0007] of Onuki)
Regarding Claim 10
FIG. 4B of Lee discloses a plurality of capacitors (70) disposed in second source/drain regions of the plurality of active regions.
Claims 9 and 23 rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Onuki.
Regarding Claim 9
FIG. 5 of Kim discloses a semiconductor memory device, comprising: a plurality of memory cell transistors (T) vertically stacked over a substrate, each of the memory cell transistors comprising an active region (ACT) and a gate electrode layer [0092]; a first conductive line (BL) vertically extending in a first direction perpendicular to a top surface of the substrate and penetrating through first source/drain regions of the plurality of active regions; a plurality of second conductive lines (WL, FIG. 4) extending in a second direction parallel to the top surface of the substrate, wherein each of the second conductive lines is electrically connected to a respective gate electrode layer; and a dielectric layer encapsulating the plurality of memory cell transistors, the first conductive line and the plurality of second conductive lines, wherein in a plan view, each of the active region has a first sidewall, a second sidewall and a third sidewall connected to the first sidewall and the second sidewall, the third sidewall extends along the second direction, and the first sidewall and the second sidewall extend along a third direction perpendicular to the first direction and the second direction, wherein each of the second conductive lines faces the third sidewall of the corresponding active region and is spaced apart from third sidewall of the corresponding active region by a first portion of the dielectric layer, and wherein each of the gate electrode layers includes a first portion extending in the second direction and connected to the corresponding active region, and each of the gate electrode layers includes a second portion extending in the third direction perpendicular to the second direction and connected to the corresponding second conductive line, connected to the corresponding second conductive line, and spaced apart from the first sidewall of the corresponding active region by a second portion of the dielectric layer.
Kim is silent with respect to a first conductive line “a dielectric layer encapsulating the plurality of memory cell transistors, the first conductive line and the plurality of second conductive lines” and “each of the second conductive lines faces the third sidewall of the corresponding active region and is spaced apart from third sidewall of the corresponding active region by a first portion of the dielectric layer”.
FIG. 22 of Onuki discloses a similar semiconductor memory device, comprising a dielectric layer (1408) encapsulating the plurality of memory cell transistors (TrC/TrB), the first conductive line and the plurality of second conductive lines; and (FIG. 8) each of the second conductive lines (WL) faces the third sidewall of the corresponding active region and is spaced apart from third sidewall of the corresponding active region by a first portion of the dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Kim, as taught by Onuki. The ordinary artisan would have been motivated to modify Kim in the above manner for purpose of storing multi-level data with low power consumption and reduced area ([0007] of Onuki)
Regarding Claim 23
FIG. 22 of Onuki discloses a dielectric layer (1408) encapsulating the plurality of memory cell transistors (TrC/TrB), the first conductive line and the plurality of second conductive lines; and (FIG. 8) each of the second conductive lines (WL) faces the third sidewall of the corresponding active region and is spaced apart from third sidewall of the corresponding active region by a first portion of the dielectric layer.
Claims 16 rejected under 35 U.S.C. 103 as being unpatentable over Onuki, in view of Li (CN 115497977, machine-translation provided).
Regarding Claim 16
FIG. 8 of Onuki discloses a semiconductor memory device, comprising: a first active region (lower 101) and a second active region (upper 101) vertically stacked over the first active region, each of the first active region and the second active region including a first source/drain region, a first channel region, a second source/drain region, a second channel region, and a third source/drain region sequentially arranged in a first direction; a bit line (BL) vertically penetrating through and electrically connected to the second source/drain region of the first active region; a first capacitor (lower 102) disposed in the first source/drain region of the first active region, wherein the first capacitor comprises a capacitor dielectric layer; and a second capacitor (upper 102) disposed in the third source/drain region of the first active region.
Onuki is silent with respect to a first conductive line “a dielectric tube continuously extending through the first source/drain region of the first active region and the first source/drain region of the second active region”; and the capacitor dielectric layer “includes a portion of the dielectric tube”.
FIG. 29 of Li discloses a similar semiconductor memory device, comprising a dielectric tube (220) continuously extending through the first source/drain region of the first active region (lower 214) and the first source/drain region of the second active region (upper 214); and the capacitor dielectric layer includes a portion of the dielectric tube (capacitor formed by 216, 220 and 230).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Onuki, as taught by Li. The ordinary artisan would have been motivated to modify Onuki in the above manner for purpose of realizing reading and writing data operation with improved storage density (Abstract of Li).
Claims 6, 8, 12 and 13 rejected under 35 U.S.C. 103 as being unpatentable over Lee, Jang and Onuki, in view of Park (U.S. Patent Pub. No. 2011/0156118) of record.
Regarding Claim 6
Lee as modified by Jang and Onuki discloses Claim 1.
Lee as modified by Jang and Onuki is silent with respect to “the first direction is neither parallel nor perpendicular to the third direction”.
FIG. 2A of Park discloses a similar semiconductor memory device, wherein the first direction is neither parallel nor perpendicular to the third direction.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Park. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of increasing cell density ([0008] of Park).
Regarding Claim 8
Lee discloses the capacitor (70) comprises a second electrode that includes a portion of the third conductive line (50) surrounded by the active region of the first layer. FIG. 1B of Park discloses in a plan view, the second electrode is located within the first electrode.
Regarding Claim 12
FIG. 1B of Park discloses each of the capacitors includes a capacitor dielectric layer (17), and the plurality of capacitor dielectric layers are made of a continuous dielectric tube that extends in the first direction.
Regarding Claim 13
FIG. 1B of Park discloses the continuous dielectric tube has a sidewall interfaced with the dielectric layer.
Claim 14 rejected under 35 U.S.C. 103 as being unpatentable over Lee and Onuki, in view of Kim908 (U.S. Patent Pub. No. 2016/0216908) of record.
Regarding Claim 14
Lee as modified by Onuki discloses Claim 9.
Lee as modified by Onuki is silent with respect to “a select transistor disposed above the plurality of memory cell transistors”.
Kim908 discloses a similar semiconductor memory device, comprising a select transistor disposed above the plurality of memory cell transistors [0041].
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Lee, as taught by Kim908. The ordinary artisan would have been motivated to modify Lee in the above manner for purpose of making data selection.
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Onuki and Li, in view of Lee964 (U.S. Patent Pub. No. 2013/0126964) of record.
Regarding Claim 17
Onuki as modified by Li discloses Claim 16.
Onuki as modified by Li is silent with respect to “a contact sandwiched between the first capacitor and the first source/drain region of the first active region, wherein in a plan view, the contact has a ring-shape profile, and the first capacitor is located within the ring-shape profile of the contact”.
FIG. 1 of Lee964 discloses a similar semiconductor memory device, comprising a contact (50) sandwiched between the first capacitor (56) and the first source/drain region (12) of the first active region, wherein in a plan view, the contact has a ring-shape profile, and the first capacitor is located within the ring-shape profile of the contact.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Onuki, as taught by Lee964. The ordinary artisan would have been motivated to modify Onuki in the above manner for purpose of reducing the overall area of a complicated semiconductor device ([0004] of Lee964).
Claims 19-20 rejected under 35 U.S.C. 103 as being unpatentable over Onuki and Li, in view of Harari (CN 11937147) of record.
Regarding Claim 19
Onuki as modified by Li discloses Claim 16.
Onuki as modified by Li is silent with respect to “a first gate structure and a second gate structure respectively abutting the first channel region and the second channel region of the first active region at a first side of the first active region; and a third gate structure and a fourth gate layer respectively abutting the first channel region and the second channel region of the first active region at a second side of the first active region, wherein the second side is opposite the first side”.
FIG. 4 of Harari discloses a similar semiconductor memory device, comprising a first gate structure and a second gate structure respectively abutting the first channel region and the second channel region of the first active region at a first side of the first active region; and a third gate structure and a fourth gate layer respectively abutting the first channel region and the second channel region of the first active region at a second side of the first active region, wherein the second side is opposite the first side.
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to modify the device of Onuki, as taught by Harari. The ordinary artisan would have been motivated to modify Onuki in the above manner for purpose of forming a high density memory structure ([0002] of Harari).
Regarding Claim 20
FIG. 4 of Harari discloses a first word line (WL) electrically connected to gate electrodes of the first gate structure and the third gate structure; and a second word line electrically connected to gate electrodes of the second gate structure and the fourth gate structure.
Pertinent Art
Choi (U.S. Patent Pub. No. 2014/0056071) discloses the active region of the first layer vertically stacks over the active region of the second layer. Other Pertinent art includes CN 116209259, CN 102544013, KR 102056893, KR 101759926 and US 20090283737.
Response to Arguments
Applicant’s arguments with respect to Claims 1, 9 and 16 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHENG-BAI ZHU whose telephone number is (571)270-3904. The examiner can normally be reached on 11am – 7pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571)270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHENG-BAI ZHU/Primary Examiner, Art Unit 2897