DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. Applicant's election with traverse of claims 1-8 in the reply filed on 7/15/2025 is acknowledged.
3. Claims 9-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 11/4/2021. It is noted, however, that applicant has not filed a certified copy of the 17/952916 application as required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election with traverse of claims 1-15 in the reply filed on 7/15/2025 is acknowledged. The traversal is on the ground(s) that “search and examination of the claims of Group I and Group II, as identified in the Action, would not be unduly extensive or burdensome. Accordingly, Applicant respectfully requests withdrawal of the restriction requirement and consideration of all of the pending claims in the present application.” (see Last paragraph in page 8 of REMARKS filed on 7/15/2025). However, this is not found persuasive because Invention I (claims 1-8) are drawn to a self-aligned gate contact fin field effect transistor, while Invention II (claim 9-15) are drawn to a method for manufacturing a self-aligned gate contact fin field effect transistor. Thus, the determination of patentability of Invention I and Invention II would require a different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries), which would impose serious search burden on the examiner.
The requirement is still deemed proper and is therefore made FINAL. This application contains claims 9-15 drawn to an invention nonelected with traverse in the reply filed on 7/15/2025. A complete reply to the final rejection must include cancellation of nonelected claims or other appropriate action (87 CFR 1.144) See MPEP § 821.01.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0334008) (hereafter Chen), in view of Huang et al. (US 2021/013496) (hereafter Huang).
Regarding claim 1, Chen discloses a self-aligned gate contact fin field effect transistor, wherein a plurality of fins 24’ (Figs. 35B and 36, paragraph 0018) are formed on a semiconductor substrate 20 (Fig. 35B, paragraph 0016);
a plurality of fin field effect transistors (FinFETs with bottom 62/64 in Fig. 36; and see “FinFETs” in paragraph 0014) are integrated on the semiconductor substrate 20 (Fig. 35B);
each fin field effect transistor (FinFETs with bottom 62/64 in Fig. 36; and see “FinFETs” in paragraph 0014) comprises a gate structure (bottom 62 in Fig. 36, paragraph 0032; and see left 62 in Fig. 35B), a source region (portion of 24’ between bottom 62 and middle 62 in Fig. 36; and see leftmost 41/42 in Fig. 35B, paragraph 0037), and a drain region (bottommost portion of 24’ in Fig. 36; and see middle 41/42 in Fig. 35B, paragraph 0037);
the gate structure (bottom 62 in Fig. 36) covers front surfaces and side surfaces of the fins 24’ (Fig. 36) in a gate region (region wherein 62 is formed in Fig. 36), the gate structure (left 62 in Fig. 35B) is formed by superposing a gate dielectric layer 56 (Fig. 35B, paragraph 0052), a work function metal layer (“work-function layer” in paragraph 0030), and a metal conductive material layer (“filling metal” in paragraph 0031), the gate structure (left 62 in Fig. 35B) is formed in a gate trench (“trenches/openings” in paragraph 0028), top surfaces of the work function metal layer and the metal conductive material layer are etched back (see paragraph 0032, wherein “The formation process may include etching replacement gates 62 to form recesses, filling the dielectric material into the recesses, and performing a planarization process to remove excess portions of the dielectric material.”) to a position lower (see Fig. 7 and 8, wherein 62 (Fig. 8) is lower than 62 (Fig. 7)) than a top surface of the gate trench (region where 62 is formed in Fig. 7), a first top trench (“recesses” in paragraph 0032) is formed in the top surfaces (see Fig. 8) of the work function metal layer and the metal conductive material layer, and the first top trench (“recesses” in paragraph 0032) is filled with a first cap layer 64 (Fig. 8, paragraph 0032) formed by a first dielectric layer (“dielectric material” in paragraph 0032);
the source region (portion of 24’ between bottom 62 and middle 62 in Fig. 36; and see leftmost 41/42 in Fig. 35B, paragraph 0037) and the drain region (bottommost portion of 24’ in Fig. 36; and see middle 41/42 in Fig. 35B, paragraph 0037) are formed in the fins 24’ (Fig. 35B) on two sides of the gate structure 62 (Figs. 36 and 35B);
the plurality of fins 24’ (Fig. 36) are arranged in parallel, the fin field effect transistors (FinFETs with bottom 62/64 in Fig. 36; and see “FinFETs” in paragraph 0014) in a same column are aligned, gate trenches (region where 62 is formed in Fig. 36) of all fin field effect transistors in the same column are connected together, the first top trenches (“recesses” in paragraph 0032; and see region where 64 is formed in Fig. 36) are connected together and the metal conductive material layers (“filling metal” in paragraph 0031) of the gate structures (bottom 62 in Fig. 36) are connected together to form a gate metal strip (bottom 62 in Fig. 36), a self- aligned gate contact metal zero layer (66B in Fig. 35A, paragraph 0056) is formed on the top of more than one fin 24’ (Fig. 35A) intersecting with the gate metal strip (left 62 in Fig. 35A), and the self-aligned gate contact metal zero layer (66B in Fig. 35A) is formed by replacing the first cap layer 64 (Fig. 34) in the first top trench within a formation area of the self-aligned gate contact metal zero layer (66B in Fig. 35A) with a metal (“metal region (formed of tungsten or cobalt)” in paragraph 0056);
sidewalls (38 and 46 in Fig. 35A, paragraphs 0021 and 0027) are formed on two sides of the gate trench (region where 62 and 64 are formed in Fig. 35A), top surfaces of the sidewalls (38 and 46 in Fig. 35A) are located below (see top surface of 46 is lower than region where 62 and 64 are formed in Fig. 35A) the top surface of the gate trench (region where 62 and 64 are formed in Fig. 35A), the sidewalls (38 and 46 in Fig. 35A) comprise air sidewalls 39 (Fig. 35A, paragraph 0022), and the air sidewalls (see paragraph 0068, wherein “reduction of the parasitic capacitance between gate electrodes and nearby regions such as source/drain regions and source/drain contacts”) are used to reduce a parasitic capacitance of the fin field effect transistor;
tops of the source regions (middle 41/42 in Fig. 35B) and the drain regions (leftmost 41/42 in Fig. 35B) of the fin field effect transistors in the same column are respectively formed with corresponding source/drain contact metal zero layers (66A in Fig. 35B), the source/drain contact metal zero layer (66A in Fig. 35B) spans each fin 24’ (Fig. 35B) and is in a strip structure (66A in Fig. 35B), a top surface of each source/drain contact metal zero layer (66A in Fig. 35B) is lower than the top surfaces of the sidewalls 38 (Fig. 35B), and a second top trench 85 (Fig. 28, paragraph 0058) is formed in a top surface of the source/drain contact metal zero layer 66A (Fig. 28);
the second top trench (“recess” in paragraph 0059) is filled with a second cap layer 86 (Fig. 28, paragraph 0059) formed by a second dielectric layer (“dielectric material” in paragraph 0059).
Chen does not disclose materials of the first dielectric layer and the second dielectric layer are different; and
the second cap layer is used to prevent short-circuiting between the self-aligned gate contact metal zero layer and the source/drain contact metal zero layer.
Huang discloses materials of the first dielectric layer 80 (Fig. 19, paragraph 0030) and the second dielectric layer 88 (Fig. 19, paragraph 0034) are different (see paragraph 0034, wherein “The dielectric material of first mask material 88 may be different (e.g., having a different composition) from gate spacers 46, CESL 58, liner 84, and/or dielectric layers 80 to provide etching selectivity in subsequent processing”); and
the second cap layer 88 (Fig. 19, paragraph 0045, wherein “reducing the chance of undesired electrical shorting or leakage between the gate stacks 72 and source/drain contact plugs 96”) is used to prevent short-circuiting between the self-aligned gate contact metal zero layer 98 (Fig. 19, paragraph 0052) and the source/drain contact metal zero layer 96 (Fig. 19, paragraph 0045).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form materials of the first dielectric layer and the second dielectric layer are different, as taught by Huang, in order to provide etching selectivity in subsequent processing. In addition, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 5, Chen further discloses the self-aligned gate contact fin field effect transistor according to claim 1, wherein a zeroth layer via 96 (Fig. 35B, paragraph 0065) is formed in the top of more than one fin 24’ (Fig. 35B) intersecting with the source/drain contact metal zero layer 66A (Fig. 35B).
Chen does not disclose the zeroth layer via passes through the second cap layer and is connected with the source/drain contact metal zero layer.
Huang discloses the zeroth layer via 96 (Fig. 19, paragraph 0043) passes through the second cap layer 88 (Fig. 19, paragraph 0034) and is connected with the source/drain contact metal zero layer 82 (Fig. 19, paragraph 0029).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form the zeroth layer via passes through the second cap layer and is connected with the source/drain contact metal zero layer, as taught by Huang, since the larger width of contact opening 95 (Huang, Fig. 18, paragraph 0047) allows most of contact plug 82 (Huang, Fig. 18, paragraph 0047) to be exposed despite the overlay shift such that this can reduce (Huang, paragraph 0047) the effect of an overlay shift on the contact area between contact plug 82 (Huang, Fig. 19, paragraph 0047) and contact plug 96 (Huang, Fig. 19, paragraph 0047), which can reduce (Huang, paragraph 0047) the effect on device performance due to an overlay shift, wherein device performance (Huang, paragraph 0047) and uniformity can be improved under process variations.
Regarding claim 6, Chen in view of Huang discloses the self-aligned gate contact fin field effect transistor according to claim 5, however Chen does not disclose a material of the zeroth layer via comprises W, Co, or Cu.
Huang discloses a material of the zeroth layer via 96 (Fig. 19, paragraph 0052, wherein “The conductive material may include a diffusion barrier layer, which may be formed of titanium nitride, tantalum nitride, titanium, tantalum, or the like, and a conductive filling material such as copper, tungsten, cobalt, aluminum, ruthenium, the like, or combinations thereof”) comprises W, Co, or Cu.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Chen to form a material of the zeroth layer via comprises W, Co, or Cu, as taught by Huang, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 8, Chen further discloses the self-aligned gate contact fin field effect transistor according to claim 1, wherein a material of the metal conductive material layer (“filling metal” in paragraph 0031, wherein “tungsten”) comprises W, and a material of the source/drain contact metal zero layer (66A in Fig. 35B, paragraph 0034, wherein “tungsten or cobalt”) comprises W, Co, or Cu.
Allowable Subject Matter
1. Claims 2-4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 2 would be allowable because a closest prior art, Chen et al. (US 2019/0334008), discloses the sidewalls (38 and 46 in Fig. 35B) further comprise first sidewalls (37A in Fig. 35B, paragraph 0039) and second sidewalls 46 (Fig. 35B, paragraph 0027) located on two sides of the air sidewalls 39 (Fig. 35B), the first sidewalls (37A in Fig. 35B) are located on inner sides close to the gate trench (region where 62 and 64 are formed in Fig. 35B), the second sidewalls 46 (Fig. 35B) are located on outer sides far away from the gate trench (region where 62 and 64 are formed in Fig. 35B) but fails to disclose the second cap layer further covers tops of the first sidewalls, the air sidewalls, and the second sidewalls. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a self-aligned gate contact fin field effect transistor, wherein the second cap layer further covers tops of the first sidewalls, the air sidewalls, and the second sidewalls in combination with other elements of the base claim 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 3, 4, and 7 depend on claim 2.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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