Prosecution Insights
Last updated: October 22, 2026
Application No. 17/953,135

SILICON INTERPOSER INCLUDING THROUGH-SILICON VIA STRUCTURES WITH ENHANCED OVERLAY TOLERANCE AND METHODS OF FORMING THE SAME

Non-Final OA §102§103
Filed
Sep 26, 2022
Priority
May 28, 2020 — CIP of 11/296,032 +1 more
Examiner
LASASSO, VICTOR JOSEPH
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
41 granted / 47 resolved
+19.2% vs TC avg
Minimal +0% lift
Without
With
+0.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 8m
Avg Prosecution
16 currently pending
Career history
70
Total Applications
across all art units

Statute-Specific Performance

§103
53.5%
+13.5% vs TC avg
§102
30.5%
-9.5% vs TC avg
§112
16.1%
-23.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 47 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's election with traverse of Species II in the reply filed on May 4, 2026 is acknowledged. The traversal is on the ground(s) that the identified species are not mutually exclusive, but rather an intermediate and final product of the device being manufactured. This is found persuasive and the requirement for election has been withdrawn. Claims 1-20 are being examined on their merits. Drawings The drawings are objected to because the specification identifies vias 414 and liners 412, but the drawings appear to draw 412 to the vias themselves and 414 as the corresponding liners. Correction is required for either the specification or the drawings. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-8, 10-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shih et al (USPGPUB 20180102311, hereinafter “Shih”). Regarding Claim 1, Shih teaches (Fig. 13 and labeled fig. 13 below) a fan-out silicon interposer comprising: a bridge die (101) including an array of through-silicon via (TSV) structures (110) extending through a silicon substrate (100) and comprising metal pads (210); through-integrated-fan-out via (TIV) structures (510) located aside the bridge die (101); an encapsulant (550) that laterally surrounds the bridge die (101) and the TIV structures (510); a first redistribution structure (700) located on the bridge die (101); and a second redistribution structure (900) located at an opposite side of the first redistribution structure (700) relative to the bridge die (101), wherein the metal pads (210) are located between the array of TSV structures (110) and the second redistribution structure (900). PNG media_image1.png 574 716 media_image1.png Greyscale Regarding Claim 2, Shih teaches (Fig. 13) the fan-out silicon interposer of Claim 1, wherein the TIV structures (510) vertically extend through the encapsulant (550) and electrically connects a respective first redistribution wiring interconnect (a TIV 510 is seen connecting wiring interconnects in first redistribution structure 700 to wiring interconnects in second redistribution wiring structure 900) in the first redistribution structure (700) to a respective second redistribution wiring interconnect in the second redistribution structure (900). Regarding Claim 3, Shih (Fig. 13) teaches the fan-out silicon interposer of Claim 1, wherein the bridge die (101) comprises metal interconnect structures (204, 208) electrically connecting a respective one of the TSV structures (110) and a respective one of the metal pads (210). Regarding Claim 4, Shih teaches (Fig. 13) the fan-out silicon interposer of Claim 3, wherein the metal interconnect structures (204, 208) comprise a combination of metal line structures (204) and metal via structures (208), or integrated metal line and via structures. Regarding Claim 5, Shih teaches (Fig. 13) the fan-out silicon interposer of Claim 1, wherein the bridge die (101) comprises additional metal pads contacting an end surface of a respective one of the TSV (110) structures and having a greater width than (additional metal pads AMP is seen having a greater width than the end of surface of TSV structures 110) the end surface of the respective one of the TSV structures (101). Regarding Claim 6, Shih teaches (Fig. 13) the fan-out silicon interposer of Claim 5, wherein a horizontal plane including interfaces between the additional metal pads (AMP) and the TSV structures (110) is more proximal to the second redistribution structure (900) than a horizontal plane including an interface between the encapsulant (550) and the first redistribution structure is to the second redistribution structure (900). Regarding Claim 7, Shih teaches (Fig. 13) the fan-out silicon interposer of Claim 5, wherein a horizontal plane including interfaces between the additional metal pads (AMP) and the TSV structures (110) is more proximal to the second redistribution structure (900) than a horizontal plane including interfaces between the TIV structures (110) and the first redistribution structure (700) is to the second redistribution structure (900). Regarding Claim 8, Shih teaches (Fig. 13) a fan-out silicon interposer of Claim 5, wherein interfaces between the TIV structures (510) and the second redistribution structure (900) are located within a same horizontal plane as interfaces between the metal pads (210) and the second redistribution structure (900). Regarding Claim 10, Shih teaches (Fig. 13 and labeled fig. 13 above) a fan-out silicon interposer comprising: a bridge die (101) including an array of through-silicon via (TSV) structures (110) extending through a silicon substrate (100), first metal pads (AMP) contacting first end surfaces of the array of TSV structures (110), and a first dielectric material layer (a portion of dielectric material 712 is seen constituting a first dielectric layer) that laterally surrounds the first metal pads (210); an encapsulant (550) that laterally surrounds the bridge die (101); a first redistribution structure (700) comprising first redistribution wiring interconnects (first redistribution wiring interconnects are seen in first redistribution structure 700) that contact the first metal pads (AMP) with a non-zero alignment overlay; and a second redistribution structure (900) including second metal pads (210) and located at an opposite side of the first redistribution structure relative to the bridge die (101). Regarding Claim 11, Shih teaches the fan-out silicon interposer of Claim 10, wherein one of the first metal pads (AMP) contacts an end surface of a respective one of the TSV structures (110) and has a greater horizontal cross- sectional area than the end surface of the respective one of the TSV structures (110). Regarding Claim 12, Shih teaches the fan-out silicon interposer of Claim 10, wherein a horizontal plane including interfaces between the first metal pads (AMP) and the TSV structures (110) is more proximal to the second redistribution structure (900) than a horizontal plane including an interface between the encapsulant (550) and the first redistribution structure (700) is to the second redistribution structure (900). Regarding Claim 13, Shih teaches the fan-out silicon interposer of Claim 10, further comprising through-integrated- fan-out via (TIV) structures (510) that vertically extends through the encapsulant (550) and electrically connecting a respective first redistribution wiring interconnect (metal interconnects in first redistribution wiring structure 700) in the first redistribution structure (700) to a respective second redistribution wiring interconnect (metal interconnects in second redistribution wiring structure 900) in the second redistribution structure (900). Regarding Claim 14, Shih teaches the fan-out silicon interposer of Claim 13, wherein a horizontal plane including interfaces between the first metal pads (AMP) and the first redistribution structure (700) is more proximal to the second redistribution structure (900) than the horizontal plane including the interfaces between the TIV structures (510) and the first redistribution structure (700) is to the second redistribution structure (900). Regarding Claim 15, Shih teaches the fan-out silicon interposer of Claim 10, wherein the bridge die (101) comprises metal interconnect structures (208, 204) providing electrical connections electrically connection between a respective one of the TSV structures (110) and respective one of the second metal pads (210). Claim(s) 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al (USPGPUB 20170263518, hereinafter “Yu”). Regarding Claim 17, Yu teaches (Fig. 17 and labeled fig. 17 below) a fan-out silicon interposer comprising: a bridge (100B) die including an array of through-silicon via (TSV) structures (V) extending through a silicon substrate ([0019], “Device dies 100 include semiconductor substrates 128, which may be silicon substrates”), first metal pads (MP1) contacting first end surfaces of the array of TSV structures (V), and a first dielectric material layer (69) that laterally surrounds the first metal pads (MP1); an encapsulant that laterally encapsulates the bridge die (100B) and the first metal pads (MP1); a first redistribution structure (RS1) located on the first metal pads (MP1) and contacting the first dielectric material layer (D1) of the bridge die (100B); and a second redistribution structure (RS2) including second bonding pads (2BP) and located at an opposite side of the first redistribution structure (RS1) relative to the bridge die (100B). PNG media_image2.png 388 698 media_image2.png Greyscale Regarding Claim 18, Yu teaches (Fig. 17) the fan-out silicon interposer of Claim 1, wherein each of the first metal pads (MP1) contacts an end surface of a respective one of the TSV structures (V) and has a greater horizontal cross- sectional area than the end surface of the respective one of the TSV structures (V). Regarding Claim 19, Yu teaches the fan-out silicon interposer of Claim 18, wherein a sidewall of the first dielectric material layer (D1) is in direct contact with the encapsulant (69). Regarding Claim 20, Yu teaches the fan-out silicon interposer of Claim 18, wherein the first redistribution structure (RS1) comprises first redistribution wiring interconnects (conductive wirings are seen within first redistribution structure RS1) that contact the first metal pads (MP1) with a non-zero alignment overlay. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih as applied to claim 5 above, and further in view of Son et al (USPGPUB 20140264848, hereinafter “Son”). Regarding Claim 9, Shih teaches the fan-out silicon interposer of Claim 5, but is silent with regards to a device wherein: each of the TSV structures is laterally surrounded by a respective cylindrical portion of a through-substrate insulating spacer; the silicon substrate is vertically spaced from a horizontal plane including interfaces between the additional metal pads and the TSV structures by a backside insulating layer that laterally surrounds the cylindrical portions of the through-substrate insulating spacer. Son teaches (Fig. 6B) a device wherein: each of the TSV structures is laterally surrounded by a respective cylindrical portion of a through-substrate insulating spacer (101A); the silicon substrate is vertically spaced from a horizontal plane including interfaces between (a person of ordinary skill in the art would understand that the use of the insulating spacers surrounding the vias would necessitate additional structural/insulating support of insulating layers such as that of backside insulating layer 104 on the metal pads of Shih) the additional metal pads and the TSV structures (101C) by a backside insulating layer (104) that laterally surrounds the cylindrical portions of the through-substrate insulating spacer (101A). It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the metal pads of Son into the device of Shih in order to arrive at the expected result of creating a device with the known benefit of increased insulating/structural support properties with reasonable expectation of success. Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih as applied to claim 10 above, and further in view of Zhai et al (USPGPUB 20180358298, hereinafter “Zhai”). Regarding Claim 16, Shih teaches the fan-out silicon interposer of Claim 10, but is silent with regards to a device wherein: the second pads comprise an array of microbumps; and the first redistribution structure comprises first bonding pads that include an array of C4 bonding pads, wherein the first bonding pads are electrically connected to a respective one of the first metal pads through first redistribution wiring interconnects in the first redistribution structure. Zhai teaches a device wherein: the second pads comprises comprise an array of microbumps; and the first redistribution structure comprises first bonding pads that include an array of C4 bonding pads ([0034], “a first plurality of conductive bumps 131 (e.g. solder) connect the first and second components 130, 132 to the RDL 120, and a second plurality of conductive bumps 133 (e.g. micro-bumps; solder) connect the first and second components 130”), wherein the first bonding pads are electrically connected to a respective one of the first metal pads through first redistribution wiring interconnects in the first redistribution structure (the pads are seen connected to metal pads through first wiring interconnects). It would have been obvious to a person of ordinary skill in the art, absent unexpected results, before the date of effective filing, to incorporate the microbump routing of Zhai into the device of Shih in order to arrive at the expected result of allowing for adequate coupling between the device components while also maintaining optimal scale within the microelectronic device with reasonable expectation of success. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR J LASASSO whose telephone number is (703)756-5668. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571) 272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.J.L./ Examiner, Art Unit 2898 /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
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Prosecution Timeline

Sep 26, 2022
Application Filed
Oct 02, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
88%
With Interview (+0.4%)
3y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 47 resolved cases by this examiner. Grant probability derived from career allowance rate.

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