Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 20 is objected to because of the following informalities: the claim has an apparent typographical error where the dependency is omitted. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 5, 19, 20, 22 and 25-29 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0375899), (hereinafter, LIN).
RE Claims 1, LIN discloses a semiconductor device and a method of making the same comprising a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section. LIN discloses a semiconductor structure, comprising:
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a substrate 10, wherein the substrate is divided into a first element region MC “memory cell region”, referring to FIGS. 16 and 17 [0049-0051], a second element region LC “logic circuit area” and a boundary region TR “transition region”, and the boundary region TR “transition region” is disposed between the first element region MC “memory cell region” and the second element region LC “logic circuit area”, referring to FIGS. 16 and 17;
a memory device structure disposed within the first element region MC, referring to FIGS. 16 and 17;
a first mask structure 41 covering the first element region and the memory device structure and only made of silicon oxide, silicon nitride or multi-layered silicon oxide/silicon nitride “ONO” [0049], respectively, which is functionally equivalent to a mask since it is used during as a mask to define the gate structures”, referring to FIG. 17, covering the first element region MC “memory cell region”, wherein the first mask structure 41 only consists of a silicon oxide layer. Since the mask layer 41 may be formed of ONO “silicon oxide/silicon nitride/ silicon oxide”, which imply that the upper most layer of the layer stack 41 is made of silicon oxide ONLY [0049], hence meeting the claimed limitation;
a second mask structure 41, referring to FIGS. 16 and 17 disposed in the boundary region TR “transition region”, wherein the second mask structure 41 only consists of the silicon oxide layer”, Since the mask layer 41 may be formed of ONO “silicon oxide/silicon nitride/ silicon oxide”, which imply that the upper most layer of the layer stack 41 is made of silicon oxide ONLY [0049], hence meeting the claimed limitation, and atopmost surface of the first mask structure 41, hence upper layer of the mask stacked ONO layer, is aligned with a topmost surface of the second mask structure 41, hence the upper layer of the second portion in the overlapping region TR of the mask stacked ONO layer, referring to FIGS. 16, 18 and 39. It is the examiner position that since the mask layer 41 is formed over all regions and subsequently patterned such that portions over the first region and part of the overlapping region having atopmost surface of the first mask structure 41 is aligned with a topmost surface of the second mask structure 41 are aligned, hence meeting the claimed limitation; and
a logic gate structure 41/43/45 disposed within the second element region LC “logic circuit area”, referring to FIG. 29;
a first shallow trench isolation 20C disposed within the substrate 10 at the boundary region TR, wherein a top surface of the first shallow trench isolation defines a stair profile, and wherein the first mask structure 41 is a continuous structure continuously extending from a top of the memory device structure into the boundary region to cover the first shallow trench isolation, referring to FIGS. 16-18. It is shown in FIG. 16 that the first mask structure is shown to continuously cover the MC, TR and LC regions, with subsequent patterning that is extending from a top of the memory device structure into the boundary region to cover the first shallow trench isolation 20, hence meeting the claimed limitation; and
a layer, forming one of the layers forming the first mask 41 stack, i.e. bottom layers of the ONO stack of the mask layer 41, hence meeting the claimed limitation, disposed between the second mask structure 41 and the first shallow trench isolation 20C, referring to FIGS. 16 and 17. Since the layer 41 may be formed of ONO “silicon oxide/silicon nitride/ silicon oxide”
RE Claim 2, LIN discloses a semiconductor structure, further comprising:
a polysilicon layer 30 “floating gate” [0032] covering the first element region MC “memory cell region”, referring to FIGS. 16 and 17, wherein the polysilicon layer 30 “floating gate” is disposed between the first mask structure 41 and the substrate 10, and the second mask structure 47, over the second region LC “logic circuit area” does not contact the polysilicon layer 30.
RE Claims 5, LIN discloses a semiconductor structure, wherein the first element region MC “memory cell region” comprises a high voltage transistor region or a memory cell region, and the second element region LC “logic circuit area” comprises a logic circuit region “41/43/45” referring to FIG. 29.
RE Claim 19 and 20, LIN discloses a semiconductor structure, wherein the layer is a silicon nitride layer [0049]. Since first mask structure 41 made of silicon oxide, silicon nitride or multi-layered silicon oxide/silicon nitride [0049], the layer, even though not shown, it is a silicon nitride layer, hence the claimed limitation is met, which means that the second mask structure 47 separates the first shallow trench isolation 20C by the layer, which is one of the first mask 41 multi-layered structure.
RE Claim 22, LIN discloses a semiconductor structure, further comprising a second shallow trench isolation 20A disposed within the substrate 10 at the first element region, and wherein the first mask structure 41 is disposed on the second shallow trench isolation 20a, referring to FIG. 14.
RE Claim 25, LIN discloses a semiconductor structure, wherein the stair profile comprises a higher portion and a lower portion, the higher portion is adjacent to the second element region, logic gate structure LC, and the lower portion is adjacent to the first element region MC.
RE Claim 26, LIN discloses a semiconductor structure, wherein a top surface of the substrate 10 at the second element region TR is lower than a top surface of the first shallow trench isolation 20C, referring to FIGS. 16 and 17.
RE Claim 27, LIN discloses a semiconductor structure, wherein the logic gate structure comprises a high-k dielectric material layer and a polysilicon layer 43on the high-k dielectric material layer [0081-0082].
RE Claim 28, LIN discloses a semiconductor structure, wherein the logic gate structure further comprises a hard mask 45/58/106 “silicon nitride” on the polysilicon layer 43, referring to FIGS. 28-29 and 42 [0061, 0066, 0071-0073].
RE Claim 29, LIN discloses a semiconductor structure, wherein the logic gate structure LC further comprises a silicon oxide mask on the silicon nitride mask. It is the examiner position that the claimed limitation is met since the layer mask layered stack 41 is formed of ONO “silicon oxide/silicon nitride/silicon oxide” layered stack.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are not persuasive since the mask layer 41 formed over the three regions MC, TR and LC, subsequently patterned and 2 portions of it formed in the first and overlapping regions MC and TR are well-aligned as shown in the annotated figures above. Furthermore, the mask layer 41 is formed of ONO “silicon oxide/silicon nitride/silicon oxide” layered stack, thus addressing the claimed limitation properly as the uppermost layer of the stack is formed of silicon oxide ONLY and is aligned in both regions MC and TR, hence meeting the claimed limitations.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, Lin et al. (US 2020/0105777) discloses an integrated circuit includes a semiconductor substrate having a peripheral region and a memory cell region separated by an isolation structure. The isolation structure extends into a top surface of the semiconductor substrate and comprises dielectric material. A logic device is arranged on the peripheral region. A memory device is arranged on the memory region. The memory device includes a gate electrode and a memory hardmask over the gate electrode. An anti-dishing structure is disposed on the isolation structure. An upper surface of the anti-dishing structure and an upper surface of the memory hardmask have equal heights as measured from the top surface of the semiconductor substrate.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898
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