DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/12/2025 has been entered.
Claim Status
Previous action: Claims 1 through 16 rejected, claims 17 through 20 withdrawn.
Present action: Claims 1 through 16 rejected, claims 17 through 20 withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1 through 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 2015/0228547) in view of Chen (US 2021/0375721)
Regarding claim 1.
Shih teaches:
An electronic device (fig 5:100; [para 0028]), comprising: a substrate (fig 5:10; [para 0021]);
a conductive structure (fig 5:25,30; [para 0022]) disposed on the substrate (fig 5:10; [para 0021]),
and the conductive structure (fig 5:25,30; [para 0022]) including a pad (fig 5:30,34,32; [para 0022]) having a first exposed surface (fig 5:32; [para 0022]) configured to be contacted by a probe during a testing process (fig 5:50; [para 0022]) and a [protective] structure (fig 5:24,36; [para 0022]) embedding the pad (fig 5:30,32,34; [para 0022]),
wherein the [protective] structure (fig 5:24,36; [para 0022]) includes an opening to expose a first portion on the first exposed surface (fig 5:32; [para 0022]) of the pad (fig 5:30,32,34; [para 0022]),
wherein the first exposed surface (fig 5:32; [para 0022]) of the pad (fig 5:30,32,34; [para 0022]) is not covered by a top surface of the electronic device (fig 5:100; [para 0023]);
and at least one external connector (fig 5:22,25,40; [para 0022,0023]) embedded by the [protective] structure (fig 5:24,36; [para 0022]) and electrically connected to the conductive structure (fig 5:25,30; [para 0022,0023]),
and the at least one external connector (fig 5:22,25,40; [para 0022]) including a sidewall coupled with the [protective] structure (fig 5:24,36; [para 0022]) and a second exposed surface not covered by a bottom surface of the electronic device (fig 5:400; [para 0028]),
which is opposite to the top surface of the electronic device (fig 5:400; [para 0028]),
for an external electrical connection,
wherein a vertical projection of the at least one external connector (fig 5:22,25,40; [para 0022,0023]) overlaps a vertical projection of the pad (fig 5:30,32,34; [para 0022]).
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Shih does not teach that the protective structure is a dielectric structure.
Chen teaches:
a bonding pad (fig 1I:130a; [para 0023]) configured to be contacted by a probe (fig 1I:132; [para 0023]) during a testing process ([para 0023])
the protective structure (fig 1k:122,140,160,180; [para 0025,0026,0033]) is a dielectric structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a pad configured as a bonding pad can also be configured as a testing pad in order to minimize the number of pads required for a structure. Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the protective structure to be a dielectric structure in order that the structure does not short the components of the device rendering it inoperable.
The limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Regarding claim 2.
Shih in view of Chen teaches he electronic device of Claim 1, further
Shih teaches:
a capacitor (fig 5:161; [para 0028]) disposed on the substrate (fig 5:10; [para 0021]).
Regarding claim 3.
Shih in view of Chen teaches the electronic device of Claim 1, further,
Shih teaches:
the conductive structure (fig 5:25,30; [para 0022]) further includes a plurality of patterned metal layers (fig 5:25; [para 0022]),
wherein the pad (fig 5:30,32,34; [para 0022]) is electrically connected to the plurality of patterned metal layers (fig 5:25; [para 0022]),
and the pad (fig 5:30,32,34; [para 0022]) and the plurality of patterned metal layers (fig 5:25; [para 0022]) are embedded in the [protective] structure (fig 5:24,36; [para 0022]).
Chen teaches:
a bonding pad (fig 1I:130a; [para 0023]) configured to be contacted by a probe (fig 1I:132[para 0023]) during a testing process ([para 0023])
the protective structure (fig 1k:122,140,160,180; [para 0025,0026,0033]) is a dielectric structure.
Regarding claim 4.
Shih in view of Chen teaches the electronic device of Claim 3 above, further
Shih teaches:
the first portion on the first exposed surface (fig 5:32; [para 0022]) of the pad (fig 5:30,32,34; [para 0022]) .
Chen teaches:
a bonding pad (fig 1I:130a; [para 0023]) configured to be contacted by a probe (fig 1I:132[para 0023]) during a testing process ([para 0023])
the test pad (fig 1b:130a; [para 0026]) has a probe mark (fig 1b:132; [para 0026]) thereon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that probing a pad with a probe will result in a probe mark due to the physical displacement of material by the probe.
Regarding claim 5.
Shih in view of Chen teaches the electronic device of Claim 3, further,
Shih teaches:
a vertical projection of the at least one external connector (fig 5:22,25,40; [para 0022]) overlaps a vertical projection of the opening (fig 5).
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Regarding claim 6.
Shih in view of Chen teaches the electronic device of Claim 3, further,
Shih teaches:
a vertical projection of the at least one external connector (fig 5:22,25,40; [para 0022]) is located outside a vertical projection of the opening (fig 5).
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Regarding claim 7.
Shih in view of Chen teaches the electronic device of Claim 1, further,
Shih teaches:
the at least one external connector (fig 5:22,25,40; [para 0023]) includes a conductive via (fig 5:22; [para 0023]) extending through the substrate (fig 5:10; [para 0023]) and exposed ([para 0023]) from a bottom surface of the electronic device.
Regarding claim 8.
Shih in view of Chen teaches the electronic device of Claim 7 above,
Chen teaches:
a bottom passivation layer (fig 1k:190; [para 0034]) disposed on a bottom surface of the substrate (fig 1k:110; [para 0034]) and surrounding the conductive via (fig 1k:154; [para 0034]),
wherein a bottom surface of the bottom passivation layer (fig 1k:190; [para 0034]) is substantially aligned with a bottom surface of the conductive via (fig 1k:154; [para 0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a bottom passivation layer in order to protect the substrate from damage and contamination during the manufacturing process.
Regarding claim 9.
Shih in view of Chen teaches the electronic device of Claim 1 above,
Chen teaches:
the at least one external connector (fig 1k:154; [para 0032]) includes a connection via (fig 1k:182; [para 0032]) connected to a second portion of the test pad (fig 1k:174; [para 0032]) and exposed from a top surface of the electronic device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a via on the top surface in order to facilitate boding to adjacent structures.
Regarding claim 10.
Shih in view of Chen teaches the electronic device of Claim 9 above,
Chen teaches:
a top passivation layer (fig 1k:180; [para 0033]) disposed on a top surface of the conductive structure (fig 1k:114,130; [para 0024]) and surrounding the connection via (fig 1k:182; [para 0032]),
wherein a top surface of the top passivation layer (fig 1k:180; [para 0033]) is substantially aligned with a top surface of the connection via (fig 1k:182; [para 0032]).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (US 2015/0228547) in view of Chen (US 2021/0375721) as applied to claim 1 and further in view of Kim (US 2021/0366856).
Regarding claim 11.
Shih in view of Chen teaches the electronic device of Claim 1.
Shih in view of Chen does not teach a connection via.
Kim teaches:
the at least one external connector (fig 3:260,220; [para 0043]) includes a conductive via (fig 3:220; [para 0043]) and a connection via (fig 3:260; [para 0043]),
the conductive via (fig 3:220; [para 0043]) extends through the substrate (fig 3:210; [para 0043]) and is disposed under the conductive structure (fig 3:231,250; [para 0043]),
the connection via (fig 3:260; [para 0043]) extends through a portion of a dielectric structure (fig 3:280; [para 0043]) of the conductive structure (fig 3:231; [para 0043]) on the pad (fig 3:250; [para 0043]),
wherein the pad (fig 3:250; [para 0043]) is disposed between the conductive via (fig 1:120; [para 0034]) and the connection via (fig 3:260; [para 0043]),
and a width of the connection via (fig 3:260; [para 0043]) is less than a width of the conductive via (fig 3:220; [para 0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a connection via on the pad in order to enable the structure to be bonded to additional die, thereby enabling a die stack which facilitate more capacity in a smaller package
Claim(s) 12, 13, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0366856) in view of Shih (US 2015/0228547)
Regarding claim 12.
Kim teaches:
An electronic structure (fig 1:10; [para 0027]), comprising: a first substrate (fig 1:110; [para 0032]);
a first conductive structure (fig 1:131,150,160; [para 0031]) disposed over the first substrate (fig 1:110; [para 0032]),
the first conductive structure (fig 1:131,150,160; [para 0031]) including a first pad (fig 1:150,160; [para 0031]) having a first exposed surface and a first dielectric structure (fig 1:180,132; [para 0040]) embedding the first pad (fig 1:150,160; [para 0031]),
wherein the first dielectric structure (fig 1:180,132; [para 0040]) includes an opening to expose a first portion on the first exposed surface of the first pad (fig 1:150,160; [para 0031]),
wherein the first exposed surface of the first pad (fig 1:150,160; [para 0031]) is not covered by a top surface of the first electronic device;
and a second conductive structure (fig 1:250,231; [para 0043]) disposed under the first substrate (fig 1:110; [para 0032]), the second conductive structure (fig 1:250,231; [para 0043]) including a second pad (fig 1:250; [para 0043]) configured to be electrically contacted to the first pad (fig 1:150,160; [para 0031]) of the first conductive structure (fig 1:131,150,160; [para 0031]) and a second dielectric structure (fig 1:280,232; [para 0050,0052]) embedding the second pad (fig 1:250; [para 0043]),
wherein an electrical path between the first conductive structure (fig 1:131,150,160; [para 0031]) and the second conductive structure (fig 1:250,231; [para 0043]) is located between the first test pad and the second test pad (fig 1:250; [para 0043]).
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Kim does not teach the pad is a test pad.
Shih teaches:
the first conductive structure (fig 5:25,30; [para 0022]) including a first test pad (fig 5:30,34; [para 0022]) having a first exposed surface configured to be contacted by a probe during a testing process,
including a second test pad (fig 5:40,44; [para 0023]) configured to be electrically contacted to the first test pad (fig 5:30,34; [para 0022]) of the first conductive structure (fig 5:25,30,40; [para 0022,0023]) during the testing process
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the pad to be testing pad in order that the quality and functionality of the fabricated structure can be evaluated (paragraph 6)
The limitation must distinguish from the prior art in terms of structure rather than function, In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997); See also In re Swinehart, 439 F.2d210, 212-13, 169 USPQ 226, 228-29 (CCPA 1971). Claims directed to apparatus must be distinguished from the prior art in terms of structure rather than function. In re Danly, 263 F. 2d 844, 847, 120 USPQ 528, 531 (CCPA 1959). “Apparatus claims cover what a device is, not what a device does.” Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F. 2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990).
Regarding claim 13.
Kim in view of Shih teaches the electronic structure of Claim 12, further
Kim teaches:
the electrical path includes a vertical electrical path,
and a projection of the vertical electrical path on the second pad (fig 1:250; [para 0043]) is within a projection of the first pad (fig 1:150,160; [para 0031]) on the second test pad (fig 1:250; [para 0043]);
the vertical electrical path passes through the first substrate (fig 1:110; [para 0032]).
Shih teaches:
a first test pad (fig 5:30,34; [para 0022])
a second test pad (fig 5:40,44; [para 0023])
Regarding claim 14.
Kim in view of Shih teaches the electronic structure of Claim 12, further
Kim teaches:
an interconnection pillar (fig 1:260,120; [para 0043]) electrically connecting the first conductive structure (fig 1:131,150,160; [para 0031]) and the second conductive structure (fig 1:250,231; [para 0043]),
wherein the interconnection pillar (fig 1:260,120; [para 0043]) forms the electrical path,
wherein the interconnection pillar (fig 1:260,120; [para 0043]) includes a conductive via (fig 1:120; [para 0043]) and a connection via (fig 1:260; [para 0043]),
and a width of the connection via (fig 1:260; [para 0043]) is less than a width of the conductive via (fig 1:120; [para 0043]),
and the conductive via (fig 1:120; [para 0043]) extends through the first substrate (fig 1:110; [para 0032]),
and the connection via (fig 1:260; [para 0043]) connects to the second pad (fig 1:250; [para 0043]).
Shih teaches:
including a second test pad (fig 5:40,44; [para 0023]) configured to be electrically contacted to the first test pad (fig 5:30,34; [para 0022]) of the first conductive structure (fig 5:25,30,40; [para 0022,0023]) during the testing process
Regarding claim 15.
Kim in view of Shih teaches the electronic structure of Claim 12, further
Kim teaches:
an interconnection pillar (fig 1:260,120; [para 0043]) electrically connecting the first conductive structure (fig 1:131,150,160; [para 0031]) and the second conductive structure (fig 1:250,231; [para 0043]),
wherein the interconnection pillar (fig 1:260,120; [para 0043]) forms the electrical path,
wherein the interconnection pillar (fig 1:260,120; [para 0043]) includes a conductive via and a plurality of connection vias,
and a width of each of the connection vias is less than a width of the conductive via (fig 1:120; [para 0043]).
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Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2021/0366856) in view of Shih (US 2015/0228547) as applied to claim 12 and further in view of Chen (US 2021/0375721)
Regarding claim 16.
Kim in view of Shih teaches the electronic structure of Claim 12, further
Kim teaches:
comprising a bonding layer (fig 1:280; [para 0045]) bonding the first substrate (fig 1:110; [para 0032]) and the second conductive structure (fig 1:210; [para 0044]),
and the electrical path passes through the bonding layer (fig 1:280; [para 0045]),
Kim in view of Shih does not teach an opening with bonding layer extending therein.
Chen teaches:
wherein the second conductive structure defines an opening (fig 1b:142; [para 0026]) to expose a portion on the second exposed surface of the second test pad (fig 1b:130a; [para 0026]),
and the bonding layer (fig 1g:140; [para 0028]) extends into the opening (fig 1b:142; [para 0026])to contact the portion of the second test pad (fig 1b:130a; [para 0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an opening in the structure exposing the pad with a bonding layer disposed therein in order to provide a level surface for subsequently deposited layers.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that Shih does not teach that the protective layer is a dielectric material.
Shih in combination with Chen teaches that the protection layer comprises a dielectric structure, which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention in order to avoid the device being shorted and thereby rendered inoperable.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 14, 2026
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