DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 29 2025 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 4-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ewe et al. (“Ewe” US 2011/0108971).
Regarding claim 1, Ewe discloses an electronic package (300, Figure 3), comprising:
an insulating carrier (insulating layer 112, para. [0044]);
a first conductive layer (conductive adhesive/solder 128, see para. [0027], [0048]) connected to a first surface of the insulating carrier (112, upper surface);
an electronic component (low side IC 120_1) disposed over the first conductive layer (128 on lower surface of the electronic component 120_1, see Figure 3, see also annotated Figure 3 below) and electrically connected to the first conductive layer (128, para. [0047] discloses that the source electrode pad 124 is connected to the trace 114c, and the conductive layer 128 is interposed therebetween, therefore provides electrical connection and is electrically connected to the electronic component 120_1), wherein the insulating carrier (112) is configured to dissipate heat from the electronic component (120_1) to a second surface of the insulating carrier (112, lower surface) opposite to the first surface facing the electronic component (120_1, since the insulating carrier 112 is made of an epoxy resin material, see para. [0019], which has a heat conductivity capable of dissipating heat, the carrier 112 will dissipate/conduct heat from one surface contacting a hot spot, i.e. the electronic component 120_1, to the opposite surface);
a second conductive layer (115d, see Figure 3, see also annotated Figure 3 below) connected to the second surface of the insulating carrier (112, connected to the lower surface, see Figure 3) that is facing away from the electronic component (the lower surface of the carrier 112 is facing away from the electronic component 120_1);
a passive component (170, para. [0057]) disposed over and connected to the second conductive layer (115d, Figure 3 shows the passive component 170 on the top surface of the carrier 112, however para. [0057] discloses that the passive component 170 may be mounted to the metal layer 160 which is over the second conductive layer 115d, thus the passive component 170 would be disposed over and connected to the second conductive layer 115d);
a circuit layer (126) disposed over and electrically connected to the electronic component (120_1, see Figure 3 and para. [0047]),
wherein the electronic component (120_1) is vertically stacked between the circuit layer (126) and the passive component (170, on lower surface of the carrier 112, see Figure 3).
Regarding claim 2, Ewe further discloses a third conductive layer (114d, see Figure 3) connected to the first surface of the insulating carrier (112, upper surface) and spaced apart from the first conductive layer (128 on lower side of electronic component 120_1), wherein the insulating carrier (112) thermally connects to the first conductive layer (128 on electronic component 120_1) and the second conductive layer (115d, since both conductive layers 128 on either side of the insulating carrier are in direct physical contact with the insulating carrier 112, they would be in thermal contact with each other through the insulating carrier, i.e. the thermal energy of one conductive layer influences the thermal energy of the other); and
a fourth conductive layer (via between the third conductive layer 114d and conductive layer 115d) extending along a lateral surface of the insulating carrier (112, see lateral surface in contact with the vertically extending via/fourth conductive layer) and connecting the third conductive layer (114d) to the second conductive layer (115d, see Figure 3), wherein the fourth conductive layer (via between 114d and 115d) has a lateral surface contacting the first conductive layer (128 on lower side of the electronic component 120_1, the lateral surface of the via/fourth conductive layer contacts the first conductive layer through the insulating carrier 112) and a bottom surface contacting the second conductive layer (115d, see Figure 3, here, “contacting” can be electrical contact, physical contact, or thermal contact, etc.).
Regarding claim 4, Ewe discloses wherein the lateral surface extends between the first surface and the second surface of the insulating carrier (the lateral surface where the fourth conductive layer, via between 114d and 115d, extends between the top and bottom surfaces of the carrier 112, see Figure 3),
and the fourth conductive layer (via between 114d and 115d) directly contacts the lateral surface (see Figure 3).
Regarding claim 5, Ewe discloses wherein the electronic component (120_1) and the passive component (170, on lower surface of the carrier 112) are disposed over and connected to opposite sides of the insulating carrier (112, Figure 3 shows the electronic component 120_1 disposed over and connected to the top surface of the carrier 112, and para. [0057] discloses the passive component as being disposed over and connected to the lower surface of the carrier 112).
Regarding claim 6, Ewe further discloses a conductive via (via between trace 140 and third conductive layer 114d) contacting the circuit layer (126, through 140 electrical/physical/thermal contact is made) and horizontally overlapped with the electronic component (120_1, see Figure 3).
Regarding claim 7, Ewe further discloses a conductive via (via between trace 140 and 115d) between and contacting the circuit layer (126, through trace 140) and the second conductive layer (115d, see Figure 3); and
a dielectric layer (130/150) encapsulating the first conductive layer (128 on upper surface of the carrier/lower surface of the electronic component 120_1), the second conductive layer (115d), the conductive via, and the electronic component (120_1, see Figure 3).
Regarding claim 8, Ewe discloses a third conductive layer (114c) connected to the first surface of the insulating carrier (112, upper surface) and spaced apart from the first conductive layer (128 on lower surface of electronic component 120_1, see 114c is spaced apart from the left side portion of 128 in Figure 3), wherein the conductive via (via between 140 and 115d) is partially between the first conductive layer (128 on lower surface of the electronic component 120_1) and the third conductive layer (the via has a portion that is laterally extending between the first and third conductive layers, see Figure 3, i.e. the via has a portion that horizontally overlaps the region between the first and third conductive layers).
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Ewe as applied to claim 2 above, and further in view of Funaya et al. (“Funaya” US 2010/0044845).
Regarding claim 3, Ewe further discloses a conductive via (via between trace 140 and 114, within layer 130) contacting the circuit layer (126, electrical/physical/thermal contact through the trace 140) and the third conductive layer(114d, see Figure 3).
Ewe does not disclose that the conductive via tapers toward the third conductive layer.
However, Funaya discloses in Figure 3 a conductive via (7) that tapers toward a conductive layer (4, see Figure 3).
It would have been obvious to one having ordinary skill in the art to incorporate the tapered via of Funaya into the conductive via of Ewe for the purpose of enhancing the product quality because with a tapered via, it is easy to detect faulty portions which can be subject to further plating/via material deposition during manufacture (Funaya, para. [0158]).
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ewe et al. (“Ewe” US 2011/0108971) and Grober et al. (“Grober” US 2019/0306988).
Regarding claim 9, Ewe discloses an electronic package (300, Figure 3), comprising:
a [ceramic] layer (112) having a top surface and a bottom surface opposite to the top surface (see Figure 3);
an upper cladding layer (114) contacting the top surface the [ceramic] layer (112, see Figure 3);
a lower cladding layer (115) contacting the bottom surface of the [ceramic] layer (112, see Figure 3), wherein a lateral surface of the [ceramic] layer (112) is exposed by the upper cladding layer (114) and the lower cladding layer (114, see Figure 3), the lower cladding layer (115) comprises a cladding part (115c) and a frame part (115a/115b/115d) separated by a gap that exposes a portion of the bottom surface of the [ceramic] layer (112, see Figure 3), and the frame part (115a/b/d) contacts a peripheral region of the bottom surface of the [ceramic] layer (112, see Figure 3, the peripheral region being the region outside of the classing part 115c);
an electronic component (120_1) attached to the upper cladding layer (114, see Figure 3); and
an encapsulant (130/150) encapsulating the upper cladding layer (114), the lower cladding layer (115), and the electronic component (120_1), wherein the encapsulant (130/150) entirely covers the electronic component (120_1, see Figure 3) and comprises a portion filled in the gap and contacting the portion of the bottom surface of the [ceramic] layer (112, see Figure 3, where the encapsulant portion 150 fills the gaps between the classing part 115c and the frame part 115a/b/d).
Ewe does not disclose that the layer 112 is a ceramic layer.
However, Grober discloses in Figure 20 a ceramic insulating structure (106).
It would have been obvious to one having ordinary skill in the art to incorporate the use of ceramic materials for insulating layers as taught by Grober into the teachings of Ewe for the purpose of utilizing a suitable or appropriate materials for insulating layers in a semiconductor device (Grober, para. [0058]. Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Regarding claim 10, Ewe discloses wherein the frame part (115a/b/d) of the lower cladding layer (115) comprises a plurality of vent holes penetrating the frame part (115a/b/d, see the gaps outside and between the cladding parts 115a/b/d in Figure 3).
Regarding claim 11, Ewe discloses wherein the ceramic layer (112) is entirely between the upper cladding layer (114) and the lower cladding layer (115, see Figure 3).
Regarding claim 12, Ewe further discloses a circuit layer (126) disposed over and electrically connected to the electronic component (120_1, see Figure 3 and para. [0047]), wherein the circuit layer (126) is partially embedded in the encapsulant (130/150, see Figure 3) and partially exposed by the encapsulant (130/150, see portions of the top surface of the circuit layer connected to the trace 140 through conductive vias, thereby exposing portions of the circuit layer by the encapsulant).
Regarding claim 13, Ewe discloses wherein the electronic component (120_1) is vertically stacked between the circuit layer (126) and the upper cladding layer (114, see Figure 3).
Regarding claim 14, Ewe discloses wherein patterns or thicknesses of the upper cladding layer (114) and the lower cladding layer (115) are substantially symmetrically arranged with respect to the ceramic layer (112, Figure 3 shows substantially parallel/matching trace patterns, and substantially equal thicknesses as measured in the vertical direction of Figure 3).
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ewe et al. (“Ewe” US 2011/0108971) and Cho et al. (“Cho” US 2016/0128186).
Regarding claim 15, Ewe discloses an electronic package (300, Figure 3), comprising:
a heat dissipation core (112, para. [0019] discloses the carrier 112 being made of epoxy resin, which has heat dissipation capabilities) having a first surface (upper surface) and a second surface (lower surface) opposite to the first surface (upper surface, see Figure 3);
a stress buffer structure (114/115) adjacent to at least one of the first surface and the second surface of the heat dissipation core (112, 114 is on the top surface and 115 is on the bottom surface of the heat dissipation core 112);
an electronic component (120_1) disposed over the stress buffer structure (114/115, see Figure 3);
a dielectric structure (130/150) encapsulating the stress buffer structure (114/115) and the electronic component (120_1), wherein in a cross-sectional view, the heat dissipation core (112) comprises a first portion (left bulk portion of 112, see labeled below in annotated Figure 3) and a second portion (right edge portion on right side of 112, see labeled below in annotated Figure 3) separated from the first portion by a gap extending between the first surface and the second surface (the gap is filled by the via/conductive material, which extends between the top and bottom surfaces of the heat dissipation core 112); and
a conductive via (via between traces 140 and 160) passing through a through hole of the heat dissipation core (112, see through hole which the via passes through in Figure 3), wherein the conductive via (via between traces 140 and 160) horizontally overlaps the electronic component (120_1, see Figure 3) and extends along a side of the stress buffer structure (114/115, see Figure 3) until protruding beyond a top surface of the stress buffer structure (see the via extending beyond the top surfaces of both 114/115 stress buffer structures in Figure 3).
Ewe does not disclose that the dielectric structure comprises a first extension filled in the gap and extending between the first surface and the second surface of the heat dissipation core, and that the conductive via contact the dielectric structure in the through hole.
However, Cho discloses in Figure 4 a dielectric structure (11/155) comprises a first extension (groove part 15 where the dielectric material 11 extends through, see Figure 3) filled in the gap (separating first and second portions of the heat dissipation core 10) and extending between the first surface and the second surface of the heat dissipation core (10, see Figure 4), and that the conductive via (150) contacts the dielectric structure (11/155) in the through hole (see Figure 4, the through hole through which the via passes is where a portion of the dielectric structure 11/155 contacts the via).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Cho into the teachings of Ewe to include the dielectric structure’s features above for the purpose of preventing crack propagation through the core/insulating layers (Cho, para. [0028]).
Regarding claim 16, Ewe further discloses a first circuit layer (140) and a second circuit layer (160), wherein the electronic component (120_1) is vertically stacked between the first circuit layer (140) and the second circuit layer (160), and the conductive via (via between circuit layers 140 and 160) contacts the first circuit layer (140) and the second circuit layer (160, see Figure 3).
Regarding claim 17, Ewe discloses wherein the stress buffer structure (114/115) comprises an upper conductive layer (114) and a lower conductive layer (115), and the heat dissipation core (112), the upper conductive layer (114), and the lower conductive layer (115) collectively define the through hole (see Figure 3).
Regarding claim 18, Ewe discloses wherein the through hole (hole which is occupied by the conductive via extending between circuit layers 140 and 160) penetrates the first portion (see annotated Figure 3 below) and extends between the first surface and the second surface of the heat dissipation core (112, see the through hole extending between the upper and lower surfaces of the heat dissipation core 112).
Ewe does not disclose the dielectric structure further comprises a second extension filled in the through hole and extending between the first surface and the second surface of the heat dissipation core.
However, Cho discloses in Figure 4 that the dielectric structure (11/155) further comprises a second extension (155) filled in the through hole (through hole is the via hole 150) and extending between the first surface and the second surface of the heat dissipation core (10, top and bottom surfaces, see Figure 4).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Cho into the teachings of Ewe to include the second extension of the dielectric structure for the purpose of alleviating differences in coefficients of thermal expansion between the core and the via (Cho, para. [0050]).
Regarding claim 19, Ewe discloses wherein the conductive via (via between traces 140 and 160) is electrically connected to the electronic component (120_1, through the drain electrode 126, see Figure 3).
Regarding claim 20, Cho discloses wherein the conductive via (150) is spaced apart from the heat dissipation core (10) by a portion of the second extension (155) of the dielectric structure (11/155, see Figure 4).
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Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899