DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the air vent holes being free from overlapping the ceramic layer as viewed in a direction perpendicular to the top surface of the ceramic layer must be shown or the feature(s) canceled from the claim(s), see claim 9 and Figure 4B. Figure 4B shows the vent holes vertically overlapping the ceramic layer in the cross-sectional view. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 2 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 requires, along with the other limitations, that the third conductive layer is on the lateral surface of the insulating carrier and contacts the first and second conductive layers, thus the claimed first conductive layer element 21B, the second conductive layer element 22, and the third conductive layer element 23 in Figure 5C. However, claim 2 then requires, along with the other limitations, 1) a fourth conductive layer that is spaced apart from the first conductive layer, 2) that the third conductive layer connects the fourth conductive layer and the second conductive layer, and 3) the conductive gel (element 33) attaches the electronic component to the first conductive layer. The listed limitations together would then require the fourth conductive layer to be element 21B and the first conductive layer to be either element 21A or element 22 on the right side in Figure 5C, which contradicts the limitations of claim 1. Applicant has not disclosed an embodiment where both of the following coexist: 1) that the third conductive layer is on a lateral surface of the insulating carrier and contacts the first and second conductive layers, and 2) that the third conductive layer also connects the fourth and second conductive layers while the fourth conductive layer is also spaced apart from the first conductive layer. Thus, new matter has been introduced to the claims. Claims 3-4 depending from the rejected claim 2 noted above are rejected at least on the same basis as the claim(s) from which the dependent claims depend.
Allowable Subject Matter
Claims 1, 6-9, 11-14, and 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record does not fairly disclose or make obvious the claimed devices of claims 1 and 9 as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations “a third conductive layer contacting the first conductive layer and the second conductive layer, wherein the insulating carrier has a first lateral surface contacting the dielectric layer and a second lateral surface contacting the third conductive layer, wherein a lateral surface of the first conductive layer is recessed with respect to the first lateral surface of the insulating carrier, and the first lateral surface of the insulating carrier is recessed with respect to a lateral surface of the second conductive layer” of claim 1 in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 9, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations “wherein a first portion of the frame part of the lower cladding layer comprises a plurality of air vent holes penetrating the first portion, and the air vent holes are free from overlapping the ceramic layer as viewed in a direction perpendicular to the top surface of the ceramic layer” of claim 9 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant' s claims are determined to be novel and non-obvious. Claims 6-8, 11-14, and 21-22 are allowable based on their dependence on claims 1 or 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ewe et al. (“Ewe” US 2011/0108971), Mok (US 2025/0349697), and Cho et al. (“Cho” US 2016/0128186).
Regarding claim 15, Ewe discloses an electronic package (300, Figure 3), comprising:
a heat dissipation core (112, para. [0019] discloses the carrier 112 being made of epoxy resin, which has heat dissipation capabilities) having a first surface (upper surface) and a second surface (lower surface) opposite to the first surface (upper surface, see Figure 3) the heat dissipation core (112) defining a first through hole (see through hole which the via passes through in Figure 3);
a stress buffer structure (114/115) adjacent to at least one of the first surface and the second surface of the heat dissipation core (112, 114 is on the top surface and 115 is on the bottom surface of the heat dissipation core 112);
an electronic component (120_1) disposed over the stress buffer structure (114/115, see Figure 3);
a dielectric structure (130/150) encapsulating the stress buffer structure (114/115) and the electronic component (120_1), wherein in a cross-sectional view, the heat dissipation core (112) comprises a first portion (left bulk portion of 112, see labeled below in annotated Figure 3) and a second portion (right edge portion on right side of 112, see labeled below in annotated Figure 3) separated from the first portion by a gap extending between the first surface and the second surface (the gap is filled by the via/conductive material, which extends between the top and bottom surfaces of the heat dissipation core 112); and
a conductive via (via between traces 140 and 160) passing through the first through hole of the heat dissipation core (112, see through hole which the via passes through in Figure 3), wherein the conductive via (via between traces 140 and 160) horizontally overlaps the electronic component (120_1, see Figure 3) and extends along a side of the stress buffer structure (114/115, see Figure 3) until protruding beyond a top surface of the stress buffer structure (see the via extending beyond the top surfaces of both 114/115 stress buffer structures in Figure 3).
Ewe does not disclose that the conductive via contacts the dielectric structure in the through hole, the dielectric structure comprises a first extension filled in the gap and extending between the first surface and the second surface of the heat dissipation core, and that the stress buffer structure defines a second through hole that is substantially aligned with the first through hole of the heat dissipation core, and a portion of the dielectric structure is within the first through hole and the second through hole and electrically isolates the conductive via from the stress buffer structure.
Mok discloses in Figure 1, however, the stress buffer structure (140) defines a second through hole (cavities with filling medium 136) that is substantially aligned with the first through hole (through hole with vias 110) of the heat dissipation core (102), and a portion of the dielectric structure (136) is within the second through hole (see hole with filling dielectric material 136).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Mok into the teachings of Ewe to include the second through hole and having the dielectric material being within the second through hole for the purpose of improving reliability (see para. [0067]).
Additionally, Cho discloses in Figure 4 a dielectric structure (11/155) comprises a first extension (groove part 15 where the dielectric material 11 extends through, see Figure 3) filled in the gap (separating first and second portions of the heat dissipation core 10) and extending between the first surface and the second surface of the heat dissipation core (10, see Figure 4), and that the conductive via (150) contacts the dielectric structure (11/155) in the through hole (see Figure 4, the through hole through which the via passes is where a portion of the dielectric structure 11/155 contacts the via), and a portion of the dielectric structure (11/155) is within the first through hole (see Figure 3), and electrically isolates the conductive via from the stress buffer structure (see Figure 3).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Cho into the teachings of Ewe and Mok to include the dielectric structure’s features above for the purpose of preventing crack propagation through the core/insulating layers (Cho, para. [0028]).
Regarding claim 16, Ewe further discloses a first circuit layer (140) and a second circuit layer (160), wherein the electronic component (120_1) is vertically stacked between the first circuit layer (140) and the second circuit layer (160), and the conductive via (via between circuit layers 140 and 160) contacts the first circuit layer (140) and the second circuit layer (160, see Figure 3).
Regarding claim 17, Ewe discloses wherein the stress buffer structure (114/115) comprises an upper conductive layer (114) and a lower conductive layer (115), and the upper conductive layer (114), and the lower conductive layer (115) collectively define the second through hole (as incorporated by Mok, see also layers 140/142 of Mok, analogous to the upper and lower conductive layers).
Regarding claim 18, Ewe discloses wherein the first through hole (hole which is occupied by the conductive via extending between circuit layers 140 and 160) penetrates the first portion (see annotated Figure 3 below) and extends between the first surface and the second surface of the heat dissipation core (112, see the through hole extending between the upper and lower surfaces of the heat dissipation core 112).
Ewe does not disclose the dielectric structure further comprises a second extension filled in the first through hole and extending between the first surface and the second surface of the heat dissipation core.
However, Cho discloses in Figure 4 that the dielectric structure (11/155) further comprises a second extension (155) filled in the first through hole (through hole is the via hole 150) and extending between the first surface and the second surface of the heat dissipation core (10, top and bottom surfaces, see Figure 4).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Cho into the teachings of Ewe and Mok to include the second extension of the dielectric structure for the purpose of alleviating differences in coefficients of thermal expansion between the core and the via (Cho, para. [0050]).
Regarding claim 19, Ewe discloses wherein the conductive via (via between traces 140 and 160) is electrically connected to the electronic component (120_1, through the drain electrode 126, see Figure 3), and further comprising a passive component (170) electrically connected to the stress buffer structure, wherein the electronic component (120_1) and the passive component (170) are disposed over and connected to opposite sides of the heat dissipation core (112, see Figure 3 and para. [0057] which discloses the passive component 170 may also be disposed on the other side of the heat dissipation core 112 connected to traces 160), and the passive component is electrically connected to a first circuit layer (140) through the conductive via (the passive component according to para. [0057] would be connected to the traces 160, which are electrically connected to the first circuit layer 140 through the via, see Figure 3).
Regarding claim 20, Cho discloses wherein the conductive via (150) is spaced apart from the heat dissipation core (10) by a portion of the second extension (155) of the dielectric structure (11/155, see Figure 4).
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Response to Arguments
Applicant’s arguments with respect to claim 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to claims 1 and 9 have been fully considered and are persuasive. The prior art rejections of claims 1 and 9 have been withdrawn.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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