DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (claims 12-20) in the reply filed on November 5, 2025, is acknowledged.
Claims 1-11 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 12-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20190103407).
Regarding claim 12, Kim teaches, in Figs. 10 and 11A-11C, a semiconductor structure ([0068]), comprising:
a lower transistor ([0037], [0048]; formed at layer L2 comprising channel CH, source/drain SD1/SD2, gate structure GI, and CL2) including a lower channel (CH at L2) that is elongated horizontally;
an upper transistor ([0044], formed at layer L3 comprising channel CH, source/drain SD1/SD2, gate structure GI, and CL2) vertically stacked over the lower transistor and including an upper channel (CH at L3) that is elongated horizontally;
a lower metal capacitor (DS at top half of L2 and bottom half of L3) electrically connected to and horizontally elongated from the lower transistor (at L2) (see Fig. 11A), the lower metal capacitor including a first lower metal plate (EL1), a lower dielectric layer (DL) that surrounds the first lower metal plate, and a second lower metal plate (EL2) that surrounds the lower dielectric layer (see Fig. 11C, [0046]); and
an upper metal capacitor (DS at top half of L3 and bottom half of L4) vertically stacked over the lower metal capacitor (DS at top half of L2 and bottom half of L3) and electrically connected to and horizontally elongated from the upper transistor (at L3) (see Fig. 11A), the upper metal capacitor including a first upper metal plate (EL1), an upper dielectric layer that surrounds the first upper metal plate (DL), and a second upper metal plate (EL2) that surrounds the upper dielectric layer (see Fig. 11C, [0046]).
Regarding claim 13, Kim further teaches, in Fig. 11A, that the first lower metal plate (EL1 at L2) of the lower metal capacitor is electrically connected to and in-plane with the lower channel (CH) of the lower transistor (at L2), and the first upper metal plate (EL1 at L3) of the upper metal capacitor is electrically connected to and in-plane with the upper channel (CH) of the upper transistor (at L3).
Regarding claim 14, Kim further teaches, in Fig. 11C, that the second upper metal plate (EL2 at bottom half of L4) and the second lower metal plate (the labelled EL2 in Fig. 11C) are electrically connected to each other.
Regarding claim 15, Kim further teaches, in Figs. 11A-11B, that the lower transistor (at L2) further includes a lower gate region (GI, [0048]) that surrounds the lower channel (CH at L2), and the upper transistor (at L3) further includes an upper gate region (GI, [0048]) that surrounds the upper channel (CH at L3).
Regarding claim 16, Kim further teaches, in Fig. 11B and labelled in Fig. 11A, that the upper gate region (GI at L3) and the lower gate region (GI at L2) are electrically connected to each other ([0048]).
Regarding claim 17, Kim further teaches, in Fig. 11B, a metal layer (CL2, [0048]) that surrounds the lower gate region (GI) of the lower transistor (at L2) and the upper gate region (GI) of the upper transistor (at L3).
Regarding claim 18, Kim further teaches, in Fig. 11A, that the lower dielectric layer of the lower metal capacitor (DL at top of L2) is in-plane with the lower gate region (GI) of the lower transistor (at L2), and the upper dielectric layer of the upper metal capacitor (DL at top of L3) is in-plane with the upper gate region (GI) of the upper transistor (at L3).
Claims 12 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20190103407).
Alternatively, regarding claim 12, Kim can be viewed in this embodiment: Kim teaches, in Figs. 7-8, a semiconductor structure ([0068]), comprising:
a lower transistor ([0037], [0048]; formed at layer L2 (Fig. 7) comprising channel CH, source/drain SD1/SD2, gate structure GI, and CL2) (Fig. 8) including a lower channel (CH at L2) that is elongated horizontally;
an upper transistor ([0044], formed at layer L3 (Fig. 7) comprising channel CH, source/drain SD1/SD2, gate structure GI, and CL2) (Fig. 8) vertically stacked over the lower transistor and including an upper channel (CH at L3) that is elongated horizontally;
a lower metal capacitor (DS at top half of L2 and bottom half of L3) electrically connected to and horizontally elongated from the lower transistor (at L2) (see Fig. 8), the lower metal capacitor including a first lower metal plate (EL1), a lower dielectric layer (DL) that surrounds the first lower metal plate, and a second lower metal plate (EL2) that surrounds the lower dielectric layer ([0045]-[0046]); and
an upper metal capacitor (DS at top half of L3 and bottom half of L4) vertically stacked over the lower metal capacitor (DS at top half of L2 and bottom half of L3) and electrically connected to and horizontally elongated from the upper transistor (at L3) (see Fig. 7), the upper metal capacitor including a first upper metal plate (EL1), an upper dielectric layer that surrounds the first upper metal plate (DL), and a second upper metal plate (EL2) that surrounds the upper dielectric layer ([0045]-[0046]).
Regarding claim 19, Kim further teaches, in Figs. 7-8, that the lower metal capacitor (DS at top half of L2 and bottom half of L3) further includes one or more lower pillars (SUP1 and SUP2, [0064]) that separate the second lower metal plate (EL2, see Fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20190103407).
Regarding claim 20, Kim teaches the limitations of claim 12. Kim depicts, in Fig. 11A, that the lower transistor (at L2) is narrower than the lower metal capacitor (DS) horizontally.
However, Kim does not explicitly teach that the lower transistor is narrower than the lower metal capacitor horizontally, because the figures are not drawn to scale.
It is known in the art that a narrower channel length has higher drive current and faster performance, and a wider capacitor plate has increased capacitance.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the lower transistor be narrower than the lower metal capacitor horizontally, because it is known in the art that a narrower channel length has higher drive current and faster performance, and a wider capacitor plate has increased capacitance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIKA HEERA SON whose telephone number is 703-756-4644. The examiner can normally be reached Monday - Friday 12:30-9 PM ET.
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/ERIKA H SON/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893