DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/04/2025 has been entered.
Response to Arguments
Applicant's arguments filed 12/04/2025 have been fully considered but they are not persuasive.
Applicant argues previously cited reference Khan (US 20220122837 A1) is directed to providing a metal heat sink, which requires growing a semiconductor structure in a reverse order on a sapphire substrate, and subsequently removing the sapphire substrate entirely. Thus, Applicant argues, Khan does not disclose a semiconductor structure on a silicon carbide substrate and, in fact, teaches away from such a product.
However, Khan merely discloses the heat sink as a possible substrate carrier for the epilayers grown in reverse order (¶ [0039]). Khan does not disparage the use of other materials as the substrate carrier. In fact, paragraph [0045] explicitly states "The goal here was to develop the ability to transfer a fabricated AlGaN/GaN high electron mobility transistor (HEMT) onto an arbitrary substrate using an excimer laser lift-off (LLO) process." The "arbitrary substrate" may include a silicon carbide substrate such as the substrate disclosed by Yu (US 20020036287 A1).
Further, the abstract of Khan discloses "a new approach for fabricating N-polar devices without the need of developing N-polar AlxGa1-xN buffer layers over substrates such as sapphire, SiC, GaN, AlN and AlxGa1-xN using a simplified material growth process." The above is the intended purpose of the method of manufacturing taught by Khan.
The process of transferring the N-polar device(s) from a sapphire substrate to a metal heat sink (or other "arbitrary substrate") is merely a required by-product resulting from growing the N-polar device(s) in reverse order without need for a buffer layer, not the intended purpose of the disclosed fabrication process as claimed by Applicant.
Regarding Khan, Applicant further argues since the substrate on which the structure was formed is completely removed from the final product and replaced with a metal heatsink, Khan does not disclose amended claim 1.
However, in the instant application, a growth substrate is not claimed nor is a method of forming a semiconductor device which results in the presence of a growth substrate in the final product. Moreover, were a growth substrate or such a method claimed in claims 1 and 17, the product-by-process doctrine would be invoked. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113).
Thus, Khan teaches amended claims 1, 17, and 30. See below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 6-13, 16-18, 20-21, 26-28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khan (US 20220122837 A1; hereinafter Khan).
Regarding claim 1, FIG. 7 of Khan teaches a semiconductor device, comprising:
a semiconductor structure (III-N structure shown in FIG. 7 ¶ [0041]) formed on a substrate (metal heat sink ¶ [0038]-[0039]), the semiconductor structure (III-N structure shown in FIG. 7) comprising a buried layer (GaN/AlN buried layer) at a depth of about 275 Angstroms or greater from a surface of the semiconductor structure (e.g. 526 Angstroms, depth from surface of GaN cap layer to bottom surface of Al0.25Ga0.75N ¶ [0040]), the semiconductor structure (III-N structure shown in FIG. 7) further comprising a confining layer (~3 nm Al0.25Ga0.75N) on the buried layer (GaN/AlN buried layer) a cap layer (50 nm GaN) on the confining layer (~3 nm Al0.25Ga0.75N ¶ [0040]), and the substrate (metal heat sink) below the buried layer (GaN/AlN buried layer); an implanted region (regrown n+-GaN) extending at least partially through the semiconductor structure (III-N structure) and into the buried layer (GaN/AlN buried layer), the implanted region (regrown n+-GaN) comprising a distribution of implanted dopants of a first conductivity type (n-type) extending into the buried layer (GaN/AlN buried layer); and an electrode (S/D) on the implanted region (regrown n+-GaN).
Regarding claim 2, Khan teaches the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the buried layer (GaN/AlN buried layer) is at a depth of about 500 Angstroms or greater from the surface of the semiconductor structure (e.g. 526 Angstroms ¶ [0040], depth from surface of ~50 nm GaN cap layer to bottom surface of ~3 nm Al0.25Ga0.75N).
Regarding claim 6, Khan teaches the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the electrode (S/D) comprises an ohmic contact (¶ [0041]).
Regarding claim 7, Khan the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the buried layer (GaN/AlN buried layer) comprises a Group III-nitride layer (i.e. GaN).
Regarding claim 8, Khan teaches the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the semiconductor structure (III-N structure) comprises an N-polar Group III-nitride semiconductor structure (N-polar GaN/AlGaN ¶ [0035]) comprising an N-face at the surface of the semiconductor structure (¶ [0036]).
Regarding claim 9, Khan teaches the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the confining layer (~3 nm Al0.25Ga0.75N) is a first confining layer (~3 nm Al0.25Ga0.75N) on a first surface of the buried layer (top surface of GaN/AlN buried layer), and wherein the semiconductor structure (III-N structure) further comprises a second confining layer (~10 nm Al0.38Ga0.62N) on a second surface of the buried layer (bottom surface of GaN/AlN buried layer).
Regarding claim 11, Khan teaches the semiconductor device of claim 9, and FIG. 7 of Khan further teaches wherein the cap layer (50 nm GaN) has a thickness in a range of about 250 Angstroms to about 1000 Angstroms (e.g. 500 Angstroms ¶ [0040]).
Regarding claim 12, Khan teaches the semiconductor device of claim 9, and FIG. 7 of Khan further teaches wherein: wherein the first confining layer (~3 nm Al0.25Ga0.75N) comprises AlwGa1-wN, where w is in a range of about 0.1 to about 0.4 (¶ [0040]); wherein the buried layer (GaN/AlN buried layer) comprises AlxGa1-xN, where x is less than about 0.1 (i.e. GaN); wherein the second confining layer (~10 nm Al0.38Ga0.62N) comprises AlyGa1-yN, where y is in a range of about 0.1 to about 0.4; and wherein the cap layer (50 nm GaN) comprises AlzGa1-zN, where w is in less than about 0.1 (i.e. GaN ¶ [0040]).
Regarding claim 13, Khan teaches the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the semiconductor device comprises a mesa (mesa between n+-GaN) and a recess (recess of n+-GaN, see examiner annotated FIG. 7).
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Regarding claim 16, Khan teaches the semiconductor device of claim 1, and FIG. 7 of Khan further teaches wherein the semiconductor device (e.g. FIG. 7) is a high electron mobility transistor device (GaN-AlGaN HEMT ¶ [0041]).
Regarding claim 17, FIGS. 6-7 of Khan teaches a transistor device, comprising: an N-polar Group III-nitride semiconductor structure (N-polar epilayer stack ¶ [0004]) having an N face (N-polar face) at a surface of the semiconductor structure (N-polar epilayer stack ¶ [0036]), the semiconductor structure (N-polar epilayer stack) formed on a substrate (metal heat sink ¶ [0038]-[0039]), the semiconductor structure (e.g. FIG. 7) comprising: a buried channel layer (GaN/AlN buried layer); a confining layer (~3 nm Al0.25Ga0.75N) on a first surface of the buried channel layer (top surface of GaN/AlN buried layer ¶ [0040]); a barrier layer (~10 nm Al0.38Ga0.62N) on a second surface of the buried channel layer (bottom surface of GaN/AlN buried layer), the barrier layer (~10 nm Al0.38Ga0.62N) above the substrate (metal heat sink); and an implanted region (n+-GaN) extending at least partially through the confining layer (~3 nm Al0.25Ga0.75N) and into the buried channel layer (GaN/AlN buried layer), the implanted region (n+-GaN) comprising a distribution of implanted dopants of a first conductivity type (n+) extending into the buried channel layer (GaN/AlN buried layer); and an electrode (S/D) on the implanted region (n+-GaN).
Regarding claim 18, Khan teaches the transistor device of claim 17, and FIG. 7 of Khan further teaches wherein the implanted region (n+-GaN) extends to a depth of about 275 Angstroms or greater into the N-polar Group III-nitride semiconductor structure ( ¶ [0040] N-polar epilayer stack, i.e. more than 526 Angstroms, see FIG. 7).
Regarding claim 20, Khan teaches the transistor device of claim 17, and FIG. 7 of Khan further teaches wherein the electrode (S/D) comprises an ohmic source contact (S) or an ohmic drain contact (D) for the transistor device (e.g. FIG. 7 ¶ [0041]).
Regarding claim 21, Khan teaches the transistor device of claim 17, and FIG. 7 of Khan further teaches further comprising a cap layer (50 nm GaN) on the confining layer (~3 nm Al0.25Ga0.75N), wherein the cap layer (50 nm GaN) has a thickness in a range of about 250 Angstroms to about 1000 Angstroms (i.e. 500 Angstroms ¶ [0040]).
Regarding claim 26, Khan teaches the transistor device of claim 21, and FIG. 7 of Khan further teaches further comprising a gate contact (G) is at least partially located in an atomic layer etch (ALE) defined trench in the cap layer (gate-recess ¶ [0041]).
The process limitation of “atomic layer etch (ALE) defined” found in product claim 26 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 26 does not require defining the trench in the cap layer through an atomic layer etch, but simply that a gate contact is at least partially located in a trench in the cap layer.
Regarding claim 27, Khan teaches the transistor device of claim 17, wherein further comprising an atomic layer deposition (ALD) defined passivation layer (gate insulator ¶ [0014]).
The process limitation of “atomic layer deposition (ALD) defined” found in product claim 27 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 27 does not require defining the passivation layer through atomic layer deposition, but simply that a passivation layer is present.
Regarding claim 28, Khan teaches the transistor device of claim 17, and FIG. 7 of Khan further teaches wherein the transistor device (e.g. FIG. 7) is a high electron mobility transistor device (GaN-AlGaN HEMT ¶ [0041]).
Regarding claim 30, FIGS. 1-7 of Khan teaches a method of forming a semiconductor device, comprising: forming a semiconductor structure (III-N structure of FIG. 7) on a substrate (Sapphire substrate shown in FIG. 1 ¶ [0037]), the semiconductor structure (III-N structure of FIG. 7) comprising a buried layer (GaN/AlN buried layer) and one or more confining layers (~3 nm Al0.25Ga0.75N, ~10 nm Al0.38Ga0.62N) above the substrate (Sapphire substrate shown in FIG. 1), the buried layer (GaN/AlN buried layer) being at a depth of about 275 Angstroms or greater from a surface of the semiconductor structure (e.g. at least 526 Angstroms, depth from surface of GaN cap layer to bottom surface of Al0.25Ga0.75N), the semiconductor structure further comprising a cap layer (50 nm GaN) on one of the one or more confining layers (~3 nm Al0.25Ga0.75N, ~10 nm Al0.38Ga0.62N ¶ [0040]); and implanting dopants (n+ dopants) into the semiconductor structure (III-N structure of FIG. 7) to form an implanted region (n+-GaN) in the semiconductor structure (III-N structure), the implanted region (n+-GaN) extending at least partially through the semiconductor structure (III-N structure) and into the buried layer (12 nm GaN, 7-10 Angstrom AlN), the implanted region (n+-GaN) comprising a distribution of implanted dopants (n+ dopants) of a first conductivity type (n-type) extending into the buried layer (12 nm GaN, 7-10 Angstrom AlN).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 3 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Suvorov (US 20110092057 A1; hereinafter Suvorov).
Regarding claim 3, Khan teaches the semiconductor device of claim 1.
Khan does not teach wherein the distribution of implanted dopants of the first conductivity type in the implanted region has a peak dopant concentration of implanted dopants at a depth in the implanted region within about 50 Angstroms or less of the buried layer.
FIGS. 4-5 of Suvorov teach a semiconductor device (e.g. FIG. 4), comprising: a semiconductor structure (10, 20, 22, 30) comprising a buried layer (20 ¶ [0029]) at a depth of about 275 Angstroms or greater from a surface of the semiconductor structure (22 has a thickness between 1 and 1000 Angstroms ¶ [0035]); an implanted region (30) extending at least partially through the semiconductor structure (10, 20, 22, 30) and into the buried layer (20 ¶ [0044]), the implanted region (30) comprising a distribution of implanted dopants of a first conductivity type (n-type) extending into the buried layer (20 ¶ [0045]); and an electrode (44) on the implanted region (30 ¶ [0054]); wherein the distribution of implanted dopants of the first conductivity type in the implanted region (30) has a peak dopant concentration of implanted dopants at a depth in the implanted region (30) within about 50 Angstroms or less of the buried layer (20 ¶ [0045] “the implanted ions form a concentration profile having a peak… the implant peak may be placed away from (i.e. above or below) the interface between the barrier layer 22 and the channel layer 20”, see FIG. 5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the distribution of implanted dopants taught by Suvorov for the purpose of activating dopant ions in the source/drain regions without substantially reducing conductivity/degrading of the channel region (¶ [0010],[0028],[0047]).
Regarding claim 19, Khan teaches the transistor device of claim 17.
Khan does not teach wherein the distribution of implanted dopants of the first conductivity type in the implanted region has a peak dopant concentration of implanted dopants at a depth in the implanted region within about 50 Angstroms or less of the buried channel layer.
FIGS. 4-5 of Suvorov teach a semiconductor device (e.g. FIG. 4), comprising: a semiconductor structure (10, 20, 22, 30) comprising a buried layer (20) at a depth of about 275 Angstroms or greater from a surface of the semiconductor structure (22 has a thickness between 1 and 1000 Angstroms ¶ [0035]); an implanted region (30) extending at least partially through the semiconductor structure (10, 20, 22, 30) and into the buried layer (20 ¶ [0044]), the implanted region (30) comprising a distribution of implanted dopants of a first conductivity type (n-type) extending into the buried layer (20 ¶ [0045]); and an electrode (44) on the implanted region (30 ¶ [0054]); wherein the distribution of implanted dopants of the first conductivity type in the implanted region (30) has a peak dopant concentration of implanted dopants at a depth in the implanted region (30) within about 50 Angstroms or less of the buried layer (20 ¶ [0045] “the implanted ions form a concentration profile having a peak… the implant peak may be placed away from (i.e. above or below) the interface between the barrier layer 22 and the channel layer 20”, see FIG. 5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the implantation region taught by Suvorov for the purpose of avoiding a substantial increase in resistance and/or a substantial decrease in charge carrier mobility in the channel region while sufficiently heating the source/drain regions (¶ [0028]).
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Inoue et al. (US 20110284865 A1; hereinafter Inoue).
Regarding claim 4, Khan teaches the semiconductor device of claim 1.
Khan does not teach wherein a peak dopant concentration of implanted dopants is at least about 1 x 1018 ions/cm3.
FIG. 2 of Inoue teaches a GaN HEMT comprising a buried layer (11 ¶ [0032]); an implanted region (13A-B) extending at least partially into the buried layer (11), the implanted region (13A-B) comprising a distribution of implanted dopants of a first conductivity type (n-type) extending into the buried layer (11 ¶ [0033]); and wherein a peak dopant concentration of implanted dopants is at least about 1 x 1018 ions/cm3 (¶ [0033]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the GaN HEMT taught by Inoue for the purpose of forming an ohmic contact (¶ [0059]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the peak dopant concentration determines the resulting device performance making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Regarding claim 5, Khan teaches the semiconductor device of claim 1.
Khan does not teach wherein the implanted dopants comprise silicon, germanium, sulfur, or oxygen ions.
FIG. 2 of Inoue teaches a GaN HEMT comprising a buried layer (11 ¶ [0032]); an implanted region (13A-B) extending at least partially into the buried layer (11), the implanted region (13A-B) comprising a distribution of implanted dopants of a first conductivity type (n-type) extending into the buried layer (11 ¶ [0033]); and wherein the implanted dopants comprise silicon, germanium, sulfur, or oxygen ions (e.g. Si ¶ [0094]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the GaN HEMT taught by Inoue for the purpose of forming an ohmic contact (¶ [0059]).
Claims 14, 22, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Romanczyk et al. (US 20220223429 A1; hereinafter Romanczyk).
Regarding claim 14, Khan teaches the semiconductor device of claim 13.
Khan does not teach wherein the implanted region is beneath the recess.
FIGS. 3 & 7C of Romanczyk teaches a semiconductor device, comprising: a semiconductor structure (GaN-AlGaN structure) comprising a buried layer (GaN channel ¶ [0036],[0126]); an implanted region (regrown n+) extending at least partially through the semiconductor structure (GaN-AlGaN structure) and into the buried layer (GaN channel ¶ [0128]), the implanted region (regrown n+) comprising a distribution of implanted dopants of a first conductivity type (n+) extending into the buried layer (GaN channel, see FIG. 7C); and an electrode (ohmic metal) on the implanted region (regrown n+ ¶ [0128]-[0131]); wherein the semiconductor device (e.g. FIG. 3/7C) comprises a mesa (GaN cap mesa) and a recess (recess occupied by ohmic metal); wherein the implanted region (regrown n+) is beneath the recess (recess occupied by ohmic metal, see examiner annotated FIG. 7C below).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the ohmic contacts taught by Romanczyk for the purpose of reducing contact resistance (¶ [0128]).
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Regarding claim 22, Khan teaches the transistor device of claim 21.
Khan does not teach wherein the transistor device further comprises a recess in the cap layer, wherein the implanted region is beneath the recess.
FIGS. 3 & 7C of Romanczyk teaches a semiconductor device, comprising: a semiconductor structure (GaN-AlGaN structure) comprising a buried layer (GaN channel ¶ [0036],[0126]); an implanted region (regrown n+) extending at least partially through the semiconductor structure (GaN-AlGaN structure) and into the buried layer (GaN channel ¶ [0128]), the implanted region (regrown n+) comprising a distribution of implanted dopants of a first conductivity type (n+) extending into the buried layer (GaN channel, see FIG. 7C); and an electrode (ohmic metal) on the implanted region (regrown n+ ¶ [0128]-[0131]); wherein the semiconductor device (e.g. FIG. 3/7C) comprises a mesa (GaN cap mesa) and a recess in the cap layer (recess in MOCVD SiN occupied by ohmic metal ¶ [0128],[0187]); wherein the implanted region (regrown n+) is beneath the recess (recess occupied by ohmic metal, see examiner annotated FIG. 7C above).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the ohmic contacts taught by Romanczyk for the purpose of reducing contact resistance (¶ [0128]).
Regarding claim 24, the process limitation of “atomic layer etch (ALE) defined recess” found in product claim 24 invokes the product-by-process doctrine. Product-by-process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps (MPEP § 2113). Anticipation of claim 24 does not require defining the recess in the cap layer through an atomic layer etch, but simply that the recess is present.
Khan as modified teaches the transistor device of claim 22, and FIGS. 3 & 7C of Romanczyk further teach wherein the semiconductor device comprises the recess (recess occupied by ohmic metal).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Yu et al. (US 20020036287 A1; hereinafter Yu).
Regarding claim 15, Khan teaches the semiconductor device of claim 1.
Khan does not teach wherein the substrate comprises a silicon carbide substrate.
FIGS. 1-2 of Yu teach an N-polar HFET device including a silicon carbide substrate (12 ¶ [0016],[0021]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the N-polar HFET taught by Yu since it has been held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945), In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960), and MPEP 2144.07 Art Recognized Suitability for an Intended Purpose.
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Romanczyk, and further in view of Moon et al. (Moon, J.S., et al. (2020), High-speed graded-channel AlGaN/GaN HEMTs with power added efficiency >70% at 30 GHz. Electron. Lett., 56: 678-680.; hereinafter Moon).
Regarding claim 23, Khan as modified teaches the transistor device of claim 22.
Khan as modified does not teach wherein the recess has a depth in a range of about 125 Angstroms to about 750 Angstroms.
FIG. 1 of Moon teaches an AlGaN/GaN HEMT device comprising a recess (opening in SiN passivation) in a cap layer (SiN passivation); wherein the cap layer (SiN passivation) has a thickness in a range of about 250 Angstroms to about 1000 Angstroms (e.g. 70 nm or 700 Angstroms); and wherein the recess (opening in SiN passivation) has a depth in a range of about 125 Angstroms to about 750 Angstroms (opening extends through 700 Angstrom thick SiN passivation, see FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the HEMT device taught by Moon for the purpose of reducing contact resistance and forming ohmic contacts.
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Xie et al. (US 20190035895 A1; hereinafter Xie).
Regarding claim 25, Khan teaches the transistor device of claim 17.
Khan does not teach wherein the confining layer or the barrier layer comprises ScAlN or ScAlGaN.
FIG. 6 of Xie teaches a HEMT device comprising a confining layer (24) on a first surface of a buried channel layer (18), wherein the confining layer comprises ScAlN (¶ [0033]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the ScAlN barrier layer taught by Xie for the purpose of providing better lattice matching with GaN and a relatively higher sheet charge density within the channel layer (¶ [0033]).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Khan in view of Moon.
Regarding claim 29, Khan teaches the transistor device of claim 17.
Khan does not teach where in the transistor device is operable at frequencies in a range of about 10 GHz to about 150 GHz.
FIG. 1 of Moon teaches a HEMT device operable at frequencies in a range of about 10 GHz to about 150 GHz (e.g. 30 GHz; abstract, FIG. 2).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught by Khan with the HEMT device taught by Moon for the purpose of forming a high-efficiency millimeter-wave power amplifier (abstract).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nora T Nix whose telephone number is (571)270-1972. The examiner can normally be reached Monday - Friday 9:00 am - 5:00 pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nora T. Nix/Assistant Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891