DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 5-8, 10-11, 15-18, and 20 are amended. Claims 4, 7-10, and 17-20 are withdrawn. Claims 1-3, 5-6, and 11-16 are present for examination.
Specification
The title objection of September 05, 2025 has been withdrawn.
Response to Arguments
Applicant's arguments filed January 02, 2026 have been fully considered but they are not persuasive.
The amendments now require claims 1-3, 5-6 and 11-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 and 16 of Application No. 17/955,520.
It is further noted, as the first set of superlattice stacked layers and second set of superlattice stacked layers are materially different in compositions of each elemental species present in the compound semiconductor material.
In the interest of compact prosecution, the Examiner suggests the Applicant more clearly define the following limitations;
advantages of aligning the gate of the field-effect transistor with the via-holes and the thermal conductive material (i.e. thereby dissipating the heat generated from the active region; Instant Application, [0112]).
projected area of one of the thermal conductive material (i.e. projected area of one of the thermal conductive material can be equal to or less than a projected area of the gate; Instant Application, [0112])
The Examiner is available at the number below for an interview to discuss ideas at the Applicant’s convenience.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 5-6 and 11-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11 and 16 of Application No. 17/955,520. Although the claims at issue are not identical, they are not patentably distinct from each other because the first and second superlattice stacked layers comprise alternating grouping of AlxiGa(1-xi)N/GaN and InzkGa(1-zk)N/GaN superlattice layer-pairs groups, in which i is an integer representing ith layer, xi is a mole fraction ranging from 0.3 ≤ xi < 1, k is an integer representing kth layer, and zk is a mole fraction ranging from 0.3 ≤ zk < 1.
Instant Application (17/961,544)
Application (17/955,520)
Claim 1, 5, 11, and 15
the first superlattice stacked layers comprises a plurality of AlxiGa(1-xi)N/GaN superlattice layer-pairs groups, in which i is an integer representing ith layer and xi is a mole fraction ranging from 0.3 ≤ xi < 1.
Claim 11, the first set of first superlattice stacked layers comprise a plurality of first set layer groups and the second set of first superlattice stacked layers comprise a plurality of second set layer groups, each of the plurality of first set layer groups and the second set layer groups sequentially comprises GaN superlattice layer and AlGaN superlattice layer, the second superlattice stacked layers comprise a plurality of second layer groups, each of the plurality of second layer groups sequentially comprises GaN superlattice layer and InGaN superlattice layer.
Claim 16, the first set superlattice stacked layers comprise an ith AlGaN superlattice layer composed of AlxiGa(1-xi)N, the second set superlattice stacked layers comprise an jth AlGaN superlattice layer composed of AlyjGa(1-yj)N and the second superlattice stacked layers comprise an kth InGaN superlattice layer composed of InzkGa(1-zk)N, xi, yj and zk are designed ratio values range from 0.3 to 1.
Claim 1, 6, 11, and 16
the second superlattice stacked layers comprises a plurality of InzkGa(1-zk)N/GaN superlattice layer-pairs groups, in which k is an integer representing kth layer and zk is a mole fraction ranging from 0.3 ≤ zk < 1.
Claim 11, the first set of first superlattice stacked layers comprise a plurality of first set layer groups and the second set of first superlattice stacked layers comprise a plurality of second set layer groups, each of the plurality of first set layer groups and the second set layer groups sequentially comprises GaN superlattice layer and AlGaN superlattice layer, the second superlattice stacked layers comprise a plurality of second layer groups, each of the plurality of second layer groups sequentially comprises GaN superlattice layer and InGaN superlattice layer.
Claim 16, the first set superlattice stacked layers comprise an ith AlGaN superlattice layer composed of AlxiGa(1-xi)N, the second set superlattice stacked layers comprise an jth AlGaN superlattice layer composed of AlyjGa(1-yj)N and the second superlattice stacked layers comprise an kth InGaN superlattice layer composed of InzkGa(1-zk)N, xi, yj and zk are designed ratio values range from 0.3 to 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 11-16 are rejected under 35 U.S.C. 103 as being unpatentable over Azize (US 2016/0351564 A1) in view of Kojima (US 2020/0083367 A1) in view of Imamura (WO 2022176051 A1).
Claim 1, Azize discloses a semiconductor device (Figs. 1A, 6A-6B, 7, 10, and 19), comprising:
a thermal conductive substrate (substrate 602 is made of the same material as substrate 2, including SiC, Si, GaN, and sapphire (e.g. Al203) which is known in the art as a material for a thermal conductive substrate, [0047], Figs. 1A and 10), wherein the thermal conductive substrate 602 that is a semiconductor wafer (602 is a thermal conductive substrate that is a semiconductor wafer, [0047], Figs. 1A and 10);
a nucleation layer (nucleation layer, hereinafter 603, [0047], Figs. 1A and 10) disposed on the thermal conductive substrate 602 (nucleation layer is disposed on 602, [0047], Figs. 1A and 10);
a buffer layer (buffer layer 604, [0047], Figs. 1A and 10) disposed on the nucleation layer 603 (604 is disposed on 603, [0047], Figs. 1A and 10);
a superlattice stack (channel 606 and band-offset layer 630 form the superlattice stack in addition to alternating sublayers 618/619/612/611, [0086], Figs. 6A/6B and 10) disposed on the buffer layer 604 (606 and 630 are disposed on 604, Figs. 6A/6B and 10), wherein the superlattice stack comprises a first set of superlattice stacked layers (first set of first superlattice stacked layers, hereinafter, first set of superlattice stacked layers 618/619_1, para [0110], Figs. 7 and 10) and a second set of superlattice stacked layers (nth sublayer 619 and n-1th sublayer 618 are a second superlattice stacked layers, wherein n = 2, further including selective etchable sublayer 611, hereinafter, second set of superlattice stacked layers 618/619_2, [0085], Figs. 6A/6B and 10) disposed on the first set of superlattice stacked layers (second set of superlattice stacked layers 618/619_2 is disposed on the first set of superlattice stacked layers 618/619_1, [0110], Figs. 7 and 10), with the first set of superlattice stacked layers 618/619_1 comprising a material different from the second set of superlattice stacked layers 618/619_2 (first set of superlattice stacked layers 618/619_1 (i.e. n=1) comprising a material different from the second set of superlattice stacked layers 618/619_2 (i.e. n=2) as each sublayer may be selectively etchable according to odd and even values of n, wherein n=1 and n=2 are previously accounted for, [0082], Fig. 10), the first set of superlattice stacked layers (first and second set of first superlattice stacked layers, hereinafter 618/619_1, [0110], Figs. 7 and 10) configured to form a two-dimensional electron gas (2DEG) carrier transport 618/619_1 form a 2DEG carrier transport to generate a first current channels group via recessed gate 1012, [0099], Fig. 10) and the second set of superlattice stacked layers 618/619_2 configured to form a two dimensional hole gas (2DHG) carrier transport to generate a second current channel group (618/619_2 form a 2DHG carrier transport to generate a second current channels group via recessed gate 1022 upon appropriate doping, [0098], Figs. 9 and 10);
a cap layer (first sublayer 611 is a cap layer within larger cap structure 608, [0080-0081], Figs. 6A-6B and 10) disposed on the superlattice stack (611 is disposed on 618/619_1 and 618/619_2, Fig. 10);
a field-effect transistor (transistor 1 1010 is a first transistor area and transistor 2 1020 is a second transistor area, [0099], Fig. 10) comprising a gate (gate 1012, [0099], Fig. 10) disposed within a contact via (gate 1012 is disposed within a gate trench contact via, [0099], Fig. 10) passing through the cap layer 611 until contacting the second set of superlattice stacked layers 618/619_2 (gate 1012 is disposed within a gate trench contact via passing through the cap layer 611 until contacting the second set of superlattice stacked layers 618/619_2, [0099], Fig. 10) to control both the first current channel group and the second current channel group (gate 1012 controls the respective current channel group of each of the sets of superlattice stacked layers, wherein the first current channel group is respective to the first set of superlattice stacked layers 618/619_1 and second set of superlattice stacked layers 618/619_2, [0099], Fig. 10);
wherein the first set of superlattice stacked layers comprise a plurality of AlxiGa(1-xi)N/GaN superlattice layer-pairs groups (Azize, first set layer groups within 618/619_2 further include AlxInyGazN wherein x, y, and z further denote species composition and include GaN when x and y are 0, [0084]; Kojima, Figs. 4A and 4C), in which i is an integer representing ith layer and xi is a mole fraction ranging from 0.3 ≤ xi < 1 (Azize, all sublayers may vary their composition gradient according to x ≥ 0, y, z ≤ 1, wherein the elemental composition of x, y, and z within AlxInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C);
wherein the second set of superlattice stacked layers comprises a plurality of InzkGa(1-zk)N/GaN superlattice layer-pairs groups (Azize, second superlattice stacked layers comprise an AlxInyGazN superlattice layer wherein x, y, and z further denote species composition and include InyGazN when x and z are 0 and varies with respect to each sublayer and include GaN when x and y are 0, [0084]-[0085]; Kojima, Figs. 4A and 4C), in which k is an integer representing kth layer and zk is a mole fraction ranging from 0.3 ≤ zk < 1 (Azize, all sublayers may vary their composition gradient according to x ≥ 0, y, z ≤ 1, wherein the elemental composition of x, y, and z within AlxInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C).
Azize does not explicitly disclose a thermal conductive substrate embedded with a plurality of via-holes filled with a thermal conductive material.
However, Kojima discloses semiconductor device 5 further including thermal conductive substrate (Kojima, substrate 110 is a thermal conductive substrate as it is patterned and may include a plurality of through holes extending from the front surface to the back surface, [0042], Figs. 4A and 4C; Azize, Figs. 1A and 10) embedded with a plurality of via-holes filled with a thermal conductive material (Kojima, 110 is filled with thermal conductive material as metal layer 30 further includes contact layer 33, barrier metal layer 37, and metal bonding layer 35, [0039], Figs. 4A and 4C; Azize, Figs. 1A and 10). The combination to utilize a thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of enhancing the thermal dissipation as well as to mitigate strain of the semiconductor interface (Kojima, [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of enhancing the thermal dissipation as well as to mitigate strain of the semiconductor interface.
Azize/Kojima does not explicitly disclose wherein one of the via-holes is aligned with the gate of the field-effect transistor.
However, Imamura (WO 2022176051 A1, referencing US 2024/0096968 A1 as a convenient translation) discloses wherein one of the via-holes (Imamura, via hole 16, Fig. 13; Azize, Figs. 1A and 10; Kojima, metal layer 30 further includes contact layer 33, barrier metal layer 37, and metal bonding layer 35, [0039], Figs. 4A and 4C) is aligned with the gate of the field-effect transistor (Imamura, via hole 16 is aligned with the gate electrode 14, [0032], Fig. 13; Azize, Figs. 1A and 10; Kojima, metal layer 30 further includes contact layer 33, barrier metal layer 37, and metal bonding layer 35, [0039], Figs. 4A and 4C). The combination would allow for the utilization of a thermally conductive via aligned with the gate electrode to serve as an improvement of high frequency characteristics in the resultant HEMT device (Imamura, [0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a thermally conductive via aligned with the gate electrode to serve as an improvement of high frequency characteristics in the resultant HEMT device (Imamura, [0005]).
Claim 2, Azize/Kojima discloses the semiconductor device (Azize, Figs. 1A and 10; Kojima, Figs. 4A and 4C) of claim 1.
Azize/Kojima discloses wherein the metallic material filling in the embedded via-holes (Kojima, concave portions 13 may further include a plurality of through holes extending from the front surface to the back surface, [0042], Figs. 4A and 4C; Azize, Figs. 1A and 10) of thermal conductive native-substrate (Kojima, substrate 110, Figs. 4A and 4C; Azize, Figs. 1A and 10) is AuTi alloy, AuSn alloy or AuNi alloy (Kojima, metal bonding layer 35 includes gold-tin (AuSn) alloy), [0028], further, contact layer 33 includes a metal film having a multilayered structure in which thin films of titanium (Ti), nickel (Ni), and gold (Au) are stacked and then heat treated wherein the stacked layers further undergo a solid-state diffusion process yielding the resulting gold alloys, [0027], Figs. 4A and 4C; Azize, Figs. 1A and 10).
Claim 3, Azize/Kojima discloses a semiconductor device (Azize, Figs. 1A, 6A-6B, 7, 10, and 19; Kojima, Figs. 4A and 4C) of claim 1.
Azize discloses wherein the semiconductor wafer of the native-substrate 602 is SiC, Si, GaN, or Al203 (Azize, substrate 602 is made of the same material as substrate 2, including SiC, Si, GaN, and sapphire (e.g. Al203) which is known in the art as a material for a thermal conductive substrate, [0047], Figs. 1A and 10; Kojima, Figs. 4A and 4C).
Claim 5, Azize/Kojima discloses the semiconductor device (Azize, Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C) of claim 1.
Azize disclosesxInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C).
Claim 6, Azize/Kojima discloses the semiconductor device (Azize, Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C) of claim 5.
Azize discloses wherein sublayers may vary their composition gradient according to x ≥ 0, y, z ≤ 1, wherein the elemental composition of x, y, and z within AlxInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C).
Claim 11, Azize discloses a semiconductor device (Figs. 1A, 6A-6B, 7, 10, and 19), comprising:
a thermal conductive substrate (substrate 602 is made of the same material as substrate 2, including SiC, Si, GaN, and sapphire (e.g. Al203) which is known in the art as a material for a thermal conductive substrate, [0047], Figs. 1A and 10), wherein the thermal conductive substrate 602 that is a semiconductor wafer (602 is a thermal conductive substrate that is a semiconductor wafer, [0047], Figs. 1A and 10);
a superlattice stack (channel 606 and band-offset layer 630 form the superlattice stack in addition to alternating sublayers 618/619/612/611, [0086], Figs. 6A/6B and 10) disposed on the buffer layer 604 (606 and 630 are disposed on 604, Figs. 6A/6B and 10), wherein the superlattice stack comprises a first set of superlattice stacked layers (first set of first superlattice stacked layers, hereinafter, first set of superlattice stacked layers 618/619_1, para [0110], Figs. 7 and 10) and a second set of superlattice stacked layers (nth sublayer 619 and n-1th sublayer 618 are a second superlattice stacked layers, wherein n = 2, further including selective etchable sublayer 611, hereinafter, second set of superlattice stacked layers 618/619_2, [0085], Figs. 6A/6B and 10) disposed on the first set of superlattice stacked layers (second set of superlattice stacked layers 618/619_2 is disposed on the first set of superlattice stacked layers 618/619_1, [0110], Figs. 7 and 10), with the first set of superlattice stacked layers 618/619_1 comprising a material different from the second set of superlattice stacked layers 618/619_2 (first set of superlattice stacked layers 618/619_1 (i.e. n=1) comprising a material different from the second set of superlattice stacked layers 618/619_2 (i.e. n=2) as each sublayer may be selectively etchable according to odd and even values of n, wherein n=1 and n=2 are previously accounted for, [0082], Fig. 10), the first set of superlattice stacked layers (first and second set of first superlattice stacked layers, hereinafter 618/619_1, [0110], Figs. 7 and 10) configured to form a two-dimensional electron gas (2DEG) carrier transport 618/619_1 form a 2DEG carrier transport to generate a first current channels group via recessed gate 1012, [0099], Fig. 10) and the set of superlattice stacked layers 618/619_2 configured to form a two dimensional hole gas (2DHG) carrier transport to generate a second current channel group (618/619_2 form a 2DHG carrier transport to generate a second current channels group via recessed gate 1022 upon appropriate doping, [0098], Figs. 9 and 10);
a field-effect transistor (transistor 1 1010 is a first transistor area and transistor 2 1020 is a second transistor area, [0099], Fig. 10) electrically connected to the superlattice stack (1010 and 1020 are electrically connected to the superlattice stack, including multi-layer structure 600/650, [0101], Figs. 6A/6B and 10); and
a buffer layer (first sublayer 611 is a buffer layer, [0080-0081], Figs. 6A-6B and 10) disposed on the superlattice stack 611 is disposed on 1010 and 1020 as both transistors 1 and 2 have buried gates, Fig. 10);
a field-effect transistor (transistor 1 1010 is a first transistor area and transistor 2 1020 is a second transistor area, [0099], Fig. 10) comprising a gate (gate 1012, [0099], Fig. 10) disposed within a contact via (gate 1012 is disposed within a gate trench contact via, [0099], Fig. 10) passing through the cap layer 611 until contacting the second set of superlattice stacked layers 618/619_2 (gate 1012 is disposed within a gate trench contact via passing through the cap layer 611 until contacting the second set of superlattice stacked layers 618/619_2, [0099], Fig. 10) to control both the first current channel group and the second current channel group (gate 1012 controls the respective current channel group of each of the sets of superlattice stacked layers, wherein the first current channel group is respective to the first set of superlattice stacked layers 618/619_1 and second set of superlattice stacked layers 618/619_2, [0099], Fig. 10);
wherein the first set of superlattice stacked layers comprise a plurality of AlxiGa(1-xi)N/GaN superlattice layer-pairs groups (Azize, first set layer groups within 618/619_2 further include AlxInyGazN wherein x, y, and z further denote species composition and include GaN when x and y are 0, [0084]; Kojima, Figs. 4A and 4C), in which i is an integer representing ith layer and xi is a mole fraction ranging from 0.3 ≤ xi < 1 (Azize, all sublayers may vary their composition gradient according to x ≥ 0, y, z ≤ 1, wherein the elemental composition of x, y, and z within AlxInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C);
wherein the second set of superlattice stacked layers comprises a plurality of InzkGa(1-zk)N/GaN superlattice layer-pairs groups (Azize, second superlattice stacked layers comprise an AlxInyGazN superlattice layer wherein x, y, and z further denote species composition and include InyGazN when x and z are 0 and varies with respect to each sublayer and include GaN when x and y are 0, [0084]-[0085]; Kojima, Figs. 4A and 4C), in which k is an integer representing kth layer and zk is a mole fraction ranging from 0.3 ≤ zk < 1 (Azize, all sublayers may vary their composition gradient according to x ≥ 0, y, z ≤ 1, wherein the elemental composition of x, y, and z within AlxInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C).
Azize does not explicitly disclose a thermal conductive transferred-substrate, wherein the thermal conductive transferred-substrate that is a semiconductor wafer embedded with a plurality of via-holes filled with a thermal conductive material.
However, Kojima discloses semiconductor device 5 further including a thermal conductive transferred-substrate (Kojima, substrate 110 is a thermal conductive substrate as it is patterned and may include a plurality of through holes extending from the front surface to the back surface, [0042], Figs. 4A and 4C; Azize, Figs. 1A and 10), wherein the thermal conductive transferred-substrate that is a semiconductor wafer embedded with a plurality of via-holes filled with a thermal conductive material (Kojima, 110 is filled with thermal conductive material as metal layer 30 further includes contact layer 33, barrier metal layer 37, and metal bonding layer 35, [0039], Figs. 4A and 4C; Azize, Figs. 1A and 10). The combination to utilize a thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of enhancing the thermal dissipation as well as to mitigate strain of the semiconductor interface (Kojima, [0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of enhancing the thermal dissipation as well as to mitigate strain of the semiconductor interface.
Azize does not explicitly disclose a metallic interlayer disposed on the thermal conductive transferred-substrate and is configured to adhere the thermal conductive transferred-substrate.
However, Kojima discloses a metallic interlayer disposed on the thermal conductive transferred-substrate (Kojima, metal bonding layer 35 is a metallic interlayer and is disposed on the thermal conductive transferred substrate 110, [0039], Figs. 4A and 4C; Azize, Figs. 1A and 10) and is configured to adhere the thermal conductive transferred-substrate (Kojima, 35 is configured to adhere 110; Figs. 4A and 4C; Azize, Figs. 1A and 10). The combination to utilize a metallic interlayer disposed on the thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of isolating contamination of the conductive material into the above lying semiconductor layers, as well as to mitigate strain of the semiconductor interface (Kojima, [0039]-[0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a metallic interlayer disposed on the thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of isolating contamination of the conductive material into the above lying semiconductor layers, as well as to mitigate strain of the semiconductor interface.
Azize does not explicitly disclose a cap layer disposed on the metallic interlayer.
However, Kojima discloses a cap layer disposed on the metallic interlayer (Kojima, barrier metal layer 37 is a cap layer disposed on metallic interlayer 35, [0039], Figs. 4A and 4C; Azize, Figs. 1A and 10). The combination to utilize a metallic interlayer disposed on the thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of isolating contamination of the conductive material into the above lying semiconductor layers, as well as to mitigate strain of the semiconductor interface (Kojima, [0039]-[0042]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a metallic interlayer disposed on the thermal conductive material embedded as a plurality of via-holes within the substrate for the purpose of isolating contamination of the conductive material into the above lying semiconductor layers, as well as to mitigate strain of the semiconductor interface.
Azize/Kojima does not explicitly disclose wherein one of the via-holes is aligned with the gate of the field-effect transistor.
However, Imamura (WO 2022176051 A1, referencing US 2024/0096968 A1 as a convenient translation) discloses wherein one of the via-holes (Imamura, via hole 16, Fig. 13; Azize, Figs. 1A and 10; Kojima, metal layer 30 further includes contact layer 33, barrier metal layer 37, and metal bonding layer 35, [0039], Figs. 4A and 4C) is aligned with the gate of the field-effect transistor (Imamura, via hole 16 is aligned with the gate electrode 14, [0032], Fig. 13; Azize, Figs. 1A and 10; Kojima, metal layer 30 further includes contact layer 33, barrier metal layer 37, and metal bonding layer 35, [0039], Figs. 4A and 4C). The combination would allow for the utilization of a thermally conductive via aligned with the gate electrode to serve as an improvement of high frequency characteristics in the resultant HEMT device (Imamura, [0005]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to utilize a thermally conductive via aligned with the gate electrode to serve as an improvement of high frequency characteristics in the resultant HEMT device (Imamura, [0005]).
Claim 12, Azize/Kojima discloses the semiconductor device (Azize, Figs. 1A and 10; Kojima, Figs. 4A and 4C) of claim 11.
Azize/Kojima discloses wherein the metallic material filling in the embedded via-holes (Kojima, concave portions 13 may further include a plurality of through holes extending from the front surface to the back surface, [0042], Figs. 4A and 4C; Azize, Figs. 1A and 10) of thermal conductive native-substrate (Kojima, substrate 110, Figs. 4A and 4C; Azize, Figs. 1A and 10) is AuTi alloy, AuSn alloy or AuNi alloy (Kojima, metal bonding layer 35 includes gold-tin (AuSn) alloy), [0028], contact layer 33 includes a metal film having a multilayered structure in which thin films of titanium (Ti), nickel (Ni), and gold (Au) are stacked and then heat treated wherein the stacked layers further undergo a solid-state diffusion process yielding the resulting gold alloys, [0027], Figs. 4A and 4C; Azize, Figs. 1A and 10).
Claim 13, Azize/Kojima discloses the semiconductor device (Azize, Figs. 1A and 10; Kojima, Figs. 4A and 4C) of claim 11.
Azize/Kojima discloses wherein the semiconductor wafer of the native-substrate is SiC, Si, GaAs, GaP, or GaN (Kojima, substrate 110/10 is a silicon substrate (Si), [0028], Figs. 4A and 4C; Azize, substrate 602/2 may be formed of SiC or Si, as well as a compound semiconductor material such as GaN which is a III-N material (e.g. GaAs and GaP are III-V compound semiconductor materials), [0047], Figs. 1A and 10).
Claim 14, Azize/Kojima discloses the semiconductor device (Azize, Figs. 1A and 10; Kojima, Figs. 4A and 4C) of claim 11.
Azize/Kojima discloses wherein the metallic interlayer (Kojima, metal bonding layer 35 is a metallic interlayer, [0039], Figs. 4A and 4C; Azize, Figs. 1A and 10) is AuTi alloy, AuSn alloy, or AuNi alloy (Kojima, metal bonding layer 35 includes gold-tin (AuSn) alloy), [0028], further, contact layer 33 includes a metal film having a multilayered structure in which thin films of titanium (Ti), nickel (Ni), and gold (Au) are stacked and then heat treated wherein the stacked layers further undergo a solid-state diffusion process yielding the resulting gold alloys, [0027], Figs. 4A and 4C; Azize, Figs. 1A and 10).
Claim 15, Azize/Kojima discloses the semiconductor device (Azize, Figs. 1A and 10; Kojima, Figs. 4A and 4C) of claim 11.
Azize discloses wherein xInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C).
Claim 16, Azize/Kojima discloses the semiconductor device (Azize, Figs. 1A and 10; Kojima, Figs. 4A and 4C) of claim 15.
Azize discloses wherein xInyGazN vary with respect to the nth or n-1th sublayer in sequence, [0083-0085], Figs. 7, 10, and 19; Kojima, Figs. 4A and 4C).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812