DETAILED ACTION
This office action is in response to the amendment filed 1/16/2026.
Currently, claims 1-4, 7 and 9-10 are pending.
Information Disclosure Statement
The documents cited in the IDSs are being considered, with the exception of the Taiwanese office action, which is written entirely in a non-English language.
Claim Objections
Claim 7 is objected to because “first” is misspelled as “frits” at the end of line 14. Furthermore, the word “on” appears to be erroneous in line 21 (“an upper surface of on the second dielectric layer”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 7 and 9-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Both independent claims 1 and 7 recite “wherein an upper surface of the first barrier material layer is higher than an upper surface of the first dielectric layer”. The disclosure lacks any description of how this could be accomplished, and thus one of ordinary skill in the art would not be enabled to perform the method as claimed.
The specification only states that the upper surface of the first barrier material layer being higher than an upper surface of the first dielectric layer is a result of a removal process described in para. [0014], with CMP being exemplary. However, CMP is a non-selective process in which a surface, which may be made up of different materials, is planarized such that the top surfaces of all materials are along a same plane (with the exception of dishing effects). An example of such a CMP process is Chen et al. (US 9,960,142, cited in IDS). See, for example, FIG. 4-5, which shows the result of CMP being a dielectric layer 110, a barrier layer 116, and a metal fill layer 118 having top surfaces sharing a same plane.
However, the disclosure appears to show the planarization process not only being selective, but selective to different regions of a same material. See FIG. 3-4, which shows the upper horizontal portions of the initial barrier material layer 104, which initially share a same plane, being removed in one region to expose the dielectric layer 103, yet remains in a different area such that it is higher than the dielectric layer. Based on known techniques, this would not be expected. The disclosure offers no explanation as to how this is accomplished. Thus, such a feature is not enabled by the disclosure.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 9-10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation “an upper surface of the second dielectric layer” in lines 25-26. However, this same limitation is also recited in line 21. Without referencing the already recited “upper surface of the second dielectric layer” from line 21, it is not clear whether the limitation recited in lines 25-26 is the same limitation from line 21.
Response to Arguments
Applicant's arguments filed 1/16/2026 regarding rejections under 35 U.S.C. 112(b) have been fully considered but they are not persuasive.
Applicant states that independent claims 1 and 7 have been amended to further detail the method that arrives at a structure where “an upper surface of the [first/second] barrier material layer is higher than the upper surface of the [first/second] dielectric layer”, citing para. [0014] – [0015] and FIGs. 3-4 for support.
The Examiner agrees that para. [0014] and FIGs. 3-4 are relevant to the steps that result in “an upper surface of the [first/second] barrier material layer is higher than the upper surface of the [first/second] dielectric layer”, but disagrees that para. [0015] is relevant. To be clear, the layer of barrier material is described differently depending on the step in the process. In FIG. 3, layer 104 is described as a [first/second] initial barrier material layer (emphasis added). FIG. 4 shows the result of an etching step that partially removes the [first/second] initial barrier material layer to form the [first/second] barrier material layer (emphasis added). Portions of the barrier material layer 404 from FIG. 4 are removed, resulting in the formation of the [first/second] barrier layer 504 shown in FIG. 5. This step from FIG. 5 has no connection to the limitation “an upper surface of the [first/second] barrier material layer is higher than the upper surface of the [first/second] dielectric layer, which is instead shown in FIG. 4. Rather, the step from FIG. 5 is claimed as “performing a chemical-mechanical planarization (CMP) process for removing part of the [first/second] barrier material layer to form a [first/second] barrier layer in the hole; wherein the upper surface of the barrier layer is coplanar with the upper surface of the dielectric layer and is higher than an upper surface of the via element”. This is the step that is described in para. [0015].
Returning to Applicant’s arguments, Applicant argues that “part of the initial barrier material layer 104 and part of the conductive layer 105 on the upper surface 103U of the dielectric layer 103 can be removed by at least one etching process with a selectivity to remove different materials along a same plane and to result in the features of ‘an upper surface of the [first/second] barrier material layer is higher than the upper surface of the [first/second] dielectric layer’”.
In response, the Examiner acknowledges that the difference in materials between the initial barrier material layer and the conductive layer may lead to different etching rates for each material. However, the result of such an etching process would be that the barrier material layer formed from the initial barrier material layer is higher than an upper surface of the via element formed from the conductive layer. Indeed, this is shown in FIG. 4. However, the limitation in question is not reciting the relative difference in heights between the barrier material layer and the via element, but rather the relative difference in heights between the barrier material layer and the dielectric layer.
Applicant then goes into detail about an etching process that may result in the barrier material layer being higher than the upper surface of the dielectric layer. The first step of this etching process is the removal of the conductive layer until it is coplanar with the initial dielectric material, which Applicant illustrates in the arguments with FIG. 3’. The etching process is then continued, which Applicant alleges leads to the removal of the part of the initial barrier material layer formed on the (initial) surface of the dielectric layer along with further removal of the conductive layer within the hole. At this point, the barrier material layer is coplanar with the dielectric layer. Applicant then alleges that etching would not stop at this point in the process but would rather continue to remove a portion of the dielectric layer at a faster rate than the barrier material layer, leading to the barrier material layer being higher than the dielectric layer.
In response, this is a detailed process that is not described in the originally filed disclosure (rather, this process closely resembles the steps shown in FIG. 15-18 of the previously cited Kim reference US 2024/0055406). While Applicant alleges that one of ordinary skill in the art would find this process to obvious, there is no evidence provided to support this claim. The Examiner disagrees with the allegation that such a process would be obvious to one of ordinary skill in the art, let alone that this process was known at the time the invention was filed. For example, the process described in the arguments would require particular materials and a particular etchant that etches the conductive layer at a greater rate than both the initial barrier material layer and the dielectric layer, and also etches the dielectric layer at a greater rate than the initial barrier material. It would also require a particular etch time.
Moreover, the process described in Applicant’s arguments appears to be at odds with what is originally disclosed. The barrier material layer being higher than the upper surface of the dielectric layer is shown in FIG. 4. Para. [0014] states that “part of the initial barrier material layer 104 and part of the conductive layer 105 are removed to form a barrier material layer 404 and via elements 405. The upper surface 103U of the dielectric layer 103 is exposed.” This explicitly cites the removal of the initial barrier material layer and the conductive layer, but makes no mention of removal of the dielectric layer. On the contrary, the disclosure states that the “upper surface 103U of the dielectric layer 103 is exposed”. The upper surface 103U of the dielectric layer 103 is also described as the surface on which the initial barrier material layer is formed (“an initial barrier material layer 104 and a conductive layer 105 are formed on an upper surface 103U of the dielectric layer 103”, para. [0013]). Taken together, this implies that the surface of the dielectric layer on which the initial barrier material layer is formed is the same surface that is exposed at the point in the process shown in FIG. 4. In fact, the independent claims recite the limitation “upper surface of the [first/second] dielectric layer” that is described as being
a) the surface on which the initial barrier material layer and conductive layer are formed (e.g. claim 1, lines 4-5),
b) the surface that is exposed as a result of the etching process that forms the barrier material layer and the via element by removal of portions of the initial barrier material layer and the conductive layer, respectively (e.g. claim 1, lines 6-8), and
c) the surface that is lower than an upper surface of the formed barrier material layer (e.g. claim 1, lines 9-10).
Thus, the barrier material layer being higher than the upper surface of the dielectric layer apparently would not rely on the further etching of the dielectric layer that leads to an upper surface of the dielectric layer that is lower than the initial upper surface of the dielectric material. Thus, the process described by Applicant in the arguments, even if such a process were obvious to one of ordinary skill in the art, could not be used to arrive at the structure shown in FIG. 4, which the disclosure suggests is achieved without (or at least prior to) any removal of the dielectric layer.
With regards to the previous prior art rejections under 35 U.S.C. 102 and 103, Applicant’s arguments are persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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