DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 22, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 28 and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,074,864 B1 to Lu et al. (hereinafter “Lu” – previously cited reference).
Regarding claim 1, Lu discloses a display device comprising:
a display panel including:
a display area;
a non-display area (display panel 10 having display and non-display areas; Fig. 1; column 6, lines 21-34);
a pixel disposed in the display area and including a light emitting element and a pixel driving circuit electrically connected to the light emitting element (pixel array 12 having individual pixels 14 each having pixel circuit drive transistors coupled to one of a plurality of light emitting elements of OLED; Fig. 1; column 6, lines 21-61);
a data line electrically connected to the pixel and extending in a first direction (data input line electrically connected to pixel 14 and extending in first column direction; Fig. 1; column 6, lines 35-48);
a plurality of scan lines electrically connected to the pixel and extending in a second direction intersecting the first direction (plurality of scan control lines SCAN(n) electrically connected to pixel 14 and extending in second row direction intersection first column direction of data input line; Fig. 1; column 6, lines 35-48);
an emission control line electrically connected to the pixel and extending in the second direction (emission control signal line GEMI electrically connected to pixel 14 and extending in second row direction; Fig. 1; column 6, lines 49-61); and
an initialization voltage line electrically connected to the pixel, extending in the second direction, and to which an initialization voltage is applied (initialization control signal line GINT of panel driver 16 electrically connected to pixel 14 for applying initialization voltage and extending in second row direction; Fig. 1; column 6, lines 49-61),
wherein, in a third direction orthogonal to each of the first direction and the second direction, the initialization voltage line: (i) is disposed between, and overlaps one of the plurality of scan lines and another of the plurality of scan lines in a parallel manner along the second direction; or (ii) is disposed between, and overlaps the emission control line and a scan line among the plurality of scan lines in a parallel manner along the second direction (GINT is disposed between and overlaps SCAN(2) and one or more of SCAN(n) in direction parallel to row direction without forming a connection, which places GINT at a different depth level than SCAN(2) and SCAN(n), where the depth direction is orthogonal to the row and column directions; Fig. 1).
Regarding claim 28, Lu discloses a display device comprising:
a display panel including:
a display area;
a non-display area (display panel 10 having display and non-display areas; Fig. 1; column 6, lines 21-34);
a pixel disposed in the display area and including a light emitting element and a pixel driving circuit electrically connected to the light emitting element and including a plurality of transistors (pixel array 12 having individual pixels 14 each having pixel circuit drive transistors coupled to one of a plurality of light emitting elements of OLED; Fig. 1; column 6, lines 21-61);
a data line electrically connected to the pixel and extending in a first direction (data input line electrically connected to pixel 14 and extending in first column direction; Fig. 1; column 6, lines 35-48);
plurality of scan lines electrically connected to the pixel and extending in a second direction intersecting the first direction (plurality of scan control lines SCAN(n) electrically connected to pixel 14 and extending in second row direction intersection first column direction of data input line; Fig. 1; column 6, lines 35-48);
an emission control line electrically connected to the pixel (emission control signal line GEMI electrically connected to pixel 14; Fig. 1; column 6, lines 49-61); and
a constant voltage line to which a constant voltage is provided and overlapping the pixel driving circuit in a plan view (initialization control signal line GINT of panel driver 16 electrically connected to pixel 14 and overlapping pixel circuit 20 therein in plan view; Figs. 1 and 3; column 6, lines 49-61; column 8, line 62 to column 9, line 62),
wherein, in a third direction orthogonal to each of the first direction and the second direction, two lines among the plurality of scan lines and the emission control line overlap with the constant voltage line in a parallel manner along the second direction (SCAN(2), SCAN(n), and GEMI, which extend in row direction parallel to one another, overlap GINT in a depth direction orthogonal to the first column direction and the second row direction as shown in Fig. 1).
Regarding claim 30, Lu discloses the display device of claim 28, wherein the constant voltage line is disposed between one of the plurality of scan lines and the emission control line and another of the plurality of scan lines and the emission control line (GINT disposed between one of SCAN(n) and GEMI and between another of SCAN(n) and GEMI as shown in Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (in a different interpretation).
Regarding claim 1, Lu discloses a display device comprising:
a display panel including:
a display area;
a non-display area (display panel 10 having display and non-display areas; Fig. 1; column 6, lines 21-34);
a pixel disposed in the display area and including a light emitting element and a pixel driving circuit electrically connected to the light emitting element (pixel array 12 having individual pixels 14 each having pixel circuit drive transistors coupled to one of a plurality of light emitting elements of OLED; Fig. 1; column 6, lines 21-61);
a data line electrically connected to the pixel and extending in a first direction (data input line electrically connected to pixel 14 and extending in first column direction; Fig. 1; column 6, lines 35-48);
a plurality of scan lines electrically connected to the pixel and extending in a second direction intersecting the first direction (plurality of scan control lines SCAN(n) electrically connected to pixel 14 and extending in second row direction intersection first column direction of data input line; Fig. 1; column 6, lines 35-48);
an emission control line electrically connected to the pixel and extending in the second direction (emission control signal line GEMI electrically connected to pixel 14 and extending in second row direction; Fig. 1; column 6, lines 49-61); and
an initialization voltage line electrically connected to the pixel, extending in the second direction, and to which an initialization voltage is applied (initialization control signal line GINT of panel driver 16 electrically connected to pixel 14 for applying initialization voltage and extending in second row direction; Fig. 1; column 6, lines 49-61),
wherein, in a third direction orthogonal to each of the first direction and the second direction, the initialization voltage line: (i) overlaps one of the plurality of scan lines and another of the plurality of scan lines in a parallel manner along the second direction; or (ii) is disposed between, and overlaps the emission control line and a scan line among the plurality of scan lines in a parallel manner along the second direction (GINT is disposed between and overlaps SCAN(2) and one or more of SCAN(n) in direction parallel to row direction without forming a connection, which places GINT at a different depth level than SCAN(2) and SCAN(n), where the depth direction is orthogonal to the row and column directions; Fig. 1).
Lu fails to explicitly disclose the initialization voltage line being disposed between one of the plurality of scan lines and another of the plurality of scan lines in the third direction.
However, Lu suggests the initialization voltage line being disposed between one of the plurality of scan lines and another of the plurality of scan lines in that GINT being at a different depth level than SCAN(2) and SCAN(n) which means GINT being disposed between SCAN(2) and SCAN(n) is one distinct placement for GINT relative SCAN(2) and SCAN(n) of three possible placements (i.e. above, below, or between SCAN(2) and SCAN(n) in the depth direction).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lu in this manner in order to potentially provide more uniform distribution of the initialization voltage line across the display panel, row-by-row sequential initialization of scan signals, and advanced compensation schemes with minimal additional lines.
Claim 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in further view of US 2020/0265778 A1 to Lee et al. (hereinafter “Lee” – previously cited reference).
Regarding claim 2, Lu discloses the display device of claim 1. Lu fails to disclose wherein the plurality of scan lines include: an initialization scan line; a compensation scan line; and a write scan line, and at least one of the initialization scan line, the compensation scan line, and the write scan line and at least another of the initialization scan line, the compensation scan line, and the write scan line are disposed on different layers.
However, Lee discloses wherein the plurality of scan lines include: an initialization scan line; a compensation scan line; and a write scan line, and at least one of the initialization scan line, the compensation scan line, and the write scan line and at least another of the initialization scan line, the compensation scan line, and the write scan line are disposed on different layers (initialization scan signal GI(j) line, compensation scan signal GC(j) line, and write scan signal GW(j) line disposed on different cross-sectional layers; Fig. 2; paragraph [0084]).
Lu and Lee are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lu to incorporate the teaching of Lee in order to potentially provide enhanced depth perception, improved resolution and detail, and reduced motion artifacts.
Regarding claim 16, Lu in view of Lee discloses the display device of claim 2. Lu further discloses wherein: the initialization voltage line is a first initialization voltage line and the initialization voltage is a first initialization voltage, the display panel further includes a second initialization voltage line electrically connected to the pixel, extending in the second direction, and to which a second initialization voltage different from the first initialization voltage is applied (initialization control signal line GINT of panel driver 18 electrically connected to pixel 14 for applying initialization voltage that may be different from initialization voltage of panel driver 16 and extending in second row direction; Fig. 1; column 6, lines 49-61), and the second initialization voltage line overlaps at least one of the plurality of scan lines and the emission control line in a plan view (initialization control signal line GINT of panel driver 18 overlaps one of SCAN(n) and GEMI in plan view as shown in Fig. 1).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Lu in further view of US 2021/0142734 A1 to Cho et al. (hereinafter “Cho” – IDS cited reference).
Regarding claim 29, Lu discloses the display device of claim 28. Lu further discloses wherein at least one of the plurality of transistors includes a layer of an oxide of a semiconducting material, others of the plurality of transistors include a silicon semiconductor layer, the silicon semiconductor layer and the layer of an oxide of a semiconducting material being disposed on different layers, and in a plan view, a portion of the layer of an oxide of a semiconducting material and a portion of the silicon semiconductor layer overlap each other (each of the pixel circuits 20 includes a driving transistor having a gate oxide and a semiconductor layer such that the oxide layer and semiconductor layer are disposed vertically upon one another; Figs. 1 and 3; column 9, lines 38-62; column 13, lines 37-58).
Lu fails to disclose wherein at least one of the plurality of transistors includes a semiconducting oxide layer.
However, Cho discloses wherein at least one of the plurality of transistors includes an oxide semiconductor layer, others of the plurality of transistors include a silicon semiconductor layer, the silicon semiconductor layer and the oxide semiconductor layer being disposed on different layers, and in a plan view, a portion of the oxide semiconductor layer and a portion of the silicon semiconductor layer overlap (transistor T3 includes a semiconductor layer which may be an oxide semiconductor and transistor T1 includes a semiconductor layer which may be amorphous silicon, where T1 is stacked above T3 in plan view; Figs. 4-5; paragraphs [0083]-[0085]).
Lu and Cho are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lu to incorporate the teaching of Cho in order to potentially provide high mobility with ultra-low leakage, variable refresh rate and power savings, and improved pixel compactness and higher aperture ratio/resolution.
Allowable Subject Matter
Claim 18 is allowable in combination as claimed as described in the Non-Final rejection on August 14, 2025.
Claims 3-15 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Further, Lu, Lee, and Cho each disclose portions of claims 3, 17, and 18 but fail to teach, disclose, or suggest these claims as a whole, in combination.
Response to Arguments
Applicant's arguments filed March 25, 2026 have been fully considered. Applicant presents amendments to claims 1 and 28 and associated arguments. Applicant’s lone assertion is that Lu does not explicitly disclose a plurality of lines extending in the same plane and overlapping one another in a vertical direction as shown in Applicant’s Figs. 10A, 10B, 16C. Examiner agrees with this statement. However, this is not what is recited in amended claims 1 and 28. Rather, what is recited in amended claim 1 is “wherein, in a third direction orthogonal to each of the first direction and the second direction, the initialization voltage line: (i) is disposed between, and overlaps one of the plurality of scan lines and another of the plurality of scan lines in a parallel manner along the second direction” which has a broadest reasonable interpretation (BRI) that includes the initialization voltage line being disposed between and overlapping the scan lines in the third direction while extending parallel one another in the second direction, which is disclosed by Fig. 1 of Lu. Similarly, claim 28 recites “wherein, in a third direction orthogonal to each of the first direction and the second direction, two lines among the plurality of scan lines and the emission control line overlap with the constant voltage line in a parallel manner along the second direction” which has a BRI that includes two scan lines and the emission control line overlapping the constant voltage line in the third direction while extending parallel one another in the second direction, which is disclosed by Fig. 1 of Lu. Examiner suggests altering the amendments to recite the plurality of lines extending in the same plane (i.e. defined by the second and third directions) and overlapping one another in the third direction. However, this does not address the single-reference obviousness rejection and its associated motivation statement which Applicant says is rebutted by Applicant’s Specification, but this is a conclusory statement and does not provide any substance with assertion to which Examiner can respond.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF NATALINI can be reached on (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights