Prosecution Insights
Last updated: April 19, 2026
Application No. 17/964,249

SEMICONDUCTOR DEVICE STRUCTURE WITH PATTERNS HAVING COPLANAR BOTTOM SURFACES AND METHOD FOR PREPARING THE SAME

Final Rejection §103§112
Filed
Oct 12, 2022
Examiner
SMITH, SAMUEL JONATHAN
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nanya Technology Corporation
OA Round
4 (Final)
83%
Grant Probability
Favorable
5-6
OA Rounds
3y 5m
To Grant
84%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
29 granted / 35 resolved
+14.9% vs TC avg
Minimal +1% lift
Without
With
+0.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
17 currently pending
Career history
52
Total Applications
across all art units

Statute-Specific Performance

§103
59.9%
+19.9% vs TC avg
§102
28.9%
-11.1% vs TC avg
§112
10.5%
-29.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 35 resolved cases

Office Action

§103 §112
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 8 and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Specifically, the newly amended claims include the limitation that hard mask patterns are carbon hard mask patterns. Furthermore, claim 1 has specifically been amended to remove the limitation that the hard mask patterns merely include carbon. Meanwhile, the specification states that the hard mask patterns merely include carbon (see paragraphs 6, 7, 9, 31 and 103). In other words, Examiner understands the language “carbon hard mask pattern” to mean that the hard mask patterns are made of only carbon, but this is not supported by the specification. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4, 8-10, 13, and 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abatchev (US 20060046200 A1) in view of Dai (US 20210294216 A1). PNG media_image1.png 275 635 media_image1.png Greyscale Regarding claim 1, Abatchev discloses a semiconductor device structure (Fig. 14, integrated circuit 100), comprising: a first hard mask pattern (150, see attached figure) disposed over a planar metal layer (substrate 110; para. 54 "the substrate can comprise... a metal layer"); a second hard mask pattern disposed over the planar metal layer and on a first side (right side) of the first hard mask pattern, and spaced apart from the first hard mask pattern, a third mask pattern disposed over the planar metal layer, wherein the second hard mask pattern is disposed between the first hard mask pattern and the third hard mask pattern, and the third hard mask pattern is spaced apart from the second hard mask pattern; and a fourth hard mask pattern disposed over the metal layer and on a second side (left side) of the first hard mask pattern, and spaced apart from the first hard mask pattern, wherein the first side of the first hard mask pattern is opposite to the second side of the first hard mask pattern, wherein a bottom surface of the first hard mask pattern, a bottom surface of the second hard mask pattern, a bottom surface of the third hard mask pattern, and a bottom surface of the fourth mask pattern are coplanar, wherein a first opening between the second hard mask pattern and the third hard mask pattern is physically connected with a second opening between the first hard mask pattern and the fourth hard mask pattern (see attached figure; all openings are connected by the rest of the open space above and between hard mask patterns), and wherein the first hard mask pattern, the second hard mask pattern, and the third hard mask pattern are in direct contact with the planar metal layer (see attached figure). However, Abatchev does not explicitly disclose wherein the first hard mask layer pattern, the second hard mask layer pattern, and the third hard mask pattern include carbon. On the other hand, Dai discloses a hard mask layer including carbon (Para. 49 "The hardmask layer may be an antireflective coating layer (ARC) layer fabricated from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide"). It would have been obvious to one of ordinary skill before the time of effective filing of the invention to modify Abatchev according to the teachings of Dai such that Abatchev’s silicon oxide hard masks (Para. 61 “hard mask layer 150 preferably comprises… silicon or aluminum oxide”) would instead be formed of silicon carbide and the first, second and third hard mask patterns would include carbon. It would be obvious to interchange these materials because of silicon carbide’s higher mechanical and thermal stability allowing for thinner mask layers which would result in lower material costs and higher pattern transfer fidelity. Regarding claim 2, Abatchev discloses wherein the bottom surface of the first hard mask pattern and the bottom surface of the second hard mask pattern are in direct contact with a top surface of the planar metal layer (Fig. 14 shows bottom surfaces of all hard masks 150 in direct contact with top surface of metal layer 110). Regarding claim 3, Abatchev discloses wherein the planar metal layer is exposed by a third opening between the first hard mask pattern and the second hard mask pattern (see attached figure). PNG media_image2.png 275 635 media_image2.png Greyscale Regarding claim 4, Abatchev discloses wherein a material of the first hard mask pattern is the same as a material of the second hard mask pattern (Figs. 12-14 show that all hard masks 150 are made from a single initial layer, and therefore are made of the same material). PNG media_image3.png 300 596 media_image3.png Greyscale Regarding claim 8, Abatchev discloses a method for preparing a semiconductor device structure, comprising: providing a substrate (Fig. 2), wherein the substrate comprises a planar metal layer (substrate 110; para. 54 "the substrate can comprise... a metal layer"), a hard mask layer over the planar metal layer (layer 150), and an anti-reflective coating layer over the hard mask layer (combination of 130 and 140; para. 58 "The material for the first hard mask layer 130 preferably comprises... a dielectric anti-reflective coating"), and the anti-reflective coating layer in direct contact with the planar metal layer (See first attached figure); etching the anti-reflective coating layer to form an anti-reflective coating pattern (Fig. 6); forming a first spacer (see first attached figure), PNG media_image4.png 283 568 media_image4.png Greyscale a second spacer, a third spacer, and a fourth spacer, wherein the first spacer and the second spacer are on opposite sidewalls of the anti-reflective coating pattern, wherein the second spacer is disposed between the first spacer and the third spacer, and the first spacer is disposed between the second spacer and the fourth spacer, wherein a bottom surface of the first spacer, a bottom surface of the second spacer, a bottom surface of the third spacer, a bottom surface of the fourth spacer, and a bottom surface of the anti-reflective coating pattern are coplanar (see first attached figure); forming an assistant feature (155) adjoining the first spacer, the second spacer, the third spacer, and the fourth PNG media_image1.png 275 635 media_image1.png Greyscale spacer and over the hard mask layer (Fig. 9 shows 155 adjoining first, second, third and fourth spacer and being positioned over the hard mask); removing the anti-reflective coating pattern and the assistant feature (Fig. 11) to form a first opening between the second spacer and the third spacer and a second opening between the first spacer and the fourth spacer, wherein the first opening and the second opening are physically connected (see second attached figure); and etching the hard mask layer by using the first spacer, the second spacer, the third spacer, and the fourth spacer as a mask (See fig. 13) to form a first hard mask pattern, a second hard mask pattern, a third hard mask pattern, and a fourth hard mask pattern (see third attached figure) in direct contact with the planar metal layer (attached figures show masks being on planar metal layer 110). However, Abatchev does not disclose wherein the hard mask layer includes carbon. On the other hand, Dai discloses a hard mask layer including carbon (Para. 49 "The hardmask layer may be an antireflective coating layer (ARC) layer fabricated from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide"). It would have been obvious to one of ordinary skill before the time of effective filing of the invention to modify Abatchev according to the teachings of Dai such that Abatchev’s silicon oxide hard masks (Para. 61 “hard mask layer 150 preferably comprises… silicon or aluminum oxide”) would instead be formed of silicon carbide and the first, second and third hard mask patterns would include carbon. It would be obvious to interchange these materials because of silicon carbide’s higher mechanical and thermal stability allowing for thinner mask layers which would result in lower material costs and higher pattern transfer fidelity. PNG media_image2.png 275 635 media_image2.png Greyscale Regarding claim 9, Abatchev discloses wherein a top surface of the planar metal layer is exposed by a third opening between the first hard mask pattern and the second hard mask pattern after the hard mask layer is etched (see attached figure). Regarding claim 10, Abatchev discloses wherein a bottom surface of the first hard mask pattern and a bottom surface of the second hard mask pattern are coplanar with the top surface of the planar metal layer (Fig. 14 shows bottom surfaces of all hard masks 150 in direct contact with top surface of metal layer 110). Regarding claim 13, Abatchev discloses wherein the anti-reflective coating pattern is separated from the assistant feature by the first spacer, the second spacer, the third spacer, and the fourth spacer (Fig. 9, anti-reflective coating 130/140 is separated from assistant feature 155 by first, second, third and fourth spacers). Regarding claim 15, Abatchev discloses further comprising: depositing a spacer layer (Fig. 7, 170) covering a top surface of the hard mask layer, and a top surface and the opposite sidewalls of the anti-reflective coating pattern (Fig. 7 shows 175 covering top surface of hard mask 150, top surface of an anti-reflective coating pattern 130, and sidewalls of anti-reflective coating pattern 130); and partially removing the spacer layer such that the first spacer and the second spacer are formed on the opposite sidewalls of the anti-reflective coating pattern (Fig. 8, spacer 170 has partially been removed such that first and second spacer portions are formed on opposite sidewalls of anti-reflective coating pattern 130). PNG media_image5.png 320 445 media_image5.png Greyscale Regarding claim 16, Abatchev discloses a method for preparing a semiconductor device structure, comprising: providing a substrate (Fig. 2), wherein the substrate comprises a planar metal layer (substrate 110; para. 54 "the substrate can comprise... a metal layer"), an anti-reflective coating layer (combination of 130 and 140; para. 58 "The material for the first hard mask layer 130 preferably comprises... a dielectric anti-reflective coating"), and a hard mask layer sandwiched between the planar metal layer and the anti-reflective coating layer (150) in direct contact with the planar metal layer; etching the anti-reflective coating layer to form a first anti-reflective coating pattern and a second anti-reflective coating pattern (Fig. 6); forming a first spacer and a second spacer on opposite sidewalls of the first anti-reflective coating pattern, wherein a bottom surface of the first spacer, a bottom surface of the second spacer, and a bottom surface of the first anti-reflective coating pattern are coplanar; forming a third spacer and a fourth spacer on opposite sidewalls of the second anti-reflective coating pattern (see attached figure); forming an assistant feature (155) adjoining the first spacer, the second spacer, the third spacer, and the fourth spacer (Fig. 9 shows 155 adjoining first, second, third and fourth spacer); removing the first anti-reflective coating pattern, the second anti-reflective coating pattern, and the PNG media_image6.png 282 409 media_image6.png Greyscale assistant feature (Fig. 11) to form a first opening adjoining the first spacer, a second opening between the second spacer and the third spacer, and the fourth spacer as a mask, such that a first hard mask pattern, a second hard mask pattern, a third hard mask pattern, and a fourth hard mask pattern in direct contact with the planar metal layer are formed (process shown in Figs. 13-14; see attached figure). However, Abatchev does not disclose wherein the hard mask layer includes carbon. On the other hand, Dai discloses a hard mask layer including carbon (Para. 49 "The hardmask layer may be an antireflective coating layer (ARC) layer fabricated from a group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide"). It would have been obvious to one of ordinary skill before the time of effective filing of the invention to modify Abatchev according to the teachings of Dai such that Abatchev’s silicon oxide hard masks (Para. 61 “hard mask layer 150 preferably comprises… silicon or aluminum oxide”) would instead be formed of silicon carbide and the first, second and third hard mask patterns would include carbon. It would be obvious to interchange these materials because of silicon carbide’s higher mechanical and thermal stability allowing for thinner mask layers which would PNG media_image1.png 275 635 media_image1.png Greyscale result in lower material costs and higher pattern transfer fidelity. Regarding claim 17, Abatchev discloses wherein bottom surfaces of the first hard mask pattern, the second hard mask pattern, the third hard mask pattern, and the fourth hard mask pattern are coplanar (Fig. 14 shows bottom surfaces of all hard masks 150 in direct contact with top surface of metal layer 110). Regarding claim 18, Abatchev discloses further comprising: removing the first spacer, the second spacer, the third spacer, and the fourth spacer after the hard mask layer is etched (Fig. 14). Regarding claim 19, Abatchev discloses wherein a top surface of the hard mask layer is exposed by a fourth opening between the first anti-reflective coating pattern and the second anti-reflective coating pattern (Fig. 6 shows top surface of hard mask 150 exposed by fourth opening indicated by rightmost instance of 122a) before the first spacer, the second spacer, the third spacer, and the fourth spacer are formed (Spacer 170 is not formed until Fig. 7). Regarding claim 20, Abatchev discloses wherein the second spacer and the third spacer are formed in the fourth opening, and a remaining portion of the fourth opening is filled by the assistant feature (Fig. 9 shows second and third spacers in rightmost instance of 122a and the remaining portion of 122a being filled with assistant feature 155). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abatchev (US 20060046200 A1) in view of Dai (US 20210294216 A1) as applied to claims 1-4, 8-10, 13 and 15-20 above, and further in view of Lu (US 20220293419 A1). Regarding claim 12, Abatchev discloses the method of preparing a semiconductor device of claim 8. However, Abatchev does not explicitly disclose wherein the hard mask layer of the substrate is formed by a plasma enhanced chemical vapor deposition process. On the other hand, Lu discloses wherein the hard mask layer of the substrate is formed by a plasma enhanced chemical vapor deposition process (Para. 23 "The hard mask layer 220 may be formed using… plasma enhanced chemical vapor deposition"). It would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Abatchev according to the teachings of Lu such that the hard mask of the substrate would be formed by a plasma enhanced chemical vapor deposition process, in order to maintain low production costs and/or simplify manufacturing by using a common deposition technique in the art and form the hard mask at lower temperatures than if traditional chemical vapor deposition were used. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Abatchev (US 20060046200 A1) in view of Dai (US 20210294216 A1) as applied to claims 1-4, 8-10, 13 and 15-20 above, and further in view of Kim (US 20160203983 A1). Regarding claim 14, Abatchev discloses the method of preparing a semiconductor device structure of claim 8. However, Abatchev does not explicitly disclose wherein the anti-reflective coating pattern and the assistant feature comprise different materials. On the other hand, Kim discloses wherein the anti-reflective coating pattern and the assistant feature comprise different materials (Fig. 6; para. 35 "the upper mask layer 108 may be formed of silicon nitride or silicide oxynitride. In this case, the upper mask layer 108 may also serve as an anti-reflective layer"; para. 57 "the filling layer pattern 114 constitute an [amorphous carbon layer]"). It would have been obvious to one of ordinary skill in the art at the time of the effective filing of the invention to modify Abatchev according to the teachings of Kim such that the anti-reflective coating pattern and the assistant feature would comprise different materials, in order to allow the two materials to have different etching rates and for a controlled etch to be performed on them. Response to Arguments Applicant's arguments filed 12/1/2025 have been fully considered but they are not persuasive. Applicant argued that Dai does not teach the feature that a carbon hardmask layer or pattern is disposed on a metal layer, and therefore Abatchev and Dai fail to teach at least the features that the first carbon hard mask pattern, the second carbon hard mask pattern, and the third carbon hard mask pattern are in direct contact with the planar metal layer. Examiner disagrees with Applicant's argument. Applicant's arguments pertain to Dai independently of Abatchev, but Examiner's rejections for claims 1, 8 and 16 depends on the combination of Abatchev in view of Dai. The combination of Abatchev and Dai teaches all claim limitations of claims 1, 8 and 16 and there is a reasonable motivation to combine the teachings of Dai with the teachings of Abatchev. Furthermore, Applicant's amendment of claim 1 suggests that Applicant intends to distinguish over the silicon carbide hard mask layer of Dai by adding the claim language "carbon hard mask pattern". The instant application merely discloses hard mask patterns which include carbon; the specification does not support any claim limitations which would exclude the use of silicon carbide. See the above 112a rejection. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL J SMITH whose telephone number is (703)756-5706. The examiner can normally be reached M-F 8-5 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S.J.S./Examiner, Art Unit 2817 /MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Oct 12, 2022
Application Filed
Apr 18, 2025
Non-Final Rejection — §103, §112
Jul 09, 2025
Response Filed
Aug 11, 2025
Final Rejection — §103, §112
Sep 16, 2025
Request for Continued Examination
Oct 01, 2025
Response after Non-Final Action
Oct 06, 2025
Non-Final Rejection — §103, §112
Dec 01, 2025
Response Filed
Dec 14, 2025
Final Rejection — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
83%
Grant Probability
84%
With Interview (+0.7%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 35 resolved cases by this examiner. Grant probability derived from career allow rate.

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