DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Continued Examination Under 37 CFR 1.114
5. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2025 has been entered.
Response to Arguments
6. Applicant’s arguments, see Independent Claims are Patentable, filed 11/12/2025, with respect to the rejection of claim 28 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Green, Bruce McRae et al. (Pub No. US 20230207676 A1) (hereinafter, Green).
7. Applicant’s arguments, see Independent Claims are Patentable, filed 11/12/2025, with respect to the rejections of claims 1 and 48 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 28-29, 32, 36, 41 and 46 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Green, Bruce McRae et al. (Pub No. US 20230207676 A1) (hereinafter, Green).
Green, Fig 5D: Cross-section of fabrication step of HFET device
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Re Claim 28 (Currently Amended), Green teaches a semiconductor device, comprising:
a substrate (Substrate and buffer layer; 102/104; Fig 5D; ¶[0027]);
an epitaxial semiconductor island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) on the substrate comprising a first material characteristic (N-type dopants implanted into implant regions 530 to form source and drain regions 142/147; ¶[0056]);
wherein the epitaxial semiconductor island comprises a discrete epitaxial region (Source and drain regions, i.e. separate/discrete regions; 142/147; Fig 5D; ¶[0033]) that protrudes (Protruding above substrate and buffer layer 102/104; Fig 5D) above the substrate; and
an epitaxial semiconductor structure (Either one or a combination of Channel layer, Barrier layer, Cap layer; 106/108/109; Figs 4/5D; Per ¶¶[0054,0059] 106/108/109/130 are grown by metal-organo chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE)) comprising a second material characteristic (Channel layer may be GaN, AlGaN with Si, Ge, C, Fe, Cr; ¶[0029]; Barrier layer may be InAlN, AlGaN with Si, Ge, C, Fe, Cr; ¶[0030]; Cap layer is GaN; ¶[0031]) different from the first material characteristic and grown from the substrate and from the epitaxial semiconductor island,
wherein the epitaxial semiconductor island extends to, contacts, or forms a part of, an active region (Active region; 125; Fig 1; ¶[0025]) of the semiconductor device.
Green, Figs 7B: Coupling Ohmic Contacts to Epitaxial Islands
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Re Claim 29 (Currently Amended), Green teaches the semiconductor device of Claim 28, further comprising:
an ohmic contact (Source/drain electrodes; 140/145; Fig 7B; Per ¶[0062] 140/145 are alternatively referred to as Ohmic Contacts) on the epitaxial island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) wherein the ohmic contact is conductively coupled (Form ohmic contact to channel 107 through connection to source/drain regions 142/147; ¶[0033]) to the epitaxial semiconductor structure (Either one or a combination of Channel layer, Barrier layer, Cap layer; 106/108/109; Fig 6; Per ¶¶[0054,0059] 106/108/109/130 are grown by metal-organo chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE)).
Re Claim 32 (Previously Presented), Green teaches the semiconductor device of Claim 28, wherein the epitaxial semiconductor island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) is at least partially formed in a recess (Opening; 515; Fig 5B; ¶[0056]) in an upper surface (Upper surface of 104; Fig 5D) of the substrate (Substrate and buffer layer; 102/104; Fig 5D; ¶[0027]) and extends above the upper surface of the substrate.
Re Claim 36 (Original), Green teaches the semiconductor device of Claim 28, wherein the substrate (Substrate and buffer layer; 102/104; Fig 5D; ¶[0027]) comprises a trench (Recess embedded into buffer layer 104 of substrate 110; Fig 5B) therein, wherein the epitaxial semiconductor island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) is at least partially formed in the trench.
Re Claim 41 (Original), Green teaches the semiconductor device of Claim 28, wherein the epitaxial semiconductor island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) forms a part of an active region (Active region; 125; Fig 2; ¶[0025]) of the semiconductor device.
Re Claim 46 (Original), Green teaches a semiconductor wafer (Semiconductor substrate; 110; Fig 1; ¶[0031]) comprising the semiconductor (Components within semiconductor substrate 110; Fig 1) of Claim 28.
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claims 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Green, Bruce McRae et al. (Pub No. US 20230207676 A1) (hereinafter, Green) as applied to Claim 28 above, and further in view of Mita, Juro et al. (Pub No. US 20110189826 A1) (hereinafter, Mita).
Mita, Fig 2: Curvature of two-dimensional electron gas layer with semiconductor island
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Re Claim 30 (Currently Amended), Green teaches the semiconductor device of Claim 28, wherein the epitaxial semiconductor island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) extends above the substrate (Substrate and buffer layer; 102/104; Fig 5D; ¶[0027]).
However, Green does not teach wherein the epitaxial semiconductor structure has a curvature such that the epitaxial semiconductor structure extends up a sidewall of the epitaxial semiconductor island.
In the same field of endeavor, Mita teaches wherein the epitaxial semiconductor structure (Either one or a combination of Electron transit layer and Electron supply layer; 20/22; Fig 2; ¶[0111]) has a curvature (Per ¶[0123]) Contact region C between curved surface 68b and two-dimensional electron layer 36 of electron transit layer 20) such that the epitaxial semiconductor structure extends up a sidewall (Curved surface; 68b; Fig 2; ¶[0123]) of the epitaxial semiconductor island (Convex portion of Ohmic electrode 62; 68; Fig 2; ¶[0123]; Note: Convex portion comprises dielectric material which may be grown epitaxially).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an epitaxial structure extending up a sidewall of the semiconductor region as taught by Mita to combine it with the semiconductor region extending above the substrate. One would have been motivated to do this with a reasonable expectation of success such that the oblique contact between the epitaxial structure and semiconductor region may increase the surface area between the two-dimensional electron gas, reducing the contact resistance between the epitaxial structure and semiconductor region, as suggested by Mita (¶[0196]).
Re Claim 31 (Currently Amended), Green teaches the semiconductor device of Claim 30, wherein the epitaxial semiconductor island (Source and drain regions; 142/147; Fig 5D; ¶[0033]) comprises a first epitaxial semiconductor island (Source and drain region; 142; Fig 5D; ¶[0033]), the semiconductor device further comprising:
a second epitaxial semiconductor island (Source and drain region; 147; Fig 5D; ¶[0033]), on the substrate (Substrate and buffer layer; 102/104; Fig 5D; ¶[0027]) adjacent the epitaxial semiconductor structure (Either one or a combination of Channel layer, Barrier layer, Cap layer; 106/108/109; Fig 6; Per ¶¶[0059] 106/108/109 are grown by metal-organo chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE)), wherein the second epitaxial semiconductor island extends (Extends beyond buffer layer 104; Fig 5D) above the substrate.
However, Green does not teach wherein the epitaxial semiconductor structure has a curvature such that the epitaxial semiconductor structure extends up a sidewall of the second semiconductor region.
In the same field of endeavor, Mita teaches wherein the epitaxial semiconductor structure (Convex portion of Ohmic electrode 62; 68; Fig 2; ¶[0123]; Note: Convex portion comprises dielectric material which may be grown epitaxially) has a curvature (Per ¶[0123]) Contact region C between curved surface 68b and two-dimensional electron layer 36 of electron transit layer 20) such that the epitaxial semiconductor structure extends up a sidewall (Curved surface; 68b; Fig 2; ¶[0123]) of the second semiconductor region (Region comprising either one or a combination of Electron transit layer and Electron supply layer; 20/22; Fig 2; ¶[0111]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an epitaxial structure extending up a sidewall of the second semiconductor region as taught by Mita to combine it with the first and second semiconductor regions extending above the substrate. One would have been motivated to do this with a reasonable expectation of success in order to create the two-dimensional electron gas (2DEG) due to second semiconductor region (electron supply layer) inducing a difference in electron affinities in the first semiconductor region (electron transit layer) due to the difference in lattice constants in each layer (Mita, ¶¶[0024-0027]). Further, the 2DEG with curvature reduces contact resistance of the surrounding layers, as suggested by Mita (¶[0112]).
12. Claim 47 is rejected under 35 U.S.C. 103 as being unpatentable over Green, Bruce McRae et al. (Pub No. US 20230207676 A1) (hereinafter, Green) as applied to Claim 28 above, and further in view of McLaurin, Melvin (Pub No. US 12191626 B1) (hereinafter, McLaurin).
McLaurin, Fig 15c: Carrier wafer connecting multiple semiconductor devices
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McLaurin, Fig 4: Die singulation
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Re Claim 47 (Original), Green does not teach a singulated semiconductor device comprising the semiconductor of Claim 28.
In the same field of endeavor, McLaurin teaches a singulated semiconductor device (Singulated substrates; 1004; Fig 4a; Col 28 ln 10-15) comprising the semiconductor (Semiconductor devices; Per Col 79 ln 25-40 the epitaxial layer structure is transferred to a carrier wafer comprising semiconductor devices) of Claim 28.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have combined a singulated semiconductor device as taught by McLaurin with the semiconductor device comprising of providing semiconductor islands, epitaxial structures, and ohmic contacts, of Green. One would have been motivated to do this with a reasonable expectation of success because combining the functions of the carrier wafer and finished semiconductor device submount, the number of components and operations needed to build a packaged device is reduced, thereby lowering the cost of the final semiconductor device significantly, as suggested by McLaurin (Col 19 ln 54-67).
Allowable Subject Matter
13. Claims 1-2, 12-15, 20-21, 26, 48-49 and 52 are allowed.
Regarding claim 1, the closest prior art Green, Bruce McRae et al. (Pub No. US 20230207676 A1) (hereinafter, Green) in view of Hao, Ronghui et al. (Pub No. US 20220376084 A1) (hereinafter, Hao) either singularly or in combination fails to anticipate or render obvious
“A method of forming a semiconductor structure, comprising:
forming an epitaxial semiconductor island comprising a first material characteristic on a substrate, wherein the epitaxial semiconductor island comprises a discrete epitaxial region that protrudes above the substrate; and
growing an epitaxial semiconductor structure from the epitaxial semiconductor island and the substrate, wherein the epitaxial semiconductor structure comprises a second material characteristic that is different from the first material characteristic of the epitaxial semiconductor island;
wherein the epitaxial semiconductor island extends to, contacts, or forms a part of, an active region of the semiconductor structure,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
Regarding claim 48, the closest prior art Green, Bruce McRae et al. (Pub No. US 20230207676 A1) (hereinafter, Green) in view of Hao, Ronghui et al. (Pub No. US 20220376084 A1) (hereinafter, Hao) either singularly or in combination fails to anticipate or render obvious
“A semiconductor wafer, comprising:
a plurality of epitaxial semiconductor islands on an upper surface of the semiconductor wafer and comprising a first material characteristic;
wherein the plurality of epitaxial semiconductor islands are laterally spaced from one another along the upper surface of the semiconductor wafer and are configured such that semiconductor devices are formed from epitaxial semiconductor material with at least one second material characteristic different from the first material characteristic that is grown from the epitaxial semiconductor islands and the semiconductor wafer and extend to, contact or form a part of active structures of the semiconductor devices,”
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
14. In the instant case, re claims 1 and 48, referring to Fig. 7 of Hao, although an epitaxial structure that may be grown from the epitaxial semiconductor island, the disclosure of Hao does not indicate the epitaxial structure is an epitaxial semiconductor structure, as amended by the applicant. The prior art does not disclose any epitaxial semiconductor structure grown from said epitaxial semiconductor islands which are discrete regions/laterally spaced apart above a substrate. Further, Green does not teach epitaxial semiconductor structures grown from the epitaxial semiconductor island, therefore Green in view of Hao cannot render claims 1 and 48 obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY EDWARD DUREN whose telephone number is (703)756-1426. The examiner can normally be reached 07:30 - 17:00 PST.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817