DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 5-6, 8, and 16 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites “…wherein the carrier and the interconnection structure are electrically connected through the first electronic component.” This limitation is not disclosed in the specification or in the drawings. For example, applicant’s FIG 2B shows power path P2 entering into the component 22 but not then connecting to the carrier. Claim 6 is rejected due to its dependence upon claim 5.
Claim 16 is rejected for containing an analogous limitation as that recited in claim 5.
Claim 8 recites “the power regulating component and the heat dissipation element are not overlapped with each other along the direction.” However, this limitation is not positively recited anywhere within applicant’s disclosure. Though figures appear to show this relation between the elements, this is insufficient to provide basis for the claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites “a plurality of power regulating components” in line 2. It is unclear whether these refer to “the plurality of power regulating components” recited in claim 13. For the purpose of compact prosecution, the examiner is interpreting those power regulating components recited in claim 14 to be the same as those recited in claim 13.
Claim 15 recites “wherein the first data storage component and the second data storage component extend exceed the backside surface of each of the plurality of electronic components…” [emphasis added]. This language makes unclear the relative positions of the data storage components and the electronic components. This degree of indefiniteness is severe enough to prevent examination of claim 15 (as well as dependent claim 16).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190164893 (Kim et al) and US 20230387762 (Waltrich et al).
As to Claim 1, Kim teaches an electronic module, comprising:
A first electronic component having a first surface and a second surface opposite to the first surface (Kim Fig 9, chip 120, first and second surfaces bottom and top of 120); and
an interconnection structure disposed over the first surface of the first electronic component (interposer 130 above bottom surface of 120);
wherein the interconnection structure comprises a first region and a second region different from the first region (first region being that portion of 130 not beneath heat dissipation pattern HD; second region being that beneath HD), and wherein the second region and the first region overlap the first electronic component (both regions overlap 120);
wherein the second region is configured to dissipate heat from the first surface of the first electronic component (heat generated in the bottom of 120 reasonably diffuses to the top of 120, and through the second region. This second region explicitly disclosed as dissipating through patterns 132’, vias 133’, and heat dissipation pattern HD, ¶0084).
However, Kim does not explicitly teach wherein the first region is configured to transmit power received from outside of the electronic module to the first surface of the first electronic component.
Waltrich teaches a device similar to that of Kim, explicitly having an electronic component (Waltrich Fig 2A, gate driver circuit 13) and an interconnection structure (carrier substrate 11 having conductive layers 112 within) having a first region configured to receive power outside the module (left-side of 10 takes DC power input) to the electronic component (input signal electrically connected to gate driver 13, ¶0166) as well as a second region configured to dissipate heat (second region having integrated heat sink 15).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the module having an interconnection structure including a heat dissipation region taught by Kim with the interconnect structure both supplying power and allowing heat dissipation taught by Waltrich in order to remove the need for separate power interconnects and heat dissipation devices, thereby reducing the number of components needed in the module and overall module size.
As to Claim 2, the combination of Kim and Waltrich teaches the electronic module of claim 1. Kim further teaches wherein a circuit density in the second region is higher than that in the first region (Kim Fig 9, features 132’ and 133’ more densely packed than features 132 and 133), and wherein from a top-view perspective, the second region extends along two non-parallel directions and along two adjacent sides of the first region (region containing HD disposed in region corresponding to top of 120 ¶0108, i.e., extends along two non-parallel dimensions in a top-view).
As to Claim 3, the combination of Kim and Waltrich teaches the electronic module of claim 1. Kim further teaches a first group of electrical contacts connecting between the interconnection structure and the first surface of the first electronic component (pads P connecting to bottom of 120 through intermediate top of 120); and
a heat dissipation element disposed over the first region and overlapping the first group of electrical contacts (HD above first region as shown in Fig 9, overlapping pads P).
As to Claim 4, the combination of Kim and Waltrich teaches the electronic module of claim 3. Kim further teaches a carrier supporting the first electronic component (160) ; and
a second group of electrical contacts connecting between the carrier and the second surface of the first electronic component (contacts 185 physically connect 160 to top of 120 through bottom side of 120).
As to Claim 7, the combination of Kim and Waltrich teaches the electronic module of claim 1. Waltrich, as applied to claim 1, a power regulating component disposed over the first region (Waltrich Fig 2A, intermediate smoothing capacitor 14 over first region). While Waltrich does not explicitly teach the power regulating component overlapping the first electronic component along a direction substantially perpendicular to the first surface of the first electronic component, this is a matter of rearrangement of parts, which has been held to be obvious over the prior art.
Kim further teaches a heat dissipation element disposed over the second region and overlapping the first electronic component along the direction (HD over regions of component 120).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, Waltrich, and US 20200185300 (Xu et al).
As to Claim 9, Kim teaches an electronic module, comprising:
An electronic component (Kim Fig 9, chip 120);
an interconnection structure disposed over the electronic component (interposer 130 over chip 120);
wherein the interconnection structure is configured to provide a plurality of paths respectively passing through a backside surface of the electronic components (can reasonably call the bottom surface of chip 120 a backside surface); and
a heat dissipation element disposed over the interconnection structure, wherein the interconnection structure and the heat dissipation element are configured to provide a heat dissipation path passing through the backside surface of the electronic component (HD over 130 explicitly allow for heat dissipation path ¶0084).
Kim does not explicitly teach the electronic component instead being a plurality of electronic components, nor does it teach the plurality of interconnection paths explicitly being power paths.
Waltrich teaches a device similar to that of Kim, explicitly having an electronic component (Waltrich Fig 2A, gate driver circuit 13) and an interconnection structure (carrier substrate 11 having conductive layers 112 within) having a first region configured to receive power outside the module (left-side of 10 takes DC power input) to the electronic component (input signal electrically connected to gate driver 13, ¶0166).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the module having an interconnection structure including a heat dissipation region taught by Kim with the interconnect structure both supplying power and allowing heat dissipation taught by Waltrich in order to remove the need for separate power interconnects and heat dissipation devices, thereby reducing the number of components needed in the module and overall module size.
However, the combination of Kim and Waltrich still fails to explicitly teach a plurality of electronic components in the module.
Xu teaches a device similar to that of Kim and Waltrich, and specifically teaches a plurality of electronic components (Xu Fig 1A, dies 108 and 109) sharing a single interconnect structure (102).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the module having an interconnect comprising power paths taught by Kim and Waltrich with the package comprising two electronic components and sharing a single interconnect structure taught by Xu in order to provide more devices on a single module, reducing the need for a separate module for the second electronic component.
Claim(s) 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Waltrich, and Xu as applied to claim 9 above, and further in view of US Patent 9,653,443 (Cheng et al).
As to Claim 10, the combination of Kim, Waltrich, and Xu teaches the electronic module of claim 9. None of the cited art teaches wherein from a top-view perspective the heat dissipation element has a cruciform.
Cheng teaches a similar device to that of Kim, Waltrich, and Xu, and further teaches a heat dissipation element having a cruciform shape (Cheng Fig 4E; Col 7 Lines 50-58).
It would have been obvious to one of ordinary skill in the art at the time of filing because the substitution of the heat dissipation element taught by Kim, Waltrich, and Xu for that having a cruciform-shape taught by Cheng would have yielded predictable results to one of ordinary skill in the art.
As to Claim 11, the combination of Kim, Waltrich, Xu, and Cheng teaches the electronic module of claim 10. Kim further teaches wherein the plurality of power paths are disposed around the heat dissipation path (additional paths to left/right of heat dissipation path. Waltrich as applied to claim 9 teaches those additional paths may comprise power paths).
As to Claim 12, the combination of Kim, Waltrich, Xu, and Cheng teaches the electronic module of claim 11. Waltrich, combined with the structure taught by Kim, further teaches wherein the interconnection structure comprises a plurality of first regions (far left and far right sides of 130 in Kim Fig 9) configured for providing the plurality of power paths (Waltrich teaches those paths providing power to electronic components), and a second region separating the plurality of first regions and configured for providing the heat dissipation path (Kim Fig 9, second region being that having HD overtop which separates the left and right sides of the structure 130).
Cheng, as applied to claim 10, further teaches a boundary of the heat dissipation element defines a boundary of the second region (HD in Kim defines a boundary of second region; see claim 1 rejection)
As to Claim 13, the combination of Kim, Waltrich, Xu, and Cheng teaches the electronic module of claim 12. Kim further teaches a plurality of connectors disposed over a corresponding one of the plurality of electronic components (Kim Fig 9, pads “P” over 120), wherein the plurality of connectors configured to receive the power and transmit the power to the plurality of first regions (Waltrich teaches those regions receiving power from outside of the module).
As to Claim 14, the combination of Kim, Waltrich, and Xu teaches the electronic module of claim 13. Kim further teaches a plurality of connectors disposed over the plurality of first regions (Kim Fig 9, pads “P” over first regions), and configured to receive the power and transmit the power to the plurality of first regions (Waltrich teaches those regions receiving power from outside of the module).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim and Waltrich as applied to claim 1 above, and further in view of Xu.
As to Claim 17, the combination of Kim and Waltrich teaches the electronic module of claim 1. However, the combination does not explicitly teach a second electronic component or its relative disposition.
Xu, for exactly the same reasons as those applied to claim 9, explicitly teaches plural electronic components connecting to a first surface of the shared interconnect structure (Xu Fig 1A, dies 108/109 on same side of 102, and may explicitly contain more than just the two dies shown ¶0031).
Further, Xu explicitly teaches a passive component connecting to the first surface of the interconnect structure, wherein the passive component is disposed between the first electronic component and the second electronic component (EMIB between dies 108/109, wherein the EMIB is being reasonably interpreted as constituting a passive component).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, Waltrich, and Xu as applied to claim 17 above, and further in view of US 20190206840 (Lee et al).
As to Claim 18, the combination of Kim, Waltrich, and Xu teaches the electronic module of claim 17. Kim further teaches:
a heat dissipation element disposed over a second surface of the interconnection structure opposite to the first surface of the interconnection structure (HD over top side of 130).
However, these references fail to explicitly teach a first or second data storage component or their positions relative to the interconnection structure.
Lee teaches a device similar to that taught by Kim, Waltrich, and Xu, and specifically teaches an a data storage component (Lee Fig 1, memory device 12 ¶0021) disposed to a side of an electronic component (SoC 11 ¶0021) wherein the data storage component is configured to support data storage and retrieval operations (12 may store data for chip 11 ¶0021).
It would have been obvious to one of ordinary skill in the art at the time of filing to combine the electronic module taught by Kim, Waltrich, and Xu with the data storage component disposed to the side of the electronic component taught by Lee in order to have data storage and related electronic components on the same substrate, thereby removing need for two separate packages (Lee ¶0029). While Lee only explicitly teaches one data storage component and one electronic component, it would have been obvious in light of the teaching of Xu, as applied to claim 17, to instead have a first and second data storage component on either side of a single interconnect structure, the single interconnect structure itself comprising a first and second electronic component.
As to Claim 19, the combination of Kim, Waltrich, Xu, and Lee teaches the electronic module of claim 18. The relative position of the electronic components as outlined in claim 18 may reasonably be considered to be at corners of that interconnection structure, satisfying the limitations of claim 18.
As to Claim 20, the combination of Kim, Waltrich, Xu, and Lee teaches the electronic module of claim 18. Kim teaches an additional connection member beneath the electronic components (Kim Fig 9, 160). This, when combined with the additional elements as combined in claim 18, teach all limitations of claim 20.
Response to Arguments
Applicant's arguments filed 17 September 2025 have been fully considered, but are moot in light of the new rejection mapping defined above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corbyn D Mellinger whose telephone number is (703)756-5683. The examiner can normally be reached M-F 9-6 Eastern.
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/Corbyn D Mellinger/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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