DETAILED ACTION
This action is responsive to the amendment filed August 18, 2025. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant is reminded when submitting amendments in Patent Center, the amendments must be in all black font. When amendments are submitted in other colors, likely due to the track changes option in Word, this prevents our automated OCR tools from recognizing the fonts in different colors.
Drawings
The drawing objections are withdrawn in view of the replacement drawings and the amended claims.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3, 6-18, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “forming a self-aligned via” rendering the claim indefinite. It is unclear what structure Applicant regards as a self-aligned via, nor is it clear what steps or manipulations are required or excluded by the claimed “forming a self-aligned via”. Also, with respect to claim 1, there is no context or disposition provided with respect to the claimed “forming a self-aligned via” making it unclear where or from what the claimed self-aligned via is formed. There is no standardized process for forming a self-aligned via nor does a self-aligned via correspond to any standardized structure. Requirements with respect to where, on/in what, and how the self-aligned via is formed are unclear.
Claim 13 recites etching the second dielectric material to expose an upper surface of the first conductive lines; etching the second dielectric material to expose an upper surface of the first etch stop layer. This limitation is unclear because it is not the etching of the second dielectric material 124 that exposes first conductive lines 202 but rather the etching of the hard mask layer 206 and etching the second etch stop layer 204 that exposes the upper surface of first conductive lines 202. Etching 124 also does not expose the upper surface of 210 either. The upper surface of 210 is only exposed after etching 202 (see Figs. 7-8). While many deposition and etch processes occur before the upper surfaces of 202 are exposed, reciting etching a layer that is several layers above the exposed surface to expose said surface implies the removal of 124 exposes 202 and 210, which is not the case.
Claim 17 recites … and to etch the dielectric layer to expose an upper surface of the first conductive lines. It is unclear what Applicant regards as “etch … to expose” in view of the specification and figures. To expose the upper surface of the first conductive lines, layers 206 and then 204 must be etched to expose the surface. Etching the dielectric layer 124 does not expose the upper surface of first conductive lines 202. In view of Figs. 6-8 it is entirely unclear how or where the dielectric layer 124 is supposed to be etched to expose an upper surface of the first conductive lines 202. Also see discussion above regarding claim 13.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3, and 9-16 are rejected under 35 U.S.C. 103 as being unpatentable over Mebarki et al. (US 2015/0056800), in view of Naik et al. (US 2014/0273430), Bothra (US 6,281,585), Wu et al. US 2016/0099174), Ding et al. (US 2011/0306215), and Zhang et al. (US 2020/0303252), all of record, and Yamazaki et al. (US 7,242,449), newly cited.
(Re Claim 1) Mebarki teaches a method of forming an interconnect structure, the method comprising:
etching a lithographic patterning structure to form a partially patterned structure having first conductive lines and to expose a top surface of a first etch stop layer (Fig. 2B, first etch stop layer 106), the lithographic patterning structure comprising a substrate having a barrier layer thereon (substrate not shown, below barrier layer 102, ¶20, alternatively, a barrier layer may be added as discussed below), a first metal layer (104) on the barrier layer, a first etch stop layer (106) on the first metal layer, a second metal layer (108) on the first etch stop layer, a second etch stop layer (210) on the second metal layer, a hard mask layer (212) on the second etch stop layer, wherein etching the lithographic patterning structure comprises etching the second metal layer in a first direction to the top surface of the first etch stop layer (Fig. 2B);
etching the first stop layer of the partially patterned structure and subsequently etching the first metal layer to form second conductive lines and expose a top surface of the barrier layer; and forming a self-aligned via (Figs. 7A-8C, 106 and 104 are etched to expose 102).
Alternatively, with respect to the barrier, Mebarki discloses 102 is an underlying semiconductor structure having vias, devices, and the like, but is silent regarding specifics of the structure. A PHOSITA desiring to make and use Mebarki’s interconnects would be motivated to look to related art to teach how to interface the interconnect structure with an underlying structure. Related art from Naik teaches when forming a metal interconnect over an underlying structure 102, a metal barrier 104 (¶19) is used. Related art from Bothra also teaches when forming a metal interconnect over an underlying structure 119/100, a metal barrier 102c (col 5, lines 45-54) is used. A PHOSITA would recognize the benefits of using a barrier layer are to prevent diffusion of the metals into the underlying dielectric layer(s) while also improving adhesion. A PHOSITA would find it obvious to further include a barrier as taught by Naik and Bothra in the layer stack for its known benefits. When incorporating the barrier layer as taught by Naik and Bothra, the layer will be exposed during the etching.
Mebarki is silent with respect to a first dielectric layer on the hard mask layer, and a patterned photoresist on the first dielectric layer. Mebarki discloses a “lithography stack” (114) which may be a combination of layers for patterning the underlying structure (¶78). Notably Mebarki later discloses using a lithography stack comprising a photoresist (502) over a BARC or spin-on dielectric (402) with respect to the subsequent patterning in Figs. 4-6 (¶¶83-85), and a PHOSITA would recognize this conventional stack and readily available processes and materials would be applicable to the lithography stack (114). Thus, a PHOSITA would find it obvious to use Mebarki’s subsequently disclosed layers in the lithography stack. Alternatively, a PHOSITA may be motivated to look to related art to teach suitable layers for Mebarki’s lithography stack (114, 214) and simply select a combination of known, working layers/materials from the prior art. Related art from Wu teaches using a combination of photoresist (414) over dielectrics (408, 410, 412) for patterning an underlying structure (¶¶ 34-35). Further noting layer (406) is TiN having a hard mask (408) thereon which corresponds to Mebarki’s TiN layer (210) also having a hard mask (212), thus one would expect the combination of layers to be compatible and perform well. Related art from Ding teaches using a combination of photoresist (208) over one or more dielectric layers (206) for patterning the underlying structure (¶¶ 20-22). Related art from Zhang also teaches using a combination of photoresist (104) over one or more dielectric layers (102, 103) for patterning the underlying structure (¶¶ 36,41). With respect to Ding and Zhang, the dielectric layers are anti-reflection coatings which are well known in the art for improving photoresist imaging/exposure. In view of Wu, Ding, and Zhang, a PHOSITA would find it obvious to use a combination of a patterned photoresist over a dielectric layer for the lithography stack (114) disclosed by Mebarki as these are conventional layers used in lithography stacks for patterning underlying films.
Mebarki is silent regarding an etch rate of the second metal layer 108 is in the range of about 0.5nm/s to about 5nm/s. A PHOSITA desiring to make and use Mebarki’s invention would be motivated to look to related art to teach etch rates for metal layer 108 (e.g. W, ¶76). Related art from Yamazaki teaches tungsten can be etched in an ICP etcher at an etch rate of 2-5 nm/sec according to the disclosed process (col 14 lines 48-62). A PHOSITA would find it obvious to select a known, working etch process from the prior art to etch Mebarki’s layer 108 at a reasonable etch rate.
(Re Claim 3) wherein the first dielectric layer comprises one or more of a bottom anti-reflective coating (BARC) or a spin-on dielectric material (¶¶ 83-85).
(Re Claim 9) wherein the first metal layer and the second metal layer independently comprise one or more of tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), aluminum (AI), or copper (Cu) (¶¶74,76).
(Re Claim 10) wherein the first etch stop layer and the second etch stop layer independently comprise one or more of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), cobalt (Co), ruthenium (Ru), niobium (Nb), or niobium nitride (NbN) (¶¶75,77).
(Re Claim 11) wherein the hard mask layer comprises one or more of silicon oxide (SiO), silicon nitride (SiN), silicon carbide (SiC), aluminum oxide (AIOx), or aluminum nitride (AIN).
Mebarki is silent with respect to the hard mask material (112), however as modified in view of Ding, as discussed above to incorporate Ding’s lithography stack (¶¶ 16, 20, 21) for improved patterning, it is noted the second antireflective layer materials are also well known hard mask materials (e.g. SiC, SiN, ¶21). By the modification in view of Ding, a PHOSITA would recognize that using one of these materials for layer (112) would have the added benefit of simultaneously functioning as a hard mask while reducing reflections at the interfaces thereby improving the patterning process. Alternatively, when modified in view of Wu to include the lithography stack materials, Wu discloses a silicon oxide hard mask layer (408, corresponding to Mebarki’s hard mask layer 112) over a TiN layer (406, corresponding to Mebarki’s 110). A PHOSITA would find it obvious to use a common hard mask material as disclosed by Wu, such as silicon oxide (¶35), to ensure good adhesion and compatibility with the adjacent layers.
(Re Claim 12) wherein the hard mask layer comprises silicon oxide (SiO) (see discussion above Re claim 11) and the second metal comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), aluminum (AI) or copper (Cu) (¶76).
(Re Claim 13, also see §112 rejection above) wherein forming the self-aligned via comprises: depositing a second dielectric material (Fig. 4, 402) on the first conductive lines and second conductive lines; etching the second dielectric material to expose an upper surface of the first conductive lines (Figs. 7A-7C); etching the second dielectric material to expose an upper surface of the first etch stop layer (since etching progresses from top to bottom, just prior to Fig. 7A, the etching will expose a top surface of 106); and removing the second dielectric material (Figs. 7A-7C).
(Re Claim 14) wherein the second dielectric material (402) comprises one or more of a bottom anti-reflective coating (BARC) or a spin-on dielectric material (¶83).
(Re Claim 15) wherein the barrier layer is a metal liner (Naik ¶19, Bothra col 5, lines 45-54).
(Re Claim 16) wherein the metal liner comprises one or more of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN),or tantalum/tantalum nitride (Ta/TaN) (Naik ¶19, Bothra col 5, lines 45-54).
Allowable Subject Matter
Claim 6 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 7 and 8 depend from allowable claim 6 and are allowable.
Claims 17, 18, and 20 will be allowable once the §112 issues above are overcome.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
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