DETAILED ACTION
This Notice is responsive to communication filed on 12/22/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 12/22/2025 has been acknowledged and entered into the record. Claim 20 has been cancelled.
Updated drawings entered on 12/22/2025 overcome the drawing objections presented in the previously disclosed Non-Final Rejection dated 09/22/2025.
Amended claim 5 overcomes the 112b rejection presented in the previously disclosed Non-Final Rejection dated 09/22/2025.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 18, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nendai et al. (US 20190371872).
Regarding claim 1, Nendai teaches a pixel Fig. 5: 100 comprising:
an emission area Fig. 5: 100a and a non-emission area Fig. 5: 100b;
a via layer Fig. 5: 116 including a lower surface (bottom surface of Fig. 5: 116) and at least one upper surface (upper surface of Fig. 5: 116) that are opposite each other (as shown in Fig. 5), the via layer Fig. 5: 116 comprising a first part having a first thickness and a second part having a second thickness different from the first thickness (annotated below);
a first alignment electrode Fig. 5: 117 and a second alignment electrode Fig. 5: 117 (corresponding to annotated Fig. 3 below; para. 0081 teaches alternating luminous and non-luminous regions 100a/b, where each non luminous region 100b includes a connection electrode layer 117) on the via layer Fig. 5: 116 and spaced from each other (shown in Fig. 3, Fig. 5; see annotated Fig. 3 below);
an insulating layer Fig. 5: 118 on the via layer Fig. 5: 116, the first alignment electrode Fig. 5: 117, and the second alignment electrode Fig. 5: 117, the insulating layer Fig. 5: 118 having a planar surface (shown in Fig. 5);
a first electrode Fig. 5: 119 and a second electrode Fig. 5: 119 (corresponding to the second alignment electrode annotated in Fig. 3 below) in the emission area Fig. 5: 100a and spaced from each other (see Fig. 5: δY spacing); and
light emitting elements Fig. 5: Light emitting element unit on the planar surface of the insulating layer Fig. 5: 118 in the emission area Fig. 5: 100a, and electrically connected to the first electrode Fig. 5: 119 and the second electrode Fig. 5: 119 (para. 0100),
wherein the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117 are on the second part of the via layer Fig. 5: 116 and overlap the second part of the via layer Fig. 5: 116 (shown in Fig. 5 annotated below; annotated First alignment electrode is disposed on and only overlaps annotated T2 which is the shorter second part of the via layer), and
wherein a distance between a surface of the first alignment electrode Fig. 5: 117 that touches the insulating layer Fig. 5: 118 and the lower surface of the via layer Fig. 5: 116 is a same as the first thickness (see annotated Fig. 5 below).
PNG
media_image1.png
575
963
media_image1.png
Greyscale
Zoomed in Fig. 5:
PNG
media_image2.png
447
405
media_image2.png
Greyscale
PNG
media_image3.png
797
1209
media_image3.png
Greyscale
Regarding claim 18, Nendai teaches a display device Fig. 3: 10 comprising:
a substrate Fig. 5: 100p including a display area and a non-display area (annotated Fig. 3 below); and
a plurality of pixels Fig. 5: 100 in the display area, each of the plurality of pixels including an emission area Fig. 5: 100a and a non-emission area Fig. 5: 100b,
wherein each of the plurality of pixels Fig. 5: 100 comprises:
a via layer Fig. 5: 116 on the substrate Fig. 5: 100p, and including a lower surface and at least one upper surface that are opposite each other, and including a first part having a first thickness, and a second part having a second thickness different from the first thickness (annotated Fig. 5 above);
a first alignment electrode Fig. 5: 117 and a second alignment electrode Fig. 5: 117 on the via layer Fig. 5: 116 and spaced from each other (see annotated Fig. 3 above);
an insulating layer Fig. 5: 118 on the via layer Fig. 5: 116, the first alignment electrode Fig. 5: 117, and the second alignment electrode Fig. 5: 117, and having a planar surface (shown in Fig. 5);
a first bank pattern Fig. 5: 122 (left of light emitting elements) and a second bank pattern Fig. 5: 122 (right of light emitting elements) in the emission area Fig. 5: 100a, the first bank pattern Fig. 5: 122 being on the insulating layer Fig. 5: 118 on the first alignment electrode Fig. 5: 117, and the second bank pattern Fig. 5: 122 being on the insulating layer Fig. 5: 118 on the second alignment electrode Fig. 5: 117;
light emitting elements Fig. 5: Light emitting element unit on the insulating layer Fig. 5: 118 between the first bank pattern Fig. 5: 122 and the second bank pattern Fig. 5: 122 in the emission area Fig. 5: 100a;
a first electrode Fig. 5: 119 in the emission area Fig. 5: 100a and electrically connected to the first alignment electrode Fig. 5: 117 and respective first ends of the light emitting elements Fig. 5: Light emitting element unit (para. 0100); and
a second electrode Fig. 5: 119 in the emission area Fig. 5: 100a and electrically connected to the second alignment electrode Fig. 5: 117 and respective second ends of the light emitting elements Fig. 5: Light emitting element unit (para. 0100),
wherein each of the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117 has a first surface at a level that is the same as a level of an upper surface of the first part of the via layer Fig. 5: 116 (shown in Fig. 5),
wherein a distance between the first surface of the first alignment electrode Fig. 5: 117 that touches the insulating layer Fig. 5: 118 and the lower surface of the via layer Fig. 5: 116 is a same as the first thickness (see annotated zoomed in Fig. 5 above).
PNG
media_image4.png
797
1209
media_image4.png
Greyscale
Regarding claim 21, Nendai teaches an electronic device Fig. 1: 1 comprising the display device according to claim 18.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nendai et al. (US 20190371872) as applied to claims 1 and 18 above, and further in view of Kim et al. (KR 20210145590).
Regarding claim 2, although Nendai teaches the substantial features of the claimed invention, Nendai fails to explicitly teach the pixel according to claim 1, wherein, in a sectional view, an upper surface of the first part of the via layer protrudes compared to an upper surface of the second part of the via layer. However, Kim teaches the pixel wherein, in a sectional view, an upper surface of the first part of the via layer (first part annotated below) protrudes compared to an upper surface of the second part of the via layer (second part annotated below) (para. 0041 teaches layer 154 comprises epoxy resin). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Nendai and Kim for the purpose of preventing a failure due to conduction through an undesired path between the plurality of light emitting cells and the printed circuit board (para. 0049).
PNG
media_image5.png
464
904
media_image5.png
Greyscale
Regarding claim 3, Nendai teaches the pixel according to claim 2, wherein the first thickness (annotated Fig. 5 T1 above) is greater than the second thickness (annotated Fig. 5 T2 above).
Regarding claim 4, Nendai teaches the pixel according to claim 3, wherein each of the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117 has a surface located at a level that is the same as a level of the upper surface of the first part of the via layer Fig. 5: 116 (bottom surface of the ALEs 117 are on the same level as the upper surface of layer 116).
Regarding claim 5, Nendai teaches the pixel according to The pixel according to wherein each of the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117 includes a first surface (bottom surface of 117) and a second surface (top surface of 117) that are opposite each other, wherein the surface of the first alignment electrode Fig. 5: 117 that touches the insulating layer Fig. 5: 118 is the second surface of the first alignment electrode Fig. 5: 117, wherein the first surface contacts the upper surface of the second part of the via layer Fig. 5: 116, and the second surface contacts the insulating layer Fig. 5: 118, and wherein a surface of each of the first electrode Fig. 5: 119 and the second electrode Fig. 5: 119 corresponds to the second surface (shown in Fig. 5).
Regarding claim 6, Nendai teaches the pixel according to claim 4, wherein, in a sectional view, the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117 are spaced from each other with the first part of the via layer Fig. 5: 116 interposed therebetween. Fig. 5 annotated below shows the first parts (annotated T1) interposed between the alignment electrodes. Fig. 3 annotated below shows the parts that the first and second alignment electrodes correspond to.
PNG
media_image6.png
570
962
media_image6.png
Greyscale
PNG
media_image3.png
797
1209
media_image3.png
Greyscale
Regarding claim 7, Nendai teaches the pixel according to claim 6, wherein the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117 do not overlap the first part of the via layer Fig. 5: 116 (shown in Fig. 5 annotated above; Alignment electrodes 117 only sit on T2/shorter portion of the via layer, without overlapping the T1 portions).
Regarding claim 8, Nendai teaches the pixel according to claim 4, wherein the via layer Fig. 5: 116 comprises an organic insulating layer (para. 0148, SiO2), but fails to explicitly teach the insulating layer comprises an inorganic insulating layer. However, Kim teaches the insulating layer Fig. 6: 132+152 comprises an inorganic insulating layer (para. 0036 teaches item 132 is an insulating inorganic layer, i.e. silicon nitride; para. 0041 teaches item 152 is an insulating inorganic layer, i.e. silicon nitride). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Nendai and Kim for the purpose of separating the plurality of light emitting stacked structured, and electrically separating the electrodes (para. 0036).
Regarding claim 9, Nendai teaches the pixel according to claim 4, further comprising: a first bank pattern Fig. 5: 122 on the insulating layer Fig. 5: 118 between the first alignment electrode Fig. 5: 117 and the first electrode Fig. 5: 119 (a portion of item 122 sits between electrode 117 and electrode 119); and a second bank pattern Fig. 5: 122 on the insulating layer Fig. 5: 118 between the second alignment electrode Fig. 5: 122 and the second electrode Fig. 5: 119, wherein the light emitting elements Fig. 5: Light emitting element unit are on the insulating layer Fig. 5: 118 between the first bank pattern Fig. 5: 122 and the second bank pattern Fig. 5: 122.
Regarding claim 10, Nendai teaches the pixel according to claim 9, further comprising: a bank Fig. 4A: 522Y on the insulating layer Fig. 5: 118 in the non-emission area Fig. 5: 100b, and including a first opening Fig. 4A: 522zR corresponding to the emission area Fig. 4A: 100a, and a second opening Fig. 4A: 522zG spaced from the first opening Fig. 4A: 522zR (shown in Fig. 4A); a light conversion pattern Fig. 5: 127+131 on the light emitting elements Fig. 5: Light emitting element unit and the first electrode Fig. 5: 119 and the second electrode Fig. 5: 119 in the emission area Fig. 5: 100a (also shown in Fig. 6); and a light block pattern Fig. 6: 129 on the bank Fig. 6: 522 in the non-emission area Fig. 5: 100b (light block on the bank is shown in Fig. 6).
Regarding claim 11, Nendai teaches the pixel according to claim 10, wherein the first bank pattern Fig. 9D: 122, the second bank pattern Fig. 9D: 122, and the bank Fig. 9D: 522 comprise a same material (para. 0154, 0156, “acrylic resin”) and are at a same layer (shown in Fig. 9D; para. 0204).
Regarding claim 12, Nendai teaches the pixel according to claim 10, wherein the light conversion pattern Fig. 5: 127+131 comprises: a color conversion layer Fig. 5: 127 on the first electrode Fig. 5: 119 and the second electrode Fig. 5: 119, and configured to convert a first color of light emitted from the light emitting elements to a second color of light (para. 0241 teaches a layer that contains light-transmissive ultraviolet curable resin which is well known in the art as a color conversion layer); and a color filter Fig. 5: 128 on the color conversion layer Fig. 5: 127 and configured to allow the second color of light to selectively pass therethrough (para. 0129).
Regarding claim 13, Nendai teaches the pixel according to claim 9, further comprising: a substrate Fig. 5: 100p; at least one transistor Fig. 2: Tr1, Tr2 on the substrate Fig. 5: 100p; and a power line Fig. 2: Va on the substrate Fig. 5: 100p, the power line Fig. 2: Va being configured to receive a power voltage (para. 0069, 0071), wherein the via layer Fig. 5: 116 is on the transistor and the power line Fig. 5: 101-110 and includes a first contactor Fig. 5: 116a (left) exposing a portion of the transistor Fig. 5: 110 (left), and a second contactor Fig. 5: 116a (right) exposing a portion of the power line Fig. 5: 110 (right).
Regarding claim 14, Nendai teaches the pixel according to The pixel according to wherein the insulating layer Fig. 5: 118 includes a first contact hole Fig. 5: 118a exposing a portion of the first alignment electrode Fig. 5: 117, and a second contact hole Fig. 5: 118a exposing a portion of the second alignment electrode Fig. 5: 117, wherein the first electrode Fig. 5: 119 is electrically connected to the first alignment electrode Fig. 5: 117 through the first contact hole Fig. 5: 118a, and wherein the second electrode Fig. 5: 119 is electrically connected to the second alignment electrode Fig. 5: 117 through the second contact hole Fig. 5: 118a (para. 0100).
Regarding claim 15, Nendai teaches the pixel according to claim 14, wherein the first contact hole Fig. 5: 118a and the second contact hole Fig. 5: 118a are located in the non-emission area Fig. 5: 100b (shown in Fig. 5).
Regarding claim 16, Nendai teaches the pixel according to claim 15, further comprising: a third alignment electrode Fig. 5: 117 on the via layer Fig. 5: 116 between the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117, and spaced from the first alignment electrode Fig. 5: 117 and the second alignment electrode Fig. 5: 117; a fourth alignment electrode Fig. 5: 117 adjacent to the third alignment electrode Fig. 5: 117 and located on the via layer Fig. 5: 116, the fourth alignment electrode Fig. 5: 117 being spaced from the first to the third alignment electrodes Fig. 5: 117; a first intermediate electrode Fig. 5: 119 spaced from the first electrode Fig. 5: 119 and the second electrode Fig. 5: 119, and located on the third alignment electrode Fig. 5: 117; and a second intermediate electrode Fig. 5: 119 spaced from the first electrode Fig. 5: 119 and the second electrode Fig. 5: 119, and located on the fourth alignment electrode Fig. 5: 117. Annotated Fig. 3 shows the relative position of the first to fourth alignment electrodes and the first and second intermediate electrodes.
PNG
media_image3.png
797
1209
media_image3.png
Greyscale
Regarding claim 17, Nendai teaches the pixel according to claim 16, wherein each of the third alignment electrode Fig. 5: 117 and the fourth alignment electrode Fig. 5: 117 has a surface at a level that is the same as a level of the upper surface of the first part of the via layer Fig. 5: 116, wherein, in a sectional view, the first alignment electrode Fig. 5: 117 and the third alignment electrode Fig. 5: 117 are spaced from each other with the first part of the via layer Fig. 5: 116 interposed therebetween, and wherein, in a sectional view, the second alignment electrode Fig. 5: 117 and the fourth alignment electrode Fig. 5: 117 are spaced from each other with the first part of the via layer Fig. 5: 116 interposed therebetween (shown in Fig. 5, with the corresponding portions of the alignment electrodes annotated above; annotated Fig. 5 below shows the spacings relative to the first part of the via layer).
PNG
media_image6.png
570
962
media_image6.png
Greyscale
Regarding claim 19, although Nendai teaches the substantial features of the claimed invention, Nendai fails to explicitly teach the display device according to claim 18, wherein, in a sectional view, the upper surface of the first part of the via layer protrudes compared to an upper surface of the second part of the via layer. However, Kim teaches the display device wherein, in a sectional view, an upper surface of the first part of the via layer (first part annotated below) protrudes compared to an upper surface of the second part of the via layer (second part annotated below) (para. 0041 teaches layer 154 comprises epoxy resin). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the teachings of Nendai and Kim for the purpose of preventing a failure due to conduction through an undesired path between the plurality of light emitting cells and the printed circuit board (para. 0049).
PNG
media_image5.png
464
904
media_image5.png
Greyscale
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-19, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Nkechinyere Esiaba/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 March 13, 2026