DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 16-17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 16, line 2 recites “the drift region has a single area density”. There does not appear to be support for this in the applicant’s disclosure. This makes the claim new matter.
Claim 17, line 2 recites “the drift region has a single area density”. There does not appear to be support for this in the applicant’s disclosure. This makes the claim new matter.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6-7, 9-10, 12-13 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAKABAYASHI (US 20120228637) in view of TU (US 20070278565).
Regarding claim 1, NAKABAYASHI discloses a semiconductor device comprising a metal oxide semiconductor field effect transistor (MOSFET) including:
a semiconductor substrate (the substrate comprising 10, 12, 20, 14 and 16, see fig 1, para 26-31) having a drift layer of a first conductivity type (drift layer 12, see fig 1, para 27);
a channel layer of a second conductivity type (fig 1, 14, para 28) disposed on the drift layer;
a trench gate structure (the gate structure comprising 22 and 24, see fig 1, para 32-33) including
a trench (the trench 18, see fig 1, para 30) penetrating the channel layer and protruding into the drift layer (18 penetrates through 18 and extends into 12, see fig 1), and extending along one direction in a planar direction of the semiconductor substrate as a longitudinal direction (the trench 18 extends in the into-the-plane or depth direction longitudinally, see fig 1),
a gate insulating film (fig 1, 22, para 32) disposed on a wall surface of the trench, penetrating the channel layer, and extending into the drift layer (22 extends through 14 into 12, see fig 1), and
a gate electrode (fig 1, 24, para 33) disposed on the gate insulating film, penetrating the channel layer, and extending into the drift layer (33 penetrates 14 and extends into 12, see fig 1);
a source layer of the first conductivity type disposed in a surface layer portion of the channel layer so as to be in contact with the trench and having an impurity concentration higher than an impurity concentration of the drift layer (n+ source region 16 is more highly doped and n drain region 12, see fig 1, para 29 and 27);
a drain layer of the first conductivity type disposed on a side of drift layer opposite from the channel layer (fig 1, 10, para 26);
a source electrode electrically connected to t the source layer (source electrode 26, see fig 1, para 34); and
a drain electrode electrically connected to the drain layer (drain electrode 28, see fig 1, para 35), wherein
the entire region of the trench protruding into the drift layer is entirely covered with a well layer of the second conductivity type (the portion of the trench 18 that protrudes below 14 into 12 is entirely covered by doped region 20, see fig 1, para 31), and
the well layer is connected to the channel layer (20 is directly connected to 14, see fig 1),
wherein
the well layer is in direct contact with the trench (well layer 20 is in direct contact with the trench 18, see fig 1, para 31).
NAKABAYASHI fails to explicitly disclose a device comprising a source electrode electrically connected to the channel layer and the source layer;
wherein an area density ratio of an impurity area density of the well layer to an impurity area density of the drift layer is in a range from 3.0x10-5 to 2.0x10-4 inclusive.
TU teaches a device comprising a source electrode electrically connected to the channel layer and the source layer (source electrode 63 is directly connected to source region 33 and body region 31, see fig 1, para 27);
wherein an area density ratio of an impurity area density of the well layer (the p-type buffer layer 27 which is in direct contact with the trench 431 can have a volume doping density of 1x10^14 per cubic cm (cm^-3) and a thickness of 0.5 microns or 5x10^-5 cm which combined mean that the density of dopants in 27 per unit area can be 5x10^9 cm^-2, see fig 7, para 18) to an impurity area density of the drift layer (the n-type region containing the channel 32 can be doped with an implant giving it an area density of 1x10^14 cm^-2, see fig 1, para 36) is in a range from 3.0x10-5 to 2.0x10-4 inclusive (the ratio of the area doping densities of 27 to 32 can be 5x10^-5 which is in the range required, see fig 1, para 18 and 36).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the source electrode in contact with the channel and source layers and the area doping density ratio of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the source electrode in contact with the channel and source layers and the area doping density ratio of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Additionally, parameters such as the specific doping density in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust doping densities in the device of NAKABAYSHI in order to increase breakdown tolerance and suppress leakage current (see NAKABAYASHI para 44).
Regarding claim 4, NAKABAYASHI and TU disclose the semiconductor device according to claim 1.
NAKABAYASHI fails to explicitly disclose a device, wherein
the area density ratio is in a range from 3.0x10^-5 to 4.0x10^-5 inclusive.
TU teaches a device, wherein
the area density ratio is in a range from 3.0x10-5 to 4.0x10-5 inclusive (the ratio of the doping area densities of 24 and 32 can be less than 5E-5, see fig 1, para 18 and 36, which is in the range).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the area doping density ratio of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the area doping density ratio of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Additionally, parameters such as the specific doping density in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust doping densities in the device of NAKABAYSHI in order to increase breakdown tolerance and suppress leakage current (see NAKABAYASHI para 44).
Regarding claim 6, NAKABAYASHI and TU disclose the semiconductor device according to claim 2.
NAKABAYASHI fails to explicitly disclose a device, wherein
the area density ratio is in a range from 3.0x10-5 to 4.0x10-5 inclusive.
TU teaches a device, wherein
the area density ratio is in a range from 3.0x10-5 to 4.0x10-5 inclusive (the ratio of the doping area densities of 24 and 32 can be less than 5E-5, see fig 1, para 18 and 36, which is in the range).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the area doping density ratio of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the area doping density ratio of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Additionally, parameters such as the specific doping density in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust doping densities in the device of NAKABAYSHI in order to increase breakdown tolerance and suppress leakage current (see NAKABAYASHI para 44).
Regarding claim 7, NAKABAYASHI discloses a semiconductor device comprising a metal oxide semiconductor field effect transistor (MOSFET) including:
a semiconductor substrate (the substrate comprising 10, 12, 20, 14 and 16, see fig 1, para 26-31) having a drift layer of a first conductivity type (drift layer 12, see fig 1, para 27);
a channel layer of a second conductivity type (fig 1, 14, para 28) disposed on the drift layer;
a trench gate structure (the gate structure comprising 22 and 24, see fig 1, para 32-33) including a trench penetrating the channel layer, protruding into the drift layer (18 penetrates through 18 and extends into 12, see fig 1), and extending along one direction in a planar direction of the semiconductor substrate as a longitudinal direction (the trench 18 extends in the into-the-plane or depth direction longitudinally, see fig 1),
a gate insulating (fig 1, 22, para 32) film disposed on a wall surface of the trench, and
a gate electrode (fig 1, 24, para 33) disposed on the gate insulating film;
a source layer of the first conductivity type disposed in a surface layer portion of the channel layer so as to be in contact with the trench and having an impurity concentration higher than an impurity concentration of the drift layer (n+ source region 16 is more highly doped and n drain region 12, see fig 1, para 29 and 27);
a drain layer of the first conductivity type disposed on a side of drift layer opposite from the channel layer;
a source electrode electrically connected to t the source layer (source electrode 26, see fig 1, para 34); and
a drain electrode electrically connected to the drain layer (drain electrode 28, see fig 1, para 35),
wherein the entire region of the trench protruding into the drift layer is entirely covered with a well layer of the second conductivity type (the portion of the trench 18 that protrudes below 14 into 12 is entirely covered by doped region 20, see fig 1, para 31),
the well layer is connected to the channel layer (22 is directly electrically connected to 14, see fig 1, para 31), and
wherein the well layer is in direct contact with the trench (well layer 20 is in direct contact with the trench 18, see fig 1, para 31).
NAKABAYASHI fails to explicitly disclose a device comprising a source electrode electrically connected to the channel layer and the source layer; and
wherein an area density ratio of an impurity area density of the well layer to an impurity area density of the drift layer is in a range from 3.0x10^-5 to 2.0x10^-4 inclusive.
TU teaches a device comprising a source electrode electrically connected to the channel layer and the source layer (source electrode 63 is directly connected to source region 33 and body region 31, see fig 1, para 27); and
wherein an area density ratio of an impurity area density of the well layer (the p-type buffer layer 27 which is in direct contact with the trench 431 can have a volume doping density of 1x10^14 per cubic cm (cm^-3) and a thickness of 0.5 microns or 5x10^-5 cm which combined mean that the density of dopants in 27 per unit area can be 5x10^9 cm^-2, see fig 7, para 18) to an impurity area density of the drift layer (the n-type region containing the channel 32 can be doped with an implant giving it an area density of 1x10^14 cm^-2, see fig 1, para 36) is in a range from 3.0x10-5 to 2.0x10-4 inclusive (the ratio of the area doping densities of 27 to 32 can be 5x10^-5 which is in the range required, see fig 1, para 18 and 36).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the source electrode in contact with the channel and source layers and the area doping density ratio of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the source electrode in contact with the channel and source layers and the area doping density ratio of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Additionally, parameters such as the specific doping density in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust doping densities in the device of NAKABAYSHI in order to increase breakdown tolerance and suppress leakage current (see NAKABAYASHI para 44).
Regarding claim 9, NAKABAYASHI and TU disclose the semiconductor device according to claim 7.
NAKABAYASHI fails to explicitly disclose a device, wherein
the area density ratio is in a range from 3.0x10-5 to 4.0x10-5 inclusive.
TU teaches a device, wherein
the area density ratio is in a range from 3.0x10-5 to 4.0x10-5 inclusive (the ratio of the doping area densities of 24 and 32 can be less than 5E-5, see fig 1, para 18 and 36, which is in the range).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the area doping density ratio of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the area doping density ratio of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Additionally, parameters such as the specific doping density in the art of semiconductor devices are subject to routine experimentation and optimization to achieve the desired device characteristics during fabrication. It would have been obvious to one of ordinary skill in the art at the time the invention was made to adjust doping densities in the device of NAKABAYSHI in order to increase breakdown tolerance and suppress leakage current (see NAKABAYASHI para 44).
Regarding claim 10, NAKABAYASHI and TU disclose the semiconductor device according to claim 7.
NAKABAYASHI fails to explicitly disclose a device, comprising a plurality of trench gate structures including the trench gate structure.
TU teaches a device, comprising a plurality of trench gate structures including the trench gate structure (there are a plurality of trench gates 57 each in a trench structure, see fig 1, para 23).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the trench gate structures of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the trench gate structures of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Regarding claim 12, NAKABAYASHI and TU disclose the semiconductor device according to claim 7.
NAKABAYASHI fails to explicitly disclose a device, further comprising an interlayer insulating film formed on the channel layer,
wherein the interlayer insulating film has a contact hole,
the source electrode is electrically connected to the channel layer and the source layer through the contact hole.
TU teaches a device, further comprising an interlayer insulating film (fig 1, 61, para 26) formed on the channel layer,
wherein the interlayer insulating film has a contact hole (the hole in 61 through which 63 contacts 33 and 36, see fig 1, para 26),
the source electrode is electrically connected to the channel layer and the source layer through the contact hole (source electrode 63 is connected to 33 and 36 by a hole in 61, see fig 1, para 26).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the interlayer insulating film of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the interlayer insulating film of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Regarding claim 13, NAKABAYASHI and TU disclose the semiconductor device according to claim 1.
NAKABAYASHI fails to explicitly disclose a device, comprising a plurality of trench gate structures including the trench gate structure.
TU teaches a device, comprising a plurality of trench gate structures including the trench gate structure (there are a plurality of trench gates 57 each in a trench structure, see fig 1, para 23).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the trench gate structures of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the trench gate structures of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Regarding claim 15, NAKABAYASHI and TU disclose the semiconductor device according to claim 1.
NAKABAYASHI fails to explicitly disclose a device, further comprising an interlayer insulating film formed on the channel layer,
wherein the interlayer insulating film has a contact hole,
the source electrode is electrically connected to the channel layer and the source layer through the contact hole.
TU teaches a device, further comprising an interlayer insulating film (fig 1, 61, para 26) formed on the channel layer,
wherein the interlayer insulating film has a contact hole (the hole in 61 through which 63 contacts 33 and 36, see fig 1, para 26),
the source electrode is electrically connected to the channel layer and the source layer through the contact hole (source electrode 63 is connected to 33 and 36 by a hole in 61, see fig 1, para 26).
NAKABAYASHI and TU are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the interlayer insulating film of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the interlayer insulating film of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Regarding claim 16, NAKABAYASHI and TU disclose the semiconductor device according to claim 1.
The first embodiment of NAKABAYASHI fails to explicitly disclose a device, wherein the drift region has a single area density.
Another embodiment of NAKABAYASHI teaches a device, wherein the drift region has a single area density (n-type drift layer 12 can have a fixed doping concentration and can have a uniform thickness, see fig 1 and 9A, para 27).
The embodiments of NAKABAYASHI are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the single area density of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the single area density of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Regarding claim 17, NAKABAYASHI and TU disclose the semiconductor device according to claim 7.
The first embodiment of NAKABAYASHI fails to explicitly disclose a device, wherein the drift region has a single area density.
Another embodiment of NAKABAYASHI teaches a device, wherein the drift region has a single area density (n-type drift layer 12 can have a fixed doping concentration and can have a uniform thickness, see fig 1 and 9A, para 27).
The embodiments of NAKABAYASHI are analogous art because they both are directed towards trench gate semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the single area density of TU because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the single area density of TU in order to provide lower on-state resistance and high breakdown voltage (see TU para 7).
Claim(s) 2 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAKABAYASHI (US 20120228637) in view of TU (US 20070278565) and further in view of BOBDE (US 20110127586).
Regarding claim 2, NAKABAYASHI and TU disclose the semiconductor device according to claim 1.
NAKABAYASHI fails to explicitly disclose a device, further comprising
a junction field effect transistor (JFET) including a JFET source electrode, a JFET drain electrode and a JFET gate electrode, wherein
the MOSFET and the JFET are cascode-connected by electrically connecting the JFET source electrode and the drain electrode of the MOSFET.
BOBDE teaches a device, further comprising
a junction field effect transistor (JFET) (the JFET shown in fig 6) including a JFET source electrode (fig 6, 520-S, para 44), a JFET drain electrode (fig 6, 520, para 44) and a JFET gate electrode (fig 6, 530, para 44), wherein
the MOSFET and the JFET are cascode-connected by electrically connecting the JFET source electrode and the drain electrode of the MOSFET (the JFET and MOSFET can be connected cascode fashion, see fig 4, para 38).
NAKABAYASHI, TU and BOBDE are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the cascode JFET of BOBDE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the cascode JFET of BOBDE in order to make the device a normally off power switch device (see BOBDE para 38).
Regarding claim 8, NAKABAYASHI and TU disclose the semiconductor device according to claim 7.
NAKABAYASHI fails to explicitly disclose a device, further comprising
a junction field effect transistor (JFET) including a JFET source electrode, a JFET drain electrode and a JFET gate electrode,
wherein the MOSFET and the JFET are cascode-connected by electrically connecting the JFET source electrode and the drain electrode of the MOSFET.
BOBDE teaches a device, further comprising
a junction field effect transistor (JFET) (the JFET shown in fig 6) including a JFET source electrode (fig 6, 520-S, para 44), a JFET drain electrode (fig 6, 520, para 44) and a JFET gate electrode (fig 6, 530, para 44), wherein
the MOSFET and the JFET are cascode-connected by electrically connecting the JFET source electrode and the drain electrode of the MOSFET (the JFET and MOSFET can be connected cascode fashion, see fig 4, para 38).
NAKABAYASHI, TU and BOBDE are analogous art because they both are directed towards semiconductor transistor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the cascode JFET of BOBDE because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the cascode JFET of BOBDE in order to make the device a normally off power switch device (see BOBDE para 38).
Claim(s) 11 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over NAKABAYASHI (US 20120228637) in view of TU (US 20070278565) and further in view of WEIS (US 20130307059).
Regarding claim 11, NAKABAYASHI and TU disclose the semiconductor device according to claim 10.
NAKABAYASHI fails to explicitly disclose a device, wherein the plurality of trenches are formed in stripes at equal intervals along one direction in the planar direction.
WEIS teaches a device, wherein the plurality of trenches are formed in stripes at equal intervals along one direction in the planar direction (the plurality of trenches 20 are disposed at a pitch which can be 1 micron, see fig 6, para 34).
NAKABAYASHI, TU and WEIS are analogous art because they both are directed towards semiconductor transistor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the trench interval of WEIS because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the trench interval of WEIS in order to decrease the on resistance (see WEIS para 34).
Regarding claim 14, NAKABAYASHI and TU disclose the semiconductor device according to claim 13.
NAKABAYASHI fails to explicitly disclose a device, wherein the plurality of trenches are formed in stripes at equal intervals along one direction in the planar direction.
WEIS teaches a device, wherein the plurality of trenches are formed in stripes at equal intervals along one direction in the planar direction (the plurality of trenches 20 are disposed at a pitch which can be 1 micron, see fig 6, para 34).
NAKABAYASHI, TU and WEIS are analogous art because they both are directed towards semiconductor transistor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify the device of NAKABAYASHI with the trench interval of WEIS because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the device of NAKABAYASHI with the trench interval of WEIS in order to decrease the on resistance (see WEIS para 34).
Response to Arguments
Applicant's arguments filed 2/6/2026 have been fully considered but they are not persuasive.
Regarding claims 1 and 7, the applicant argues that NAKABAYASHI in view of TU do not disclose every element of the claim device for several reasons. These arguments are unpersuasive.
Firstly, the applicant argues that the element of TU previously relied upon by the examiner as the well region (region 24 of fig 1 of TU, see para 18) no longer meets the requirements of the claims because 24 is not in direct contact with the trench (the trench lined with insulator 43 and 431, see fig 1, para 23) as required by the amended claims. This is unpersuasive for several reasons. Firstly, the primary reference NAKABAYASHI already discloses a well region (20, see NAKABAYASHI fig 1, para 31) which is directly in contact with the trench (18, see fig 1, para 31). Thus, TU does not need to disclose this feature since it is already disclosed in NAKABAYASHI. Secondly, although region 24 of TU was used in the previous rejection, region 27 of TU has the same properties of thickness and doping as 24 (see TU para 18) and is disposed directly in contact with the trench (24 is directly in contact with insulator 431 in the trench (see TU fig 1). Thus, 27 can be relied upon instead of 24 as the well region.
Secondly, the applicant argues that TU does not disclose a device with the required area density ratio since the density of dopants per unit area of regions 27 and 32 are not disclosed in TU. It is true that, for region 27, the area doping density is not disclosed, but TU does say, in paragraph 18, that 27 has a volume doping density of 1x10^14 cm^-3 and a thickness of 0.5 microns (or 5x10^-5 cm). Multiplying these together gives an area density of the dopants of 5x10^9 cm^-2. Region 32, as described by TU in paragraph 36, doped with a dose (and thus an area density) of 1x10^14 cm^-2. Dividing these two numbers to get the area density ratio (which is the number specified in the claim, the ratio of the area densities of the well layer to the drift layer) gives a ratio of 5x10^-5, which is in the range between 3x10^-5 to 2x10^-4 as required in the claims.
The examiner notes that, in the arguments of 2/6/2026, the applicant writes that it was agreed in the interview of 1/13/2026 that the amendments would overcome the cited prior art of NAKABAYASHI and TU. This agreement is not reflected in the examiner interview summary record. It is true that the amendments to claims 1 and 7 do exclude the previous interpretation of TU using region 24 as the well layer, since 24 is not in direct contact with the trench, but TU region 27 could be used instead, and NAKABAYASHI already discloses the well layer in direct contact with the trench.
For at least these reasons, and those given in the rejection above, NAKABAYASHI in view of TU discloses every element of claims 1 and 7, which are not patentable over NAKABAYSHI in view of TU.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAS TYLER BEARDSLEY whose telephone number is (571)272-3227. The examiner can normally be reached 930-600 M-F.
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/JONAS T BEARDSLEY/Examiner, Art Unit 2811
/SAMUEL A GEBREMARIAM/Primary Examiner, Art Unit 2811
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