DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 21 January 2025 have been fully considered but they are not persuasive. Applicant argues that Song in view of Ando does not teach the limitation of “a thickness of the first gate oxide layer is greater than a thickness of the first high-k dielectric layer” citing several passages in Ando that allegedly proves that a person of ordinary skill would not be motivated to modify the ratio of the thickness between the first gate oxide layer and the first high-k dielectric layer. The examiner respectfully disagrees.
First, there is no passage in Song that teaches away from modifying the thickness of the first gate oxide layer and/or the first high-k dielectric layer. Hence, any dimensional changes to the first high-k dielectric layer, as suggested by Ando in ¶ [0031], and which would naturally result to a change in the relative dimensions between the high-k dielectric layer and the first gate oxide layer, would not render the device of Song inoperable.
Second, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See also MPEP § 2144.04 (IV) (A).
In summary, this application is not in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 9, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2020/0365733 A1) in view of Ando (US 2013/0009257 A1).
Regarding claim 1, Song teaches the semiconductor structure (Figs. 1-9, Abstract, [0010]-[0019]), comprising:
a semiconductor substrate (Fig. 4a, [0029]: 10&11) comprising a first active structure (Figs. 1 & 4a, [0030]: 15; Fig. 4a shows the active region 15 of first gate structure GS2);
a first gate structure (Fig. 4a, [0049]: GS2) disposed on the first active structure (Fig. 4a shows GS2 on top of 15), wherein the first gate structure comprises:
a first gate oxide layer (Figs. 4a-4b, [0049]: 34; also [0106]: 34 made of silicon oxide, etc.), wherein the first gate oxide layer comprises a U-shaped structure (Figs. 4a-4b shows 34 comprising of a U-shaped structure) in a cross-sectional view ([0013]-[0014]: Figs. 4a-4b are cross-sectional views) of the first gate structure (Figs. 4a-4b are cross-sectional views of GS2); and
a first high dielectric constant (high-k) dielectric layer (Figs. 4a-4b, [0049]: 36; also [0051]: 36 made of hafnium oxide, a high-k material listed in Applicant Specification [0018]; hence 36 is a first high-k dielectric layer) disposed on the first gate oxide layer (Figs. 4a-4b shows 36 on top of 34); and
a first spacer structure (Figs. 4a-4b, [0035]: SP1) disposed on a sidewall (vertical wall of GS2) of the first gate structure (Figs. 4a-4b and [0051] shows SP1 on disposed on vertical wall of GS2 ), wherein a first portion (vertical side wall of 34) of the first gate oxide layer is located between the first spacer structure and the first high-k dielectric layer in a horizontal direction (Figs 4a-4b: horizontal direction; Figs. 4a-4b shows vertical side wall of 34 is located between SP1 and 36 along the horizontal direction).
However, Song does not teach: a thickness of the first gate oxide layer is greater than a thickness of the first high-k dielectric layer.
Ando, in the same field of invention, teaches a semiconductor structure wherein the thickness of the first high-k dielectric layer can be adjusted to be thinner (¶ 0031). Hence, Song in view of Ando teaches: a thickness of the first gate oxide layer is greater than a thickness of the first high-k dielectric layer.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Ando into the device of Song to make the thickness of the first gate oxide layer to be greater than a thickness of the first high-k dielectric layer. The ordinary artisan would have been motivated to modify Song in the manner set forth above for at least the purpose of adjusting the thickness of the oxide layers surrounding the gate of a transistor to suit to the dimensional requirements of a preferred embodiment (Ando ¶ 0031).
Furthermore, in Gardner v. TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984), the Federal Circuit held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. See also MPEP § 2144.04 (IV) (A
Regarding claim 2, the semiconductor structure according to claim 1, wherein the first portion of the first gate oxide layer is sandwiched between the first high-k dielectric layer and the first spacer structure in the horizontal direction (Song Figs. 4a-4b shows the vertical side wall of 34 is between 36 and SP1 along the horizontal direction).
Regarding claim 3, the semiconductor structure according to claim 2, wherein the first portion of the first gate oxide layer is directly connected with the first high-k dielectric layer and the first spacer structure in the horizontal direction (Song Figs. 4a-4b shows vertical side wall 34 is directly connected with 36 and SP1, i.e., there are no intervening structures, between any of these three elements along the horizontal direction).
Regarding claim 9, the semiconductor structure according to claim 1, wherein the first gate structure further comprises:
a gate electrode (Song Figs. 4a-4b, [0049]: 38) disposed on the first high-k dielectric layer (38 is on 36), wherein the first high-k dielectric encompasses at least a part (vertical and horizontal surfaces of 38 surrounded by 36) of the gate electrode (Song Figs. 4a-4b show 36 surrounding the vertical and horizontal surfaces of 38).
Regarding claim 11, the semiconductor structure according to claim 1, wherein a top surface (Song Fig. 4b: top surface of the vertical wall of 34) of the first portion of the first gate oxide layer is lower than a top surface (Song Fig. 4b: top surface of SP1) of the first spacer structure in a vertical direction (Song Fig. 4b: vertical direction; Fig. 4b shows the top surface of the vertical wall of 34 is lower than the top surface of SP1 along the vertical direction).
Regarding claim 13, the semiconductor structure according to claim 1, wherein the first active structure comprises a fin-shaped semiconductor structure (Song [0030]: “active region 15 may be a fin-type active region”)
Claim(s) 4-6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2020/0365733 A1) Ando (US 2013/0009257 A1) as applied to claim 1 above, and further in view of Wang (US 2016/0225872 A1).
Regarding claim 4, Song in view of Ando teaches the semiconductor structure according to the semiconductor structure according to claim 1, wherein the first gate structure further comprises:
a second gate layer (Song Figs. 4a-4b,[0050]: 32; made of SiC), wherein the first gate oxide layer is disposed on the second gate layer (Song Figs. 4a-4b show 34 is on top of 32), and a second portion (Song Figs. 4a-4b: horizontal portion of 34) of the first gate oxide layer is sandwiched between the first high-k dielectric layer and the second gate oxide layer in a vertical direction (Song Figs. 4a-4b: vertical direction; these figures show the horizontal portion of 34 is sandwiched between 36 and 32 in along the vertical direction).
However, Song in view of Ando does not teach the material of the second gate layer to be an oxide.
Wang, in the same field of invention, teaches a semiconductor structure with a second gate layer (Fig. 10, [0014]: 14; 14 is analogous to the second gate layer of Song since a first gate oxide layer 16 is on top of 14, with the first gate oxide layer wedged between 14 and a first high-k dielectric layer 120; see also [0023]) made of oxide ([0016]: “the first gate oxide 14 has a chemical formula of SiAOB”).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wang into the device of Song in view of Ando to use an oxide material in a second gate layer in a semiconductor structure at least comprising of a gate structure having the second gate layer, a first gate oxide layer disposed on the second gate layer and sandwiched in between the second gate layer and a first high-k dielectric layer. The ordinary artisan would have been motivated to modify Song in view of Ando in the manner set forth above for at least the purpose of using thermal oxidation process of forming the oxide material of the second gate layer (see Wang’s Abstract) as means to prevent pinholes (Wang [0024]) and for the further purpose of improving the quality of the device (Wang [0005]).
Regarding claim 5, the semiconductor structure according to claim 4, wherein the second portion of the first gate oxide layer is directly connected with the first high-k dielectric layer and the second gate oxide layer (Song Figs. 4a-4b shows the horizontal portion of 34 is directly connected with 36 and 32).
Regarding claim 6, the semiconductor structure according to claim 4, further comprising:
a second gate structure (Song Fig. 1, [0028]: shows a plurality of gate structures GS), wherein the semiconductor substrate further comprises a second active structure (Song Fig. 1, [0028]: shows a plurality of active structures 15), the second gate structure is disposed on the second active structure (Song Figs. 4a-4b shows GS2 disposed on 15, with Figs. 4a-4b representing another gate structure and active region different from the one in claim 1 rejection), and the second gate structure comprises:
a third gate oxide layer (Figs. 4a-4b, [0051]: 34&32; see also [0106]: 34 made of silicon oxide ); and
a second high-k dielectric layer (Figs. 4a-4b, [0049]: 36) disposed on the third gate oxide layer (Figs. 4a-4b show 36 disposed on top of 34&32), wherein the third gate oxide layer is directly connected with the second active structure and the second high-k dielectric layer (Figs. 4a-4b show 34&32 directly connected to 15 and 36).
Regarding claim 8, the semiconductor structure according to claim 6, further comprising:
a second spacer structure (Song Figs. 4a-4b, [0035]: SP1; this is the SP1 of the second gate structure in claim 6) disposed on a sidewall (Figs. 4a-4b: vertical sidewall of GS2) of the second gate structure,
wherein the second high-k dielectric layer is directly connected with the second spacer structure (Figs. 4a-4b show 36 directly connected with SP1).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2020/0365733 A1) in view of Ando (US 2013/0009257 A1) and Wang (US 2016/0225872 A1) as applied to claim 6 above, and further in view of Liang (US 2014/0183642 A1).
Regarding claim 7, Song in view of Ando and Liang teaches the semiconductor structure according to claim 6, but does not teach wherein a thickness of the third gate oxide layer in a vertical direction is less than a total thickness of the first gate oxide layer and the second gate oxide layer in the vertical direction.
Liang, in the same field of invention, teaches a semiconductor structure (Fig. 11, Abstract) wherein
a thickness (vertical thickness of left 192) of the third gate oxide layer (Fig. 11, [0030]: left 192; left 192 is analogous to a third gate oxide layer since it directly connected to the active layer, which is the fin of 110, and a high-k dielectric layer 194, and with the left 192 in between these two elements; see also [0015] and [0023]; also, [0028]: buffer layer 192 is formed by thermal oxide process; hence it is a third gate oxide layer)
in a vertical direction (vertical direction of Fig. 11) is less than
a total thickness (total vertical thickness of right 192 and 122a) of the first gate oxide layer (Fig. 11, [0030]: right 192; this is analogous to the first gate oxide layer since it is a U-shaped layer in a cross-sectional view of the gate structure G2; see also Figs. 1-10 and [0015]-[0029]) and the second gate oxide layer (Fig. 11, [0017], [0029]: 122a; this is analogous to the second gate oxide layer since the first gate oxide layer is disposed on it, with the first gate oxide layer sandwiched between it and a high-k dielectric layer 194; [0027]: 122a is an oxide)
in the vertical direction (Fig. 11 shows the vertical thickness of the left 192 is less than the total vertical thickness of the right 192 and 122a).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Liang into the device of Song in view of Wang to provide a vertical thickness of a third gate oxide layer to be less than a total vertical thickness of a first gate oxide layer and a second gate oxide layer in a semiconductor structure at least comprising of a first gate structure that at least comprised of the first gate oxide layer and the second gate oxide layer and a second gate structure at least comprised of the third gate oxide layer. The ordinary artisan would have been motivated to modify Song in view of Wang in the manner set forth above for at least the purpose of using different spacer thicknesses to enable epitaxial structures formed in the substrate of the semiconductor structure to have different spacing in the gate channel length direction, thereby electrical performances of transistors with different requirements and standards, in different circuit areas, can be improved (Liang [0031]) and for the further purpose of preventing damage by a cleaning solution and for making these structures closer to the gate, so as to control the stresses in the gate channel (Liang [0032]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Song (US 2020/0365733 A1) in view of Ando (US 2013/0009257 A1), as applied to claim 9 above, and further in view of Huang (US 2022/0271148 A1).
Regarding claim 10, Song in view of Ando teaches the semiconductor structure according to claim 9, but does not teach wherein a top surface of the first portion of the first gate oxide layer is lower than a top surface of the gate electrode and higher than a bottom surface of the gate electrode in a vertical direction.
Huang, in the same field of invention, teaches a semiconductor structure wherein a top surface (Fig. 8I: top surface of 152) of the first portion (vertical sidewall of 152) of the a gate oxide layer (Fig. 8I, [0104]; 152) is lower than a top surface (Fig. 8I: top surface of 170&160&158) of the gate electrode (Fig. 8I, [0081], [0073], [0067]: 170&160&158) and higher than a bottom surface (Fig. 8I: bottom surface of 170&160&158) of the gate electrode in a vertical direction (Fig. 8I shows the top surface of 152 is lower than the top of top surface of 170&160&158 and higher than the bottom surface of 170&160&158).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the device of Song in view of Ando to place a top surface of a first gate oxide layer lower than a top surface a gate electrode and higher than the bottom surface of the gate electrode in a semiconductor structure at least comprising of a first gate structure comprising of the gate electrode disposed on a first high-k dielectric layer, wherein the first high-k dielectric layer encompasses at least part of the gate electrode. The ordinary artisan would have been motivated to modify Song in view of Ando in the manner set forth above for at least the purpose of designing gate-all-around (GAA) finFET transistor structures (see Huang Fig. 1K and Figs. 8A-8I and [0020], [0099]-[0108]) that require double patterning or multi-patterning techniques to obtain smaller pitches (Huang [0020]), such as the gate electrode shown in Fig. 8I (Huang [0108]) for the further motivation of increasing device density, higher performance, and lower costs of three-dimensional transistor designs (Huang [0003]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899