Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The amendment filed on 06/25/2025, responding to the Office action mailed on 05/13/2025 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-12 and 21-24.
Response to Amendment
Applicant’s amendments to Claim 1 has overcome all claim rejections under 35 U.S.C. § 103 previously set forth in the Non-Final Office action mailed on 05/13/2025. Accordingly, all previous claim rejections under 35 U.S.C. § 103 have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-4, 12, 21 and 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The claim amendments added into claim 1 necessitated an updated search and a new prior art Kim et al. (US 20220122977 A1; hereinafter “Kim’77”) has been found. Claims 1, 3-4, 12, 21 and 22 are unpatentable over Kim’77 as modified by Brewer as described below.
Specification
The abstract of the disclosure is objected to for three reasons:
(1) the abstract has implied language. For example, the abstract begins with “Aspects of the present disclosure provide a semiconductor structure. For example, the semiconductor structure can include…”. It is suggested to be changed as “A semiconductor structure includes…”.
(2) Furthermore, abstract has more than one paragraph and the second paragraph has two incomplete sentences.
(3) Abstract contains more than 150 words.
MPEP § 608.01(b) provides guidance regarding the language of the abstract.
A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 12, 21 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20220122977 A1; hereinafter “Kim’77”) in view of Brewer et al. (US 11094699 B1; hereinafter “Brewer”)
In re claim 1, Kim’77 discloses a method for fabricating a semiconductor structure (figs. 4-18), comprising:
forming over a substrate 11 a lower stack of alternating semiconductor and dielectric layers (e.g., two of the lower layers 22, 21. Hereinafter “Lower_Stack”) that are parallel to a top surface of the substrate (¶42; figs. 4A-4B);
forming an upper stack of alternating semiconductor and dielectric layers (e.g., two of the upper layers 22, 21. Hereinafter “Upper_Stack”) that are parallel to the top surface of the substrate,
the upper stack Upper_Stack vertically stacked over the lower stack Lower_Stack;
forming a first opening 23 through the upper stack and the lower stack until uncovering a top surface of the substrate 11 (¶43; fig. 5B); and
forming within the first opening a lower transistor (e.g., a lower transistor comprising gate structure 31, 32, active layer 22M, source and drain 25, 35. Hereinafter “Lower_Tran”) (¶45, 52-57) that is insulated from the substrate 11 (e.g., insulated by the lower dielectric layer 21) and an upper transistor (e.g., a upper transistor comprising gate structure 31, 32, active layer 22M, source and drain 25, 35. Hereinafter “Upper_Tran”) that is vertically stacked over the lower transistor (figs. 6-15),
wherein the lower transistor Lower_Tran includes a lower channel 22M that is elongated horizontally and is in-plane with a first lower metal layer 36 of the lower stack (fig. 16) (¶58),
the lower transistor Lower_Tran is electrically connected to a lower metal capacitor (a lower metal capacitor formed by storage node 36, dielectric 38 and plate node 39. Hereinafter “Cap1”) that includes the first lower metal layer 36 as a first lower metal plate (e.g., lower metal layer 36. Hereinafter “Cap1_Plate1”) and a second lower metal layer 39 of the lower stack as a second lower metal plate (e.g., portion of the plate node 39 facing the first lower metal layer 36. Hereinafter “Cap1_Plate2”) (figs. 17-18; ¶58-60),
the upper transistor Upper_Tran includes an upper channel 22M that is elongated horizontally and is in-plane with a first upper metal layer 36 of the upper stack,
the upper transistor Upper_Tran is electrically connected to an upper metal capacitor that includes the first upper metal layer 36 as a first upper metal plate (e.g., lower metal layer 36. Hereinafter “Cap2_Plate1”) and a second upper metal layer (e.g., portion of the plate node 39 facing the first upper metal layer 36. Hereinafter “Cap2_Plate2”) of the upper stack as a second upper metal plate (figs. 17-18; ¶58-60), and
the second lower metal plate Cap1_Plate2 is electrically connected to the second upper metal plate Cap2_Plate2, or
the second lower metal plate has one end separated from the lower transistor by a lower insulating layer, and the second upper metal plate has one end separated from the upper transistor by an upper insulating layer.
Kim’77 does not expressly disclose forming the initial lower stack and upper stack from alternating metal layer and dielectric layer.
In the same field of endeavor, Brewer discloses a method for fabricating a semiconductor structure (figs. 1-7) wherein forming an initial lower stack and upper stack from alternating metal layer 106 and dielectric layer 104 (C. 6, L. 25-45).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Brewer into the method of Kim’77 and form the initial stack from alternating metal and dielectric layers to reduce number of process steps and save fabrication cost.
Furthermore, the selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946); In re Gibson, 39 F.2d 975, 5 USPQ 230 (CCPA 1930). See MPEP § 2144.04.
In re claim 3, Kim’77, as modified by Brewer, discloses the method of claim 1.
Kim’77 further discloses (figs. 4-18) wherein the lower transistor Lower_Tran further includes a lower gate region 31, 32 that surrounds the lower channel 22M (e.g., gate region 31, 32 surrounds channel 22M from inside), and the upper transistor Upper_Tran further includes an upper gate region 31, 32 that surrounds the upper channel 22M.
In re claim 4, Kim’77, as modified by Brewer, discloses the method of claim 3.
Kim’77 further discloses (figs. 4-18) wherein the upper gate region 31, 32 is electrically connected to the lower gate region 31, 32.
In re claim 12, Kim’77, as modified by Brewer, discloses the method of claim 1, wherein the lower transistor Lower_Tran is narrower than the lower metal capacitor Cap1 horizontally (see fig. 18B of Kim’77).
In re claim 21, Kim’77, as modified by Brewer, discloses the method of claim 1, wherein the second lower metal plate (Kim’77: Cap1_Plate2) is electrically connected to the second upper metal plate (Kim’77: Cap2_Plate2).
In re claim 22, Kim’77, as modified by Brewer, discloses the method of claim 1.
Kim’77 discloses in figs. 4-18, wherein the second lower metal plate Cap1_Plate2 has one end separated from the lower transistor Lower_Tran by a lower insulating layer 38, and the second upper metal plate Cap2_Plate2 has one end separated from the upper transistor Upper_Tran by an upper insulating layer 38.
Allowable Subject Matter
Claims 23-24 are allowed.
Claims 2, 5-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Closest prior art of record, alone or in combination, does not expressly disclose the method steps cited in claim 2 to make the capacitor stacks, in combination with the method steps cited in claim 1.
Closest prior art of record, alone or in combination, does not expressly disclose the method steps cited in claim 5 to make the transistor stacks, in combination with the method steps cited in claims 1, 3-4.
New independent claims 23 and 24 are original claims 2 and 5, respectively written in independent form. Therefore, same reason for allowance for claims 23 and 24 as cited above for claims 2 and 5.
Regarding claim 11, Kim’77, as modified by Brewer, discloses the method of claim 3.
Kim’77 further discloses (figs. 4-18) wherein
the lower metal capacitor further includes a lower dielectric layer DL of the lower stack that is between to the first lower metal plate EL1 and the second lower metal plate EL2 and is in-plane with the lower gate region GI, CL2 of the lower transistor (“Lower_FET”), and
the upper metal capacitor further includes an upper dielectric layer 38 of the upper stack that is between the first upper metal plate Cap2_Plate1 and the second upper metal plate Cap2_Plate2
However, closest prior art of record, alone or in combination, does not expressly disclose the upper metal capacitor further includes an upper dielectric layer of the upper stack that is between the first upper metal plate and the second upper metal plate and is in- plane with the upper gate region of the upper transistor, in combination with other limitations cited in claims 1 and 3.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
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/NILUFA RAHIM/Primary Examiner, Art Unit 2893