DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Amendments to claims 1, 4, 6, 7, 10, 11, 16, and 17 submitted on 8 July 2026 are acknowledged. Claims 12 and 15 were previously cancelled.
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 11 June 2026 has been considered by the examiner and made of record in the application file.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-11, 13-14, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jiang et al (US 20230018716 A1, hereinafter “Jiang”).
Regarding Claim 1 – Jiang discloses a semiconductor device, comprising: a substrate (10 [0085]); a plurality of capacitors (1112 [0063] and Fig. 6) disposed on the substrate, wherein the capacitors are disposed along a vertical direction (as shown by 1112 in Fig. 7, vertical considered to be the Z-direction), each of the capacitors extends along a first horizontal direction (X annotated Fig. 6 [0058]), each of the plurality of capacitors comprises a first capacitor electrode (Combination of 26 and 1112a [0115] and Fig. 19), a second capacitor electrode (1112c [0115] and Fig. 19), and a capacitor dielectric (1112b [0115] and Fig. 19) separating the first capacitor electrode from the second capacitor electrode (Fig. 19), and a first supporting layer (50 [0106], Sup1 annotated Jiang Fig. 6)) disposed on the substrate and extending along a second horizontal direction (Y annotated Fig. 6 [0058]) different from the first horizontal direction, wherein the capacitor dielectric comprises a first surface (S1 annotated Fig. 6) and a second surface (S2 annotated Fig. 6) which are disposed on two opposite sides of the capacitor dielectric along the first horizontal direction, the first surface of the capacitor dielectric is coupled with the first capacitor electrode (surface of 1112b coupled with 1112a, annotated Fig. 24), the first supporting layer is disposed between the first surface and the second surface of the capacitor dielectric (Fig. 6), the first supporting layer surrounds the first capacitor electrode (Fig. 19), the capacitors are disposed along the vertical direction (as shown by 1112 in Fig. 7, vertical considered to be the Z-direction).
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Regarding Claim 2 – Jiang further discloses the semiconductor device of claim 1, wherein the first capacitor electrode of the plurality of capacitors is spaced apart from the substrate (See annotated Fig. 24).
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Regarding Claim 3 – Jiang further discloses the semiconductor device of claim 1, wherein the first supporting layer is in contact with the substrate (50 at cross section D-D (Sup1) of Fig. 6 [0080] in Fig. 14 [0106]).
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Regarding Claim 4 – Jiang further discloses the semiconductor device of claim 3, further comprising: a second supporting layer spaced apart from the first supporting layer and extending along the second horizontal direction (Sup2, annotated Fig. 6), wherein the second supporting layer is in contact with the substrate (similar to 50 in D-D of Fig. 14 [0106]).
Regarding Claim 5 – Jiang further discloses the semiconductor device of claim 3, further comprising: a transistor (1111 [0060] and Fig. 5) electrically connected to one of the plurality of capacitors; and an interconnection trace (Interconnection Trace, annotated Fig. 5) disposed between the transistor and the one of the plurality of capacitors.
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Regarding Claim 6 – Jiang further discloses the semiconductor device of claim 5, wherein the interconnection trace and the first capacitor electrode of the one of the plurality of capacitors are in contact along the first horizontal direction (Fig. 5 [0084]).
Regarding Claim 7 – Jiang further discloses the semiconductor device of claim 5, wherein the interconnection trace extends along the first horizontal direction (X, Fig. 5 [0058]), and the transistor comprises a word line extending along a third direction (Z, annotated Fig. 24 [0127]) different from the first horizontal direction and the second horizontal direction.
Regarding Claim 9 – Jiang further discloses the semiconductor device of claim 7, wherein the word line (layer 140 portion, Fig. 24 [0112]) is in contact with the substrate (as shown in Fig. 24).
Regarding Claim 10 – Jiang further discloses the semiconductor device of claim 1, further comprising: a plurality of isolation layers (60 [0108] and Fig. 17) each of which extends along the first horizontal direction, and the plurality of isolation layers and the first capacitor electrode of the plurality of capacitors have a staggered arrangement (Fig. 24 [0125-0127]).
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Regarding Claim 11 – Jiang discloses a semiconductor device, comprising: a substrate having an upper surface (10 [0085]); and a plurality of capacitors (1112 [0063] and Fig. 6) disposed on the upper surface of the substrate (Fig. 24 [0060]), wherein the plurality of capacitors are arranged along a plane (in the Z-direction of annotated Fig. 24) that is substantially perpendicular to the upper surface of the substrate, and each of the capacitors comprises a first capacitor electrode (Combination of 26 and 1112a [0115] and Fig. 19) extending along a first direction (X Fig. 5 [0058]); and a supporting layer (50 [0106], Sup1 annotated Jiang Fig. 6) disposed on the upper surface of the substrate, wherein the supporting layer extends along a second direction (Y annotated Fig. 6 [0058]) different from the first direction and connects the plurality of capacitors (Fig. 6 [0063]), the first supporting layer surrounds the first capacitor electrode (Fig. 19), and the supporting layer and the first electrodes of the plurality of capacitors are alternately arranged along the plane (as shown by alternating layers 26 and 50 in the Z-direction in cross section E-E in Figs. 14 and 24).
Regarding Claim 13 – Jiang further discloses the semiconductor device of claim 11, wherein each of the capacitors comprises a capacitor dielectric (1112b [0115] and Fig. 19) enclosing the first capacitor electrode along the first direction (X Fig. 5 [0058]).
Regarding Claim 14 – Jiang further discloses the semiconductor device of claim 11, wherein each of the capacitors comprises a second capacitor electrode (1112c [0115] and Fig. 19) enclosing the first capacitor electrode along the first direction (X Fig. 5).
Regarding Claim 16 – Jiang further discloses the semiconductor device of claim 11, wherein the supporting layer is in contact with the substrate (as shown by cross section D-D from Fig. 6 in Fig. 14), and the substrate comprises a semiconductor material ([0085]).
Regarding Claim 17 – Jiang further discloses the semiconductor device of claim 11, further comprising: an interconnection trace (Interconnection Trace annotated Fig. 5) configured to connect one of the plurality of capacitors and a transistor, wherein the interconnection trace extends along the first direction (X Fig. 5 [0058]).
Regarding Claim 18 – Jiang further discloses the semiconductor device of claim 17, wherein the interconnection trace and the first capacitor electrode of the one of the plurality of capacitors are
Regarding Claim 19 – Jiang further discloses the semiconductor device of claim 17, further comprising: a word line extending along a third direction (Z, annotated Fig. 24) different from the first direction and the second direction; and a gate dielectric (80 [0112] and Fig. 24) separating the word line and the interconnection trace.
Regarding Claim 20 – Jiang further discloses the semiconductor device of claim 19, further comprising: a bit line (121 [0065] and Fig. 24), wherein the word line (marked by 160 in Figs. 5, 6, and 24 [0127]) is disposed between the one of the plurality of capacitors and the bit line (contained in 120 Figs. 5 and 6 [0065]) along the first direction (Figs. 5 and 6 [0058]); and wherein the word line (140 [0112] and Fig. 24) extends into the substrate (Fig. 24 [0112]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al (US 20230018716 A1, hereinafter “Jiang”), in view of Shao et al (US 20230016558 A1, hereinafter “Shao”).
Regarding Claim 8 – Jiang further discloses the semiconductor device of claim 7, wherein the transistor comprises a channel layer (channel region [0110] and denoted by transistor 1111 in Fig. 5) spaced apart from the first capacitor electrode of the one of the plurality of capacitors by the word line (Fig. 5 [0084]).
Jiang fails to expressly disclose a material of the channel layer is different from a material of the first capacitor electrode of the one of the capacitors.
However, Shao discloses a material of the channel layer (semiconductor layer 202 [0062]) is different from a material of the first capacitor electrode of the one of the capacitors (metal nitride or metal silicide [0071]).
Shao is analogous to Jiang in the area of stacked capacitor structures for DRAM. Shao teaches using a semiconductor material for the channel to enable the formation of a transistor and word line control of its gate (Shao [0062]). Shao further teaches using metal nitride or silicide in the capacitor electrodes to reduce the electrode resistance, thereby reducing power consumption ([0085-0086]). Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to make the material of the channel layer different from the first capacitor electrode for the benefits of word line control and reduced power consumption.
Response to Arguments
The applicant argues that Jiang does not show the support structure 50 between the first electrodes in the vertical directions. The examiner respectfully disagrees. As can be seen in Figures 14 and 24, layers 26 and 50 (labeled only in Fig. 14) alternate in a plane perpendicular to the surface of the substrate (cross section E-E), as described in Claim 11, and shown above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON MCDONALD whose telephone number is (571) 272-5944. The examiner can normally be reached M-F 8a-6p Eastern, alternating Fridays out of office.
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/JASON MCDONALD/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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