Attorney’s Docket Number: 5481/1003PUS1
Filing Date: 10/26/2022
Inventor: Yang
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed on 04/23/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendments filed on 4/23/2026, responding to the Office action mailed 3/09/2026, has been
entered. Applicant amended claims 1 and 12. The present Office action is made with all the suggested
amendments being fully considered.
Response to Amendments/Arguments
Applicant’s amendments have overcome the claim objections and claim rejections of 35 U.S.C. 112 and 35 U.S.C. 103 as previously formulated in the Non-Final Office actioned mailed on 3/09/2026. Accordingly, the claim objections and rejections of 35 U.S.C. 112 and 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 1-20. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung (US 20110062577 A1) in view of Lin (US 7514299 B2) further in view of Chen (US 20080105974 A1)
Regarding claim 1, Hung (see, e.g., fig. 4) shows most aspects of the instant invention including a package structure comprising:
a substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310, a first trace 320 + second trace 330…”) including a patterned circuit layer (e.g., first trace 320 + second trace 330) and defining a through hole (e.g., central slot 313), wherein the patterned circuit layer (e.g., first trace 320 + second trace 330) on a cross-sectional plane (e.g., the cross-sectional view of fig. 4) comprises a first extending portion (e.g., suspended inner lead 321 extension) extending along a sidewall of the through hole (e.g., central slot 313); and the patterned circuit layer (e.g., first trace 320 + second trace 330) comprises a first main portion (e.g., first trace 320 contacting first board part 314) coupled to the first extending portion (e.g., suspended inner lead 321 extension) disposed on and contacted with the substrate (e.g., first board part 314 of substrate 300, see annotated fig. 1 below) and;
an electronic component (e.g., chip 10) having an active surface (e.g., active surface 11) over the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300), wherein the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) is electrically connected to the patterned circuit layer (e.g., first trace 320 + second trace 330) of the substrate (e.g., first board part 314 + second board part 315) through a contacting end (e.g., contact surface between first trace extension 321 and chip 10) of the first extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320 + second trace 330) in the through hole (e.g., central slot 313);
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Annotated Fig. 1
Hung (see, e.g., fig. 4), however, fails to explicitly show on a same cross-sectional plane a second extending portion extending along a sidewall of the through hole with a contacting end, wherein the contacting end of the first extending portion and the contacting end of the second extending portion are disposed at a same vertical level, while it also fails to explicitly show wherein a length of the first extending portion of the patterned circuit layer is less than one half of a width of the through hole of the substrate, and a length of the second extending portion of the patterned circuit layer is less than one half of the width of the through hole of the substrate.
Lin (see, fig. 2), in a similar device to Hung, teaches a second extending portion (e.g., left-side bonding wire 230 portion extending between the substrate 210) extending along a sidewall of a through hole (e.g., through hole 216), and a second main portion (e.g., bonding wire 230 in contact with substrate 210) coupled to the second extending portion (e.g., left-side bonding wire 230 portion extending between the substrate 210) disposed on and contacting a substrate (e.g., left-side circuit substrate 210), wherein contacting ends (e.g., end portions of bonding wires) are disposed at a same vertical level.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the mirrored/symmetric wire-substrate configuration of Lin onto the left-side trace protruding onto the chip within the through hole of Hung, in order to achieve the expected result of providing electrical connection between the chip and left-side board part. Note that the added extending portion’s contacting end would also contact the chip at the same height as the contacting end of the first extending portion, hence they share the same vertical level and are disposed on the same cross-sectional plane (e.g., the cross-sectional view of fig. 4 of Hung).
In addition, it also would have been obvious to one of ordinary skill in the art to duplicate the first extending portion (protruding out of the right trace) and its bonding pad, to protrude out of the left trace, in order to provide electrical connection between the chip and the terminals/second board part, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. Note that this duplicated extending portion (hereinafter duplicated second extending portion) would also contact the chip at the same vertical level as the first extending portion with its contacting end, since the duplicated extending portion has identical characteristics and is therefore making contact with the same chip surface as the first extending portion. Note that since the trace is duplicated exactly on the left-side, they would be equivalent on the same cross-sectional plane (e.g., the cross-sectional view of fig. 4 of Hung) in regards to vertical level.
Hung in view of Lin, however, fails to explicitly teach wherein a length of the first extending portion of the patterned circuit layer is less than one half of a width of the through hole of the substrate, and a length of the second extending portion of the patterned circuit layer is less than one half of the width of the through hole of the substrate.
Chen (see, e.g., fig. 2), in a similar device to Hung in view of Lin, teaches a first extending portion (e.g., right-side bonding wire 140) extends through a depth of a through hole (e.g., window opening 110c) and a second extending portion (e.g., left-side bonding wire 140) extends through a depth of a through hole (e.g., window opening 110c), wherein both the first extending portion (e.g., right-side bonding wire 140) and the second extending portion (e.g., left-side bonding wire 140) are disposed on an edge of a chip (e.g., chip 120).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chip-edge connectivity arrangement/configuration of Chen within the device of Hung in view of Lin, in order to achieve the expected result of both reducing the amount of wire material required to reach the chip pads (note that Chen also shows wire-bonding pads 121 on the edge of the chip), and diversifying the connection location on the chip, as the exact location of the bonding pads/wires becomes a design choice based on the layout and connectivity requirements. Note that the chip-pad connection located on the edge of the chip shortens the exact distance/length required for the bonding wire to make contact and perform the expected result of providing connectivity between the substrate and the chip. In addition, note that the length of the wire that sticks out (so as to contact the pad when folded) depends on the depth of the through hole (thickness of the substrate) and the relative position of the pad to the edge of the through hole. So, since Hung already recognizes the length of the wire that sticks out as a result effective variable for enabling connectivity to the pad and implementing a functional package, the particular length claimed is an optimization of that length to adapt to the thickness of the substrate or position of the receiving pad, and no new or non-obvious results arise from that particular length limitation, other than enabling a conductive path from the back side BGA to the pad on the chip, which is already suggested by Hung.
Regarding claim 2, Hung (see, e.g., fig. 4) shows the substrate (e.g., substrate 300) has a first surface (e.g., top surface of first board part 314) and a second surface (e.g., bottom surface of first board part 314) opposite to the first surface (e.g., top surface of first board part 314), the electronic component (e.g., chip 10) is over first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300).
Regarding claim 3, Hung (see, e.g., fig. 4) shows the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) has a first portion (e.g., portion of active surface 11 between first board part 314 and second board part 315) and a second portion (e.g., portion of active surface 11 directly in contact with elastomer 350), the first portion (e.g., portion of active surface 11 between first board part 314 and second board part 315) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) is exposed in the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300), and the second portion (e.g., portion of active surface 11 directly in contact with elastomer 350) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) is adhered to the first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300) through an adhesion layer (e.g., elastomer 350 + paragraph 31 “…elastomer 350 can be chosen from flexible b-stage paste…”); and the second portion (e.g., portion of active surface 11 directly in contact with elastomer 350) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10) surrounds the first portion (e.g., portion of active surface 11 between first board part 314 and second board part 315) of the active surface (e.g., active surface 11) of the electronic component (e.g., chip 10).
Regarding claim 4, Hung (see, e.g., fig. 4) shows the patterned circuit layer (e.g., first trace 320 + second trace 330) is coupled with the second surface (e.g., bottom surface of first board part 314) of the substrate (e.g., substrate 300).
Regarding claim 5, Hung (see, e.g., fig. 4) in view of Lin teaches the electronic component (e.g., chip 10) includes bump (e.g., bonding pad 12 + added bonding pad 7 on added second extending portion 11) disposed adjacent to the active surface (e.g., active surface 11) thereof, and the first extending portion (e.g., suspended inner lead 321 extension) and the second extending portion (e.g., extended portion of second portion added via Lin/duplication) of the patterned circuit layer (e.g., first trace 320 + second trace 330) are respectively connected to bumps (e.g., bonding pad 12 + added bonding pad on added second extending portion) of the electronic component (e.g., chip 10).
Regarding claim 6, Hung (see, e.g., fig. 4) in view of Lin teaches a package body (e.g., encapsulant 40) disposed in the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300) and encapsulating the first extending portion (e.g., suspended inner lead 321 extension) and the second extending portion (e.g., extending portion of second portion added via Lin/duplication) of the patterned circuit layer (e.g., first trace 320 + second trace 330), wherein the package body (e.g., encapsulant 40) is further disposed on the first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300) and encapsulating the electronic component (e.g., chip 10).
Regarding claim 7, Hung (see, e.g., fig. 4) in view of Lin teaches the first extending portion (e.g., suspended inner lead 321 extension) and the second extending portion (e.g., extended portion of second portion added via Lin/duplication) of the patterned circuit layer (e.g., first trace 320 + second trace 330) and the patterned circuit layer (e.g., first trace 320 + second trace 330) are at the same layer (e.g., note that first part of the extension is at the same level of the first trace 320 + second trace 330 portion contacting the substrate, and that the second portion added via Lin/duplication comprises the same characteristics).
Regarding claim 8, Hung (see, e.g., fig. 4) in view of Lin teaches the first extending portion (e.g., suspended inner lead 321 extension) and the second extending portion (e.g., extended portion of second portion added via Lin/duplication) of the patterned circuit layer (e.g., first trace 320 + second trace 330) and the patterned circuit layer (e.g., first trace 320 + second trace 330) are formed integrally (see, e.g., paragraph 25 “The inner lead 321 integrally connects with the first trace 320 + second trace 330”).
Regarding claim 9, Hung (see, e.g., fig. 4) shows at least one external connector (e.g., external terminals 50) disposed on the patterned circuit layer (e.g., first trace 320 + second trace 330).
Regarding claim 11, Hung (see, e.g., fig. 4) shows a length of the first extending portion (e.g., suspended inner lead 321 extension) of the patterned circuit layer (e.g., first trace 320 + second trace 330) is greater than a thickness (e.g., note that the first trace 320 + second trace 330 extends from below the bottom surface of first board 314 above the top surface of first board 314, so the length of the first trace 320 + second trace 330 is greater than the first board 314’s thickness) of the substrate (e.g., substrate 300).
Regarding claim 12, Hung (see, e.g., fig. 4) shows most aspects of the instant invention including a package structure comprising:
A substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310” + figure 4 (note substrate core 310 includes first board part 314 and second board part 315)) including a patterned circuit layer (e.g., first trace 320 + second trace 330) and defining a through hole (e.g., central slot 313);
An electronic component (e.g., chip 10) disposed corresponding to the through hole (e.g., central slot 313) of the substrate (e.g., substrate 300), wherein the patterned circuit layer (e.g., first trace 320 + second trace 330) on a cross-sectional plane (e.g., cross-sectional view of fig. 4) comprises a first portion (e.g., suspended inner lead 321 extension) respectively bent (see, e.g., annotated fig. 2 below) to extend through the through hole (e.g., central slot 313), the patterned circuit layer (e.g., first trace 320 + second trace 330) comprises a first main portion (e.g., first trace 320 contacting first board part 314) respectively coupled to the first portion (e.g., suspended inner lead 321 extension) disposed on and contacted with the substrate (e.g., substrate 300), and contacting ends (e.g., contact surface between first trace extension 321 and chip 10) of the first portion (e.g., suspended inner lead 321 extension) to connect the electronic component (e.g., chip 10).
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Annotated Fig. 2
Hung (see, e.g., fig. 4), however, fails to explicitly show the patterned circuit layer, on a same cross-sectional plane, comprises a second portion respectively bent to extend through the through hole, the patterned circuit layer comprises a second main portion, respectively coupled to the second portion disposed on and contacted with the substrate, a contacting end of the second portion of the patterned circuit layer connects to the electronic component, wherein the contact end of the first portion and the contacting end of the second portion are disposed at a same vertical level, while it also fails to explicitly show wherein a length of the first portion of the patterned circuit layer is less than one half of a width of the through hole of the substrate, and a length of the second portion of the patterned circuit layer is less than one half of the width of the through hole of the substrate.
Lin (see, fig. 2), in a similar device to Hung, teaches a second portion (e.g., left-side bonding wire 230 portion extending between the substrate 210) respectively bent (see, e.g., bent portion of bonding wire 230 that extends upward after the bend) to extend through a through hole (e.g., gap between substrate 210 through which the wire extends), and a second main portion (e.g., bonding wire 230 in contact with substrate 210) coupled to the second portion (e.g., left-side bonding wire 230 portion extending between the substrate 210) disposed on and contacting a substrate (e.g., left-side circuit substrate 210), wherein contacting ends (e.g., end portions of bonding wires) are disposed at a same vertical level.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the mirrored/symmetric wire-substrate configuration of Lin onto the left-side trace protruding onto the chip within the through hole of Hung, in order to achieve the expected result of providing electrical connection between the chip and left-side board part. Note that the added portion’s contacting end would also contact the chip at the same height as the contacting end of the first portion, hence they share the same vertical level and are disposed on a same cross-sectional plane (e.g., the cross-sectional view of fig. 4 of Hung).
In addition, it also would have been obvious to one of ordinary skill in the art to duplicate the first portion (protruding out of the right trace) and its bonding pad, to protrude out of the left trace, in order to provide electrical connection between the chip and the terminals/second board part, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04. Note that this duplicated portion (hereinafter duplicated second portion) would also contact the chip at the same vertical level as the first portion with its contacting end, since the duplicated second portion has identical characteristics and is therefore making contact with the same chip surface as the first portion. Note that since the trace is duplicated exactly on the left-side, they would be equivalent on the same cross-sectional plane (e.g., the cross-sectional view of fig. 4 of Hung) in regards to vertical level.
Hung in view of Lin, however, fails to explicitly teach wherein a length of the first portion of the patterned circuit layer is less than one half of a width of the through hole of the substrate, and a length of the second portion of the patterned circuit layer is less than one half of the width of the through hole of the substrate.
Chen (see, e.g., fig. 2), in a similar device to Hung in view of Lin, teaches a first portion (e.g., right-side bonding wire 140) extends through a depth of a through hole (e.g., window opening 110c) and a second portion (e.g., left-side bonding wire 140) extends through a depth of a through hole (e.g., window opening 110c), wherein both the first portion (e.g., right-side bonding wire 140) and the second portion (e.g., left-side bonding wire 140) are disposed on an edge of a chip (e.g., chip 120).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the chip-edge connectivity arrangement/configuration of Chen within the device of Hung in view of Lin, in order to achieve the expected result of both reducing the amount of wire material required to reach the chip pads (note that Chen also shows wire-bonding pads 121 on the edge of the chip), and diversifying the connection location on the chip, as the exact location of the bonding pads/wires becomes a design choice based on the layout and connectivity requirements. Note that the chip-pad connection located on the edge of the chip shortens the exact distance/length required for the bonding wire to make contact and perform the expected result of providing connectivity between the substrate and the chip. In addition, note that the length of the wire that sticks out (so as to contact the pad when folded) depends on the depth of the through hole (thickness of the substrate) and the relative position of the pad to the edge of the through hole. So, since Hung already recognizes the length of the wire that sticks out as a result effective variable for enabling connectivity to the pad and implementing a functional package, the particular length claimed is an optimization of that length to adapt to the thickness of the substrate or position of the receiving pad, and no new or non-obvious results arise from that particular length limitation, other than enabling a conductive path from the back side BGA to the pad on the chip, which is already suggested by Hung.
Regarding claim 13, Hung (see, e.g., fig. 4) in view of Lin further in view of Chen teaches the electronic component (e.g., chip 10) is electrically connected to the patterned circuit layer (e.g., first trace 320 + second trace 330) using the bent first portion (see, e.g., annotated fig. 1 above) and the bent second portion (e.g., bent portion of second portion added via Lin/duplication) of the patterned circuit layer (e.g., first trace 320 + second trace 330).
Regarding claim 14, Hung (see, e.g., fig. 4) shows the substrate (e.g., substrate 300 + paragraph 24 “The substrate 300 primarily comprises a substrate core 310” + figure 4 (note substrate core 310 includes first board part 314 and second board part 315) + paragraph 31 “As shown in FIG 4. And FIG. 6 again, the substrate 300 further comprises a solder resist 340 formed on the bottom surface 312 of the substrate core 310 to cover the first trace 320 + second trace 330…”) has a first surface (e.g., top surface of first board part 314) and a second surface (e.g., bottom surface of solder resist 340) opposite to the first surface (e.g., top surface of first board part 314), the electronic component (e.g., chip 10) is over the first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300), the patterned circuit layer (e.g., first trace 320 + second trace 330) is disposed adjacent to the second surface (e.g., bottom surface of solder resist 340) of the substrate (e.g., substrate 300).
Regarding claim 15, Hung (see, e.g., fig. 4) shows the patterned circuit layer (e.g., first trace 320 + second trace 330) is coupled with the second surface (e.g., bottom surface of solder resist 340) of the substrate (e.g., substrate 300).
Regarding claim 16, Hung (see, e.g., fig. 4) shows the patterned circuit layer (e.g., first trace 320 + second trace 330) is embedded (see, e.g., paragraph 31 “As shown in FIG 4. And FIG. 6 again, the substrate 300 further comprises a solder resist 340 formed on the bottom surface 312 of the substrate core 310 to cover the first trace 320 + second trace 330…”) in the substrate (e.g., substrate 300).
Regarding claim 17, Hung (see, e.g., fig. 4) shows there is no direct electrical connection (note the elastomer 350 between chip 10 and substrate 300, see paragraph 31) between the electronic component (e.g., chip 10) and the first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300).
Regarding claim 18, Hung (see, e.g., fig. 4) shows there is no electrical connection between the first surface (e.g., top surface of first board part 314) of the substrate (e.g., substrate 300) and the second surface (e.g., bottom surface of solder resist 340 + paragraph 31 “The solder resist 340 can be…non-photo-sensitive dielectric materials… to provide surface isolation and protection to prevent the first trace 320 + second trace 330….from contamination which may lead to electrical short”) of the substrate (e.g., substrate 300).
Regarding claim 19, Hung (see, e.g., fig. 4) shows the substrate (e.g., substrate 300) includes
only one patterned circuit layer (e.g., first trace 320 + second trace 330).
Regarding claim 20, Hung (see, e.g., fig. 4) in view of Lin further in view of Chen teaches a package body (e.g., encapsulant 40) encapsulating the bent first portion (see, e.g., annotated fig. 1 above) and the bent second portion (e.g., bent portion of second portion added via Lin/duplication) of the patterned circuit layer (e.g., first trace 320 + second trace 330) and the electronic component (e.g., chip 10).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Hung in view Lin further in view of Chen and Li (US 20170103957 A1).
Regarding claim 10, Hung in view of Lin further in view of Chen fails to teach the patterned circuit layer is formed from a metal foil.
Li (see, e.g., fig. 1), in a similar device to Hung in view of Lin further in view of Chen, teaches a patterned circuit layer formed from a metal foil (see, e.g., paragraph 20 “The metal foil 108 is etched in a pattern to create metal traces…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to form the use the metal foil to metal trace formation methodology of Li within the device of Hung in view of Lin further in view of Chen, to achieve the expected result of providing conductive properties within the layer in order to allow the transfer of current as necessary between the electronic component and the substrate/external terminals.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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