DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7, and 8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho (US 2021/0375625).
Regarding claim 1, Cho discloses a fabrication method comprising: depositing a semiconductor material (Fig.4A, numeral 205; [0062]) onto a substrate (201); applying a hard mask layer; (206) applying a photoresist layer (207); performing lithography to form voids in the photoresist layer that form a pattern (Fig.4A; [0074]); applying the pattern to the hard mask layer based on the pattern in the photoresist layer (Fig.4B); etching the semiconductor material based on the pattern in the hard mask layer to form a cavity in the semiconductor material (Fig.4D, numeral 208); performing atomic layer deposition to deposit pillar material ([0079]) into the cavity (208), wherein the atomic layer deposition applies the pillar material to sidewalls of the cavity such that the pillar material accumulates inwardly from the sidewalls until the cavity is filled ([0079]); planarizing to remove the hard mask layer ([0079]) and pillar material disposed above a pillar height from a surface of the substrate ([0080]; Fig.4E); and removing the semiconductor material to release a pillar (Fig.4F, numeral 209) of the pillar material supported by the substrate (201).
Regarding claim 3, Cho discloses wherein the semiconductor material (205) comprises silicon ([0062]).
Regarding claim 7, Cho discloses wherein the pillar material comprises titanium ([0079]).
Regarding claim 8, Cho discloses wherein an aspect ratio of the pillar is between 10 to 1 and 4 to 1 ([0080]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Tseng (Tseng et al, “Electron Beam Lithography in Nanoscale Fabrication: Recent Development, “IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 26, NO. 2, APRIL 2003, pp. 141-149).
Regarding claim 2, Cho does not disclose applying a conductive layer to the photoresist layer prior to performing the lithography, wherein performing the lithography comprises performing electron beam lithography to form the pattern in the photoresist layer and remove the conductive layer.
Tseng however discloses applying a conductive layer (Fig. 9A) to the photoresist layer prior to performing the lithography, wherein performing the lithography comprises performing electron beam lithography to form the pattern in the photoresist layer (Abstract) and remove the conductive layer (Fig.9f).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Tseng to have apply a conductive layer to the photoresist layer prior to performing the lithography, wherein performing the lithography comprises performing electron beam lithography to form the pattern in the photoresist layer and remove the conductive layer for the purpose using lithography technique for fabrication patterns having nanometer feature sizes (Tseng, Abstract).
Claim(s) 4 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claims 1 above, and further in view of Smith (US 2020/0006073).
Regarding claim 4, Cho does not disclose wherein the hard mask layer comprises aluminum.
Smith however discloses that the hard mask layer comprises aluminum ([0054]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Smith to have the hard mask layer comprising aluminum because it is typical material for forming a hard mask (Smith, [0054]).
Regarding claim 15, Cho discloses the semiconductor material comprises silicon ([0062]) and the pillar material comprises titanium ([0079]).
Cho does not disclose wherein the hard mask layer comprises aluminum.
Smith however discloses that the hard mask layer comprises aluminum ([0054]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Smith to have the hard mask layer comprising aluminum because it is typical material for forming a hard mask (Smith, [0054]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Charlton (US 2012/0112165).
Regarding claim 5, Cho does not disclose wherein applying the pattern to the hard mask layer comprises ion milling the hard mask layer.
Charlton however discloses that applying the pattern to the hard mask layer comprises ion milling the hard mask layer ([0219].
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Charlton to apply the pattern to the hard mask layer by ion milling the hard mask layer because this is one of typical methods for applying pattern to the hard mask (Charlton, [0219]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Ting (US 6, 309, 977).
Regarding claim 6, Cho discloses wherein the planarizing comprises etching ([0080]).
Cho does not disclose that the etching is a plasma etching. Ting however discloses plasma etching process for planarization surfaces (column 7, lines 15-25).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Ting to perform plasma etching because this is a typical etch-back process for planarization.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Liao (US 2020/0020711).
Regarding claim 9, Cho does not disclose wherein a cross-sectional shape of the pillar is a polygon.
Liao however discloses wherein a cross-sectional shape of the pillar is a polygon ([0030]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Liao to have a cross-sectional shape of the pillar as a polygon for the purpose of optimizing design of the memory device (Liao, [0030]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as applied to claim 1 above, and further in view of Charlton (US 2012/0112165) and Ting (US 6, 309, 977).
Regarding claim 16, Cho discloses wherein the planarizing comprises etching ([0080]).
Cho does not disclose wherein applying the pattern to the hard mask layer comprises ion milling the hard mask layer.
Charlton however discloses that applying the pattern to the hard mask layer comprises ion milling the hard mask layer ([0219].
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Charlton to apply the pattern to the hard mask layer by ion milling the hard mask layer because this is one of typical methods for applying pattern to the hard mask (Charlton, [0219]).
Cho does not disclose that the etching is a plasma etching. Ting however discloses plasma etching process for planarization surfaces (column 7, lines 15-25).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Ting to perform plasma etching because this is a typical etch-back process for planarization.
Claims 10, 11, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Tsai (US 10, 546, 917).
Regarding claim 10, Cho discloses a fabrication method for a nanostructure material array, the fabrication method comprising: depositing a semiconductor material (Fig. 4A, numeral 205; [0062]) onto a substrate (201); applying a hard mask layer (206); applying a photoresist layer (207); performing lithography to form voids in the photoresist layer that form a pattern; (Fig.4A) applying the pattern to the hard mask layer based on the pattern in the photoresist layer (Fig.4B); etching the semiconductor material based on the pattern in the hard mask layer to form a plurality of cavities comprising a first cavity in the semiconductor material and a second cavity in the semiconductor material (Fig.4D),; performing atomic layer deposition to deposit pillar material into the first cavity and the second cavity, wherein the atomic layer deposition applies the pillar material to sidewalls of the first cavity and the second cavity such that the pillar material accumulates inwardly from the sidewalls until the first cavity and the second cavity are filled ([0079]); planarizing to remove the hard mask layer and pillar material disposed above a pillar height from a surface of the substrate (Fig.4E); and removing the semiconductor material to release a first pillar of the pillar material supported by the substrate and a second pillar of the pillar material supported by the substrate (Fig.4F).
Cho does not disclose the first cavity having a first cross-sectional dimension that is larger than a largest cross-sectional dimension of the second cavity.
Tsai however discloses the first cavity having a first cross-sectional dimension (Fig.2B, numeral 122) that is larger than a largest cross-sectional dimension of the second cavity (124).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Tsai to have the first cavity having a first cross-sectional dimension that is larger than a largest cross-sectional dimension of the second cavity for the purpose of preventing metal residue defects during the photolithography patterning process (Tsai, column 3, lines 9-15).
Regarding claim 11, Cho discloses wherein the first pillar has a first aspect ratio of between 4 to 1 and 10 to 1, the second pillar has a second aspect ratio of between 4 to 1 and 10 to 1 ([0080]).
Cho does not disclose that the first aspect ratio is different from the second aspect ratio.
Tsai however discloses that the first aspect ratio is different from the second aspect ratio (Fig.8B).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Tsai to have the first aspect ratio is different from the second aspect ratio for the purpose of preventing metal residue defects during the photolithography patterning process (Tsai, column 3, lines 9-15).
Regarding claim 13, Cho discloses wherein heights of the first pillar and the second pillar are the pillar height (Fig.4F).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Tseng as applied to claim 10 above, and further in view of Lu (US 2020/0058732).
Regarding claim 12, Cho does not disclose wherein the pattern defines a first cross-sectional shape for the first pillar and a second cross- sectional shape for the second pillar, and the first cross-sectional shape is different than the second cross-sectional shape.
Lu however discloses wherein the pattern defines a first cross-sectional shape for the first pillar and a second cross- sectional shape for the second pillar, and the first cross-sectional shape is different than the second cross-sectional shape ([0016]; Fig.7).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Lu to have wherein the pattern defines a first cross-sectional shape for the first pillar and a second cross- sectional shape for the second pillar, and the first cross-sectional shape is different than the second cross-sectional shape for the purpose of fabrication 3D capacitor based structure with increasing capacitance density (Lu, [0006]).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Cho in view of Tsai as applied to claim 10 above, and further in view of Tseng (Tseng et al, “Electron Beam Lithography in Nanoscale Fabrication: Recent Development, “ IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, VOL. 26, NO. 2, APRIL 2003, pp. 141-149).
Regarding claim 14, Cho does not disclose applying a conductive layer to the photoresist layer prior to performing the lithography, wherein performing the lithography comprises performing electron beam lithography to form the pattern in the photoresist layer and remove the conductive layer.
Tseng however discloses applying a conductive layer (Fig. 9A) to the photoresist layer prior to performing the lithography, wherein performing the lithography comprises performing electron beam lithography to form the pattern in the photoresist layer (Abstract) and remove the conductive layer (Fig.9f).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Cho with Tseng to have apply a conductive layer to the photoresist layer prior to performing the lithography, wherein performing the lithography comprises performing electron beam lithography to form the pattern in the photoresist layer and remove the conductive layer for the purpose using lithography technique for fabrication patterns having nanometer feature sizes (Tseng, Abstract).
Response to Arguments
Applicant's arguments filed 11/26/2025 have been fully considered but they are not persuasive.
Applicant’s arguments that Cho does not disclose performing lithography to form voids in the photoresist layer to form a pattern are not persuasive because Cho discloses forming voids to the photoresist layer (207) that form a pattern (Fig. 4A; [0074]). And forming pattern in the photoresist layer is a part of a conventional lithography process.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., various types of lithography as a printing process) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Applicant’s argument that Cho does not disclose performing atomic layer deposition to deposit pillar material into the cavity, wherein the atomic layer deposition applies the pillar material to sidewalls of the cavity such that the pillar material accumulates inwardly from the sidewalls until the cavity is filled are not persuasive because Cho discloses performing atomic layer deposition to deposit pillar material into the first cavity and the second cavity, wherein the atomic layer deposition applies the pillar material to sidewalls of the first cavity and the second cavity such that the pillar material accumulates inwardly from the sidewalls until the first cavity and the second cavity are filled ([0079]). Examiner also would like to not that lower electrode that is formed by atomic layer deposition as disclosed in [0079] is a pillar material (209) ([0080]). Thus, Cho discloses deposing pillar material into cavity by atomic layer deposition.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891